|Publication number||USRE41841 E1|
|Application number||US 11/208,132|
|Publication date||Oct 19, 2010|
|Filing date||Jun 8, 2000|
|Priority date||Jun 14, 1999|
|Also published as||EP1186024A1, EP1186024B1, US6607968, WO2000077846A1|
|Publication number||11208132, 208132, PCT/2000/1570, PCT/FR/0/001570, PCT/FR/0/01570, PCT/FR/2000/001570, PCT/FR/2000/01570, PCT/FR0/001570, PCT/FR0/01570, PCT/FR0001570, PCT/FR001570, PCT/FR2000/001570, PCT/FR2000/01570, PCT/FR2000001570, PCT/FR200001570, US RE41841 E1, US RE41841E1, US-E1-RE41841, USRE41841 E1, USRE41841E1|
|Inventors||Malgorzata Jurczak, Thomas Skotnicki|
|Original Assignee||Malgorzata Jurczak, Thomas Skotnicki|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Non-Patent Citations (1), Classifications (8), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention generally relates to a method of fabricating a silicon substrate having a thin buried silicon oxide layer (SOI substrate) and in particular to a method of this sort which makes it possible to produce an SOI substrate having a buried silicon oxide layer that is extremely thin and has excellent uniformity.
2. Description of the Related Art
The known techniques of fabricating an SOI substrate all have a number of drawbacks, in particular, a low production yield, a substrate quality which is still inadequate, and the production of a thin Si layer and a thin buried silicon oxide layer which are relatively thick and of mediocre uniformity.
A first method of fabricating an SOI substrate, known by the name of “SIMOX technology”, consists of forming the buried SiO2 layer in a silicon substrate by implanting oxygen at high dose followed by annealing at a temperature greater than 1300° C. A major drawback of this method is that it requires nonstandard equipment. Furthermore, the length of time for the process of implanting oxygen at high dose considerably reduces the production efficiency.
The substrates obtained by this method also suffer from inadequate quality of the buried silicon oxide layer and of the thin silicon layer (high pinhole density).
Finally, because the thin layers (thin Si layer and thin buried silicon oxide layer) are determined by the implantation process, this method makes it difficult to achieve thicknesses of less than 50 nm for the thin silicon layer and 80 nm for the buried SiO2 layer.
A second method, known by the name of “BESOI technique”, consists of forming a thin SiO2 film on a surface of a first silicon body, then bonding this first body to a second silicon body by means of the thin SiO2 film, and finally, removing part of one of the silicon bodies by mechanical grinding and polishing in order to form the thin silicon layer above the buried silicon oxide layer.
The silicon oxide layer on the first silicon body is formed by successively oxidizing the surface of this first body, then etching the oxide layer formed in order to obtain the desired thickness.
This method only allows relatively thick buried silicon oxide layers and silicon layers to be produced on the buried silicon oxide because of the poor control of the etching method. Furthermore, the thin layers obtained by this method have poor uniformity.
A third method, known by the name of “SMART CUT technology”, consists of forming, by oxidation, a thin silicon oxide layer on a first silicon body, then implanting H+ ions in the first silicon body in order to form a cavity plane in this first silicon body under the thin silicon oxide layer. Subsequently, by means of the thin silicon oxide layer, this first body is bonded to a second silicon body and then the assembly subjected to thermal activation in order to transform the cavity plane into a cleaving plane. This makes it possible to recover, on the one hand, an SOI substrate and, on the other hand, a reuseable silicon body.
This method requires the implantation of a high dose of hydrogen atoms. In spite of using atoms of smaller size for the implantation, the surface of the thin silicon layer obtained is also damaged. Furthermore, since the thickness of the thin silicon layer is defined by the implantation energy of the hydrogen atoms, it is difficult to make this thickness less than about 50 nm.
The methods above are described, in particular, in the article SOI: Materials to Systems, A. J. Auberton-Hervé, 1996, IEEE.
Therefore, a method of fabricating an SOI substrate, which overcomes the drawbacks of the methods of the prior art, may be desired.
In particular, a method of fabricating an SOI substrate which makes it possible to produce silicon oxide layers and silicon layers on the buried oxide layer that are very thin and of very good uniformity may be favorable.
A method of fabricating an SOI substrate that can be implemented in standard equipment may also be desired.
According to a first embodiment of the invention, the method of fabricating a silicon substrate having a thin buried silicon oxide layer includes:
According to a second embodiment of the invention, the method of fabricating a silicon substrate having a thin buried silicon oxide layer includes:
In a third embodiment of the invention, the method of fabricating a silicon substrate having a thin buried silicon oxide layer includes:
The thin buffer layers made of Ge and germanium-silicon alloys of the first element may be produced by epitaxial deposition. For example, the thin buffer layers are produced by well-known methods of vapor deposition or of molecular beam epitaxial deposition, such that the thin silicon layer may have a very small thickness of a few nanometers while still having a suitable uniformity, typically from 1 to 50 nm.
The thin buried oxide layer may be produced by a known thermal oxidation method, such that it is possible to obtain an oxide layer of very high quality with a virtually arbitrary thickness that can vary from 2 nm to 400 nm.
As is known per se, the bonding of the first and of the second elements can be carried out by using the Van der Waals forces. In order to increase the strength at the interface between the elements, the assembly can possibly be subjected to annealing.
The buffer layer of the first element may consist of pure germanium, of a silicon-germanium alloy or of a silicon-germanium alloy containing carbon. More particularly, Si1-xGex alloys (0<x<1) or Si1-x-yGexCy alloys (0<x≦0.95 and 0<y≦0.05) can be used.
As is known, the germanium and the Si1-xGex and Si1-x-yGexCy alloys have very high selectivity to chemical etching by solutions or to anisotropic plasma etching. In the case of silicon-germanium alloys, in order to obtain etching of high selectivity, it is preferable that the proportion of germanium in the alloy is at least equal to 10% by weight, and preferably equal to or greater than 30% by weight.
The use of the silicon-germanium alloy containing a small proportion of carbon makes it possible to reduce the high stresses between the silicon layers and the buffer layer. Thus, it is possible to use alloys with higher germanium concentrations and, consequently, with better etching selectivity, while producing a relaxation of the stresses. It is also possible to form a buffer layer made of a silicon-germanium alloy having a germanium concentration gradient (relaxed SiGe buffer layer). In this type of buffer layer, the germanium concentration increases from the silicon body of the first element.
It is thus possible to make relatively thick buffer layers, which can significantly increase the etching rate. Because of their thickness, the buffer layers may have a surface free of dislocations (all the dislocations and defects being located in the low part of the buffer layer), which provides good conditions and good continuity for the epitaxial growth of the thin single-crystal silicon layer which is to be deposited later.
In the SiGe alloy layer, the concentration profile of the germanium can be nonuniform. Thus, at the bottom of the layer, the Ge concentration can be 0%, then increase to 50% (or 70% and even 100%), and then decrease down to 0%. This solution makes it possible to avoid deformations in the upper silicon layer and to remove the thickness limitations. A high molar fraction of Ge in the SiGe alloy (in particular in the middle of the layer) provides, on the one hand, a very high selectivity of the etching method and, on the other hand, freedom from the risk of relaxation of the Si film.
The remainder of the description refers to the appended figures, which show:
With reference to
Typically, the buffer layer 2a and the silicon layer 3a have a thickness of from 1 to 50 nm. Thus a first element A is made, having a silicon body 1a with a main surface coated with a buffer layer 2a made of germanium, or of a germanium-silicon alloy, and with a thin silicon layer 3a, in that order.
Moreover, a thin silicon oxide layer 2b is formed on a silicon body 1b, distinct from the previous silicon body, by a conventional thermal oxidation method. This produces a second element B having a silicon body 1b, a main surface of which is coated with a thin silicon oxide layer 2b, as shown in FIG. 1b.
At this stage, the first element A and the second element B are bonded, as is shown in
The selective removal of the buffer layer 2a is then carried out, as shown in FIG. 1d. For example, a well-known oxidizing chemistry may be used, such as a solution comprising 40 ml of 70% HNO3+20 ml of H2O2+5 ml of 0.5% HF or by anisotropic plasma etching.
Once the buffer layer 2a is completely removed, a silicon substrate is obtained, as shown in FIG. 1e. The silicon substrate includes a buried silicon oxide layer 2b.
The SOI substrate obtained does not require additional polishing as is the case in the techniques of the prior art, in particular the techniques known as “BESOI” and “SMART CUT”.
Finally, the silicon body 1a is not lost and can be recycled to be used. For example, the silicon body 1a may be used as a silicon body for the fabrication of the elements A or B.
The second element B, shown in
The first element A and the second element B are then bonded as above, such that the silicon oxide layer 4a of the first element A is in contact with the silicon layer 2b of the second element B, as shown in FIG. 2c.
Although, in this case, the first element A and the second element B can be bonded by means of Van der Waals forces, it is preferable to subject the assembly to a thermal treatment so that the elements have a good mechanical bond. For example, the assembly can be heated to a temperature of 1000° C. for a duration of about 30 minutes (as in the BESOI technology).
The method is finished as above and as shown in
By proceeding in this way, it is possible to further improve the quality of the interface between the buried silicon oxide layer 4a, 2b, and the thin silicon layer 3a thereabove.
In another variant of the method of the invention, it is possible to proceed in the same way as described in connection with
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|U.S. Classification||438/455, 438/458, 438/457, 438/464|
|International Classification||H01L21/762, H01L21/30|
|Aug 26, 2009||AS||Assignment|
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Effective date: 20051128
|May 17, 2010||AS||Assignment|
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