|Publication number||USRE41842 E1|
|Application number||US 11/493,014|
|Publication date||Oct 19, 2010|
|Filing date||Jul 26, 2006|
|Priority date||Dec 5, 1996|
|Also published as||US5960317|
|Publication number||11493014, 493014, US RE41842 E1, US RE41842E1, US-E1-RE41842, USRE41842 E1, USRE41842E1|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (18), Non-Patent Citations (1), Classifications (25), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to methods of forming integrated circuits and more particularly, to methods of forming electrical interconnects on integrated circuit substrates.
A wiring layer in a semiconductor device functions to transmit signals and is typically connected to lower conduction layers via contact plugs. Contact plugs should typically be formed of low-resistivity metals in order to prevent signal delays.
Referring now to
Referring now to
It is therefore an object of the present invention to provide improved methods of forming electrical interconnects on integrated circuit substrates.
These and other objects, advantages and features of the present invention are provided by methods of forming electrical interconnects which include the steps of forming a first electrically conductive layer on a semiconductor substrate and then forming a first electrically insulating layer on the first electrically conductive layer. A second electrically insulating layer is then formed on the first electrically insulating layer. The second electrically insulating layer is then etched to expose the first electrically insulating layer and then a third electrically insulating layer is formed on the first electrically insulating layer. The first and third electrically insulating layers are then etched to define a contact hole therein which exposes a portion of the first electrically conductive layer. A barrier metal layer is then formed. The barrier metal layer is preferably formed to extend on the third electrically insulating layer and on the exposed portion of the first electrically conductive layer. The second electrically conductive layer is then formed to extend on the barrier metal layer and into the contact hole. The second electrically conductive layer and barrier metal layer are then polished in sequence to expose the third electrically insulating layer.
According to a preferred aspect of the present invention, the step of polishing the second electrically conductive layer and the barrier metal layer comprises the steps of polishing the second electrically conductive layer and the third electrically insulating layer simultaneously at a first rate and a second rate less than the first rate, respectively, using a first slurry, and then polishing the second electrically conductive layer and the third electrically insulating layer simultaneously at a third rate and a fourth rate greater than the third rate, respectively, using a second slurry. These polishing steps are preferably performed in an apparatus containing first and second polishing plates with the first and second slurries, respectively. According to another preferred aspect of the present invention, the step of forming a third electrically insulating layer is followed by the step of forming a trench having a first width in the third electrically insulating layer. According to this aspect of the present invention, the step of patterning the first and third electrically insulating layers comprises patterning the first and third electrically insulating layers to define a contact hole having a second width less than the first width, extending between a bottom of the trench and the first electrically conductive layer.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like numbers refer to like elements throughout.
Referring specifically to
Among the above materials forming the third insulating film 31, SiO2, undoped silicate glass (USG), boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), SiOF, SiN and SiON are deposited according to either a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced CVD (PECVD) method, and spin-on-glass (SOG), flowable oxide and insulating polymer are coated according to a spin coating method.
Next, a cleaning process is performed on the semiconductor substrate 21 using DI (De-Ionized) water in order to eliminate particles generated during the polishing process. This cleaning process may be performed by a polishing plate, to which a polishing pad used only for cleansing is attached, or in a dedicated cleaning apparatus.
The first insulating film 57 is formed by depositing an oxide material including silicon to a thickness of between 1000 and 100000 Å using a high density plasma (HDP) method wherein deposition and etching are simultaneously performed. At this time, a step difference is generated due to the wiring layer 55. SiO2, SiOF, boron phosphorus silicate glass (BPSG), etc. can be used as the oxide material including silicon. The second insulating film is formed by depositing silicon-on-glass (SOG) to a thickness of between 1000 and 100000 Å. However, any one selected among a flowable oxide, a photoresist and an insulating polymer can be used instead of SOG. Alternatively, the second insulating film can be formed by depositing any one of the above materials twice or more. At this time, a thermal treatment step is additionally performed after each of the depositing processes in order to improve the characteristics of the film material. The etching-back process is performed under a condition where the etching selectivity of the first insulating film 57 to the second insulating film is between 3 to 1 and 1 to 3. Consequently, the first insulating film 57 is planarized.
As compared to the conventional method wherein a spin scrubbing process is performed after a chemical and mechanical polishing (CMP) process, the planarizing method using the etching-back process is simple and reduces fabricating costs, as described more fully herein below. The third insulating film 59 is formed of either a single layer using any one selected among SiO2, undoped silicate glass (USG), boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), SiOF, SiN, SiON, spin-on-glass (SOG), a flowable oxide and an insulating polymer, or a multi layer formed by combining the single layers. At this time, the thickness of the entire third insulating film 59 is set between 10 and 100000 Å.
Among the above materials forming the third insulating film 59, SiO2, undoped silicate glass (USG), boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), SiOF, SiN or SiON may be deposited according to either a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced CVD (PECVD) method, and spin-on-glass (SOG), flowable oxide and insulating polymer may be deposited according to a spin coating method.
The trench 58 is for forming another wiring layer which is connected to the wiring layer 55. Referring to
The barrier layer 61 can be formed of a single layer of a refractory metal, e.g., titanium (Ti), titanium nitride (TiN) or tungsten nitride (WN) or a multi layer formed by combining the single layers, in addition to a titanium nitride (TiN)/titanium (Ti) structure. The low-resistance metal for the material layer 63 includes tungsten (W), aluminum (Al) and copper (Cu). In addition, the material layer 63 can be formed of any one material selected among low-resistance metal compounds such as polysilicon and tungsten silicon, aluminum copper compound and aluminum copper silicon compound.
Then, a second polishing process is performed using another slurry which is capable of polishing the third insulating film 59a at a faster rate than the material layer 63. The first and second polishing processes may be performed using respective first and second polishing plates in a polishing apparatus. At this time, the contact plug having a material layer 63a/barrier layer 61 a structure can be formed to a certain thickness by controlling the polishing time. Next, a cleaning process is performed on the semiconductor substrate 51 using DI (De-Ionized) water in order to eliminate particles generated during the polishing process. This cleaning process may be performed by a polishing plate to which a polishing pad used only for cleansing is attached, or in a cleaning apparatus.
As described above, in the contact plug forming method for a semiconductor device according to the present invention, the insulating film is planarized using an etching-back method instead of a CMP process, and the material layer and the insulating film for forming a contact plug are consecutively polished using a CMP apparatus including at least two polishing plates. Therefore, the process is simplified, the planarization degree is improved, and a contact plug and another wiring layer can be simultaneously formed.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5494854||Aug 17, 1994||Feb 27, 1996||Texas Instruments Incorporated||Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films|
|US5578523 *||May 18, 1995||Nov 26, 1996||Motorola, Inc.||Method for forming inlaid interconnects in a semiconductor device|
|US5607880 *||Apr 28, 1993||Mar 4, 1997||Nec Corporation||Method of fabricating multilevel interconnections in a semiconductor integrated circuit|
|US5663102||Jul 29, 1996||Sep 2, 1997||Lg Semicon Co., Ltd.||Method for forming multi-layered metal wiring semiconductor element using cmp or etch back|
|US5783485||Jul 19, 1996||Jul 21, 1998||Motorola, Inc.||Process for fabricating a metallized interconnect|
|US5786275||May 30, 1997||Jul 28, 1998||Nec Corporation||Process of fabricating wiring structure having metal plug twice polished under different conditions|
|US5840625||Oct 4, 1996||Nov 24, 1998||Siemens Aktiengesellschaft||Method of fabricating integrated circuit interconnection employing tungsten/aluminum layers|
|US5858875||Nov 13, 1996||Jan 12, 1999||National Semiconductor Corporation||Integrated circuits with borderless vias|
|US5880018||Oct 7, 1996||Mar 9, 1999||Motorola Inc.||Method for manufacturing a low dielectric constant inter-level integrated circuit structure|
|US5882999 *||Aug 5, 1996||Mar 16, 1999||International Business Machines Corporation||Process for metallization of an insulation layer|
|US5920790 *||Aug 29, 1997||Jul 6, 1999||Motorola, Inc.||Method of forming a semiconductor device having dual inlaid structure|
|US6100184 *||Aug 20, 1997||Aug 8, 2000||Sematech, Inc.||Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer|
|US6329284 *||Aug 25, 1997||Dec 11, 2001||Mitsubishi Denki Kabushiki Kaisha||Manufacturing process of a semiconductor device|
|JPH07135252A||Title not available|
|JPH07142465A||Title not available|
|JPH07283177A||Title not available|
|JPH08124886A||Title not available|
|JPH08288391A||Title not available|
|U.S. Classification||438/633, 438/626, 438/691, 438/627, 438/629, 438/637, 438/645, 257/E21.576, 438/631, 438/692|
|International Classification||H01L21/321, H01L21/28, H01L21/3105, H01L21/316, H01L21/768, H01L21/4763|
|Cooperative Classification||H01L21/31625, H01L21/76819, H01L21/7684, H01L21/31612, H01L21/31629, H01L21/3212, H01L21/31053|
|European Classification||H01L21/768C2, H01L21/768B4|