|Publication number||USRE42037 E1|
|Application number||US 12/426,884|
|Publication date||Jan 18, 2011|
|Filing date||Apr 20, 2009|
|Priority date||Dec 14, 2001|
|Also published as||CN1605148A, CN100405722C, CN101335487A, DE10297493T5, US6765372, US20030111984, USRE40915, WO2003052911A1, WO2003052911A8|
|Publication number||12426884, 426884, US RE42037 E1, US RE42037E1, US-E1-RE42037, USRE42037 E1, USRE42037E1|
|Inventors||Robert Haynes Isham|
|Original Assignee||Intersil Americas Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Classifications (16), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application claims the benefit of co-pending U.S. Provisional Patent Application, Serial No. 60/340,324, filed Dec. 14, 2001, entitled: “Continuous Control Temperature Compensated Current Sensing Technique for DC to DC,” by R. Isham, assigned to the assignee of the present application and the disclosure of which is incorporated herein.
Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,765,372. The reissue applications are reissue application Ser. No. 11/488,927 (the parent reissue); and reissue application Ser. No. ( 12/426,884 ) (the present, continuation reissue application). Both Reissue applications are reissues of the same U.S. Pat. No. 6,765,372.
This reissue application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/340,324, filed Dec. 14, 2001.
The present invention relates in general to electronic circuits and components therefor, and is particularly directed to a new and improved current-sensing and correction circuit with programmable, continuous compensation for temperature variations of an output switching MOSFET of a buck mode DC—DC converter.
Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current (DC) power sources, such as a buck-mode, pulse width modulation (PWM) based, DC—DC converter of the type diagrammatically shown in FIG. 1. As shown therein, a controller 10 supplies a PWM signal to a (MOSFET gate) driver 20, for controlling the turn-on and turn-off of a pair of electronic power switching devices, to which a load is coupled. In the illustrated DC—DC converter, these power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device 30, and a lower (or low side) power NFET device 40, having their drain-source current flow paths connected in series between a pair of power supply rails (e.g., VIN and ground (GND)).
The upper NFET device 30 is turned on and off by an upper gate switching signal UGATE being applied to its gate from driver 20, and the lower NFET device 40 is turned on and off by a lower gate switching signal LGATE from driver 20. A common node 35 between the upper and lower NFETs is coupled through an inductor 50 (which may typically comprise a transformer winding) to a load reservoir capacitor 60 coupled to a reference voltage terminal (GND). A connection 55 between inductor 50 and capacitor 60 serves as an output node from which a desired (regulated) DC output voltage Vout is applied to a LOAD 65 (shown as coupled to GND).
The output node connection 55 is also fed back to error amplifier circuitry (not shown) within the controller, the error amplifier being used to regulate the converter's output DC voltage relative to a reference voltage supply. In addition, the common node 35 is also coupled to current-sensing circuitry 15 within controller 10, in response to which the controller adjusts the PWM signal, as necessary, to maintain the converter's DC output within a prescribed set of parameters.
For this purpose, the controller may incorporate a current-sensing circuit of the type described in U.S. Pat. No. 6,246,220, entitled: “Synchronous-Rectified DC to DC Converter with Improved Current Sensing,” issued Jun. 12, 2001, by R. Isham et al, assigned to the assignee of the present application and the disclosure of which is incorporated herein. As described therein, the controller monitors the source-drain current flowing through the lower NFET 40 by way of a current-sensing or scaling resistor 37 electrically interconnected between node 35 and an current-sensing circuit 15.
The current-sensing circuit is operative to monitor the current ISENSE flowing through scaling resistor 37. This current is the product of the output current IOUT flowing from the common node 35 to the inductor 50 times the ratio of the ON-resistance RDS40ON of the lower NFET 40 to the resistance R37 of the scaling resistor 37, and is thus proportionally representative of the output current IOUT. The load current IL, namely the current I50 flowing through the inductor 50, is substantially equal to the output current IOUT minus the current ISENSE flowing through the scaling resistor 37.
As the ratio of RDS40ON to R37 is typically relatively small, the current ISENSE will be substantially smaller than the output current IOUT, so that the output current IOUT and the load current IL will have substantially similar magnitudes, making ISENSE representative of load current. The resistance of the scaling resistor 37 is selected to provide a prescribed value of current flow for the values of load current IL and/or the value of the ON-state resistance RDS40ON of the lower NFET 40. Thus, the sensitivity or magnitude of, for example, voltage droop, current limiting or trip, and current balancing incorporated into the DC/DC converter is effectively ‘scaled’ by selecting resistor 37 relative to the value of the on-state resistance RDS40ON of the lower NFET 40. Moreover, the voltage drop across the on-state resistance RDS40ON of the lower NFET 40 (usually negative) is accommodated in the converter without a negative voltage supply. In addition, since the ON-resistance RDS40ON of the lower NFET 40 varies with temperature, scaling resistor 37 must be selected to have a temperature coefficient which offsets the behavior of NFET 40. This may be accomplished by replacing scaling resistor 37 with a network of resistors and positive temperature coefficient thermistors.
As shown in greater detail in
In operation, the sense amplifier 200 and NFET 210 (which serves as a controlled impedance) are operative to continuously drive the controller's SENSE+ port 11 toward ground potential. This forces the end of the current feedback resistor 37 which is connected to controller SENSE+ port 11 to be at ground potential and the end connected to common node 35 to have a negative voltage. The negative voltage at common output node 35 will be equal to the product of the output current IOUT and the on-state resistance RDS40ON between the drain and source of the lower NFET 40.
Current from the sample and hold circuit 220 flows into the drain and out of the source of NFET 210 into the SENSE+ port 11. Also flowing into the SENSE+ port 11 from the opposite direction is the current ISENSE which, as described above, is representative of load current IL. In order to maintain the SENSE+ port 11 at ground potential, sense amplifier 200 adjusts the current flowing through NFET 210 and into SENSE+ port 11 to be substantially equal to ISENSE. Since ISENSE is representative of the load current IL, the current flowing through NFET 210 and into SENSE+ port 11, as controlled by sense amplifier 200, is also representative of load current IL.
Within the controller 10, sampling control circuitry periodically supplies a sampling control signal to the sample-and-hold circuit 220, when NFET 210 is in its ON (conducting) state. In response to this sampling control signal, the sample-and-hold circuit 220 samples the current flowing through NFET 210 and stores the sampled value on capacitor 260 via node 236. Thus, the sampled current value acquired by the sample-and-hold circuit 220 is also representative of load current IL. This sampled value of sensed current is coupled from the sample and hold circuit's output port 223 to the controller's error amplifier circuitry that monitors the output node 55.
As pointed out above, the scaling resistor 37 that couples the common node 35 to the controller's SENSE+ port 11 must have a temperature coefficient that offsets the behavior of the on-state resistance RDS40ON of the lower NFET 40 (which varies with temperature and may be as high as forty percent over a typical operating range). As a result, it is customary to employ some form of complicated and costly feedback network in place of resistor 37.
In accordance with the present invention, the above-discussed temperature variation problem is successfully addressed by a new and improved current-sensing and correction circuit, containing programmable temperature compensation circuitry and being configured to be incorporated into a DC—DC converter, such as the buck mode architecture of the type shown in
The front end portion of each embodiment of the invention includes sense amplifier, NFET and sample-and-hold components described above with reference to FIG. 2. In addition to providing the sampled sense current to the sample-and-hold output terminal, an auxiliary output of the sample-and-hold circuit supplies a copy of the sampled sense current to a programming resistor having a programmable resistance. The voltage produced across the programming resistor is coupled to respective high temperature compensation (HIGHtc) and low temperature compensation (LOWtc) auxiliary sense amplifiers.
The output of the HIGHtc auxiliary sense amplifier controls a HIGHtc NFET, the drain-source path of which is coupled to a HIGHtc scaling resistor. The temperature coefficient of resistance of the HIGHtc scaling resistor is higher than that of a LOWtc scaling resistor in the source-drain path of a LOWtc NFET at the output of the LOWtc auxiliary sense amplifier. The source-drain path of the HIGHtc NFET is coupled to a current mirror, which supplies a copy of the current in the source-drain path of the HIGHtc NFET to summing node, that serves as the output of the current-sensing and correction circuit. The summing node combines the HIGHtc and LOWtc currents and the sensed current to produce a “temperature-corrected” output current that is coupled to the controller's error amplifier circuitry in place of the sensed current.
Since the temperature coefficient of the HIGHtc scaling resistor is larger than the temperature coefficient of the LOWtc scaling resistor, the ratio of the resistance of the HIGHtc resistor to that of the programming resistor will have a larger slope with temperature than the ratio of the resistance of the LOWtc resistor to that of the programmiong resistor. As a result, the contribution of the HIGHtc current flowing into the output node will decrease with increasing temperature faster than the contribution of the LOWtc current flowing out of the output node, so that the composite corrected current will decrease with increase in temperature.
For temperatures greater than a HIGHtc/LOWtc current-equality temperature, at which point the HIGHtc and LOWtc resistors are equal, the ratio of the corrected current to the sensed current will be less than 1.0; for temperatures below this current-equality temperature, the ratio of the corrected current to the sensed current will be greater than 1.0. Namely, the temperature-compensating relationship of the corrected current to the sensed current is such that the ratio of corrected current to sensed current follows a deterministic curve at temperatures other than said predetermined temperature. It should be noted that the amount of temperature compensation is set by the programming resistor.
In a second embodiment, the first embodiment is modified to substitute an additional gain stage for the current mirror that supplies the replicated HIGHtc current to the output/summing node. This provides more temperature dependence for given values of thermal coefficients of resistance.
Before describing a number of embodiments of the current-sensing circuit of the invention, which provides programmable, continuous compensation for variations in the operational temperature of an output switching MOSFET of a buck mode DC—DC converter, it should be observed that the invention resides primarily in an arrangement of conventional DC power supply circuit and control components, and the manner in which they are integrated together to realize a temperature-compensated power supply architecture of the type described briefly above.
It will also be appreciated that the invention may be embodied in a variety of other implementations, and should not be construed as being limited to only those shown and described herein. For example, although the non-limiting circuit implementations of the Figures shows the use of MOSFET devices, it is to be understood that the invention is not limited thereto, but also may be configured of alternative equivalent circuit devices, such as bipolar transistors, for example. The implementation examples to be described are intended to furnish only those specifics that are pertinent to the present invention, so as not to obscure the disclosure with details that are readily apparent to one skilled in the art having the benefit of present description. Throughout the text and drawings like numbers refer to like parts.
Attention is now directed to
Within the front end circuitry 300 of the temperature compensated sense amplifier, a sample value storage node 224 of the sample-and-hold circuit 220 is connected to a sampled value storage capacitor 260, which is switchably coupled (via switching unit 231) to input node 221, so that it may receive and store a sampled value of the sensed current. Node 224 is further coupled to the gate of an output PMOSFET 250 that supplies the sampled sense current ISENSE to the sample-and-hold output terminal 223, and additionally to the gate of an auxiliary output PMOSFET 227, that supplies a copy of the sample sense ISENSE current to an auxiliary output terminal 228.
This copy of the ISENSE current provided by the auxiliary output terminal 228 is coupled to a programming resistor 310, referenced to ground and having a programmable resistance rPROGRAM. (Ideally, the temperature coefficient of the programming resistor 310 is zero or very close to zero). The programming resistor is used to change the slope of a deterministic curve, such as that shown in
The voltage produced across the programming resistor 310 at node 228 is coupled to each of a first, non-inverting (+) input 321 of a first auxiliary sense amplifier 320, and to a first, non-inverting (+) input 331 of a second auxiliary sense amplifier 330. The first auxiliary sense amplifier 320 has its second, inverting (−) input 322 coupled to a node 324 between a first, ‘HIGHtc’ scaling resistor 325 and the source-drain current flow path of an NFET 340.
NFET 340 has its gate coupled to the output 323 of the first auxiliary sense amplifier 320. Scaling resistor 325, which is coupled to ground, has a first prescribed scaling resistance value rHIGHtc, that serves to reduce the ratio of a composite, temperature compensated, or corrected, output current ICORRECTED to the ISENSE current at temperatures above a predetermined temperature. In the present example, the temperature coefficient of resistance of the scaling resistance 325 is higher than the temperature coefficient of resistance of a second scaling resistor 335, to be described.
The source-drain path of NFET 340 is coupled to the source-drain path of a current mirror PFET 350, which is referenced to the VCC voltage rail. NFET 340 is controlled by the first auxiliary sense amplifier 320 to produce a first fractional, or scaled, version of sense current ISENSE as a first temperature compensation current IHIGHtc, that is combined with the sense current ISENSE and a second temperature compensation current ILOWtc, to realize the temperature corrected, output current ICORRECTED, as will be described.
PFET 350 is coupled in current-mirror configuration with PFET 360, which has its source-drain path referenced to the VCC voltage rail, and coupled via an output node 365 to the source-drain path an NFET 370. As result, the source-drain path of current mirror PFET 360 mirrors the ‘high’ temperature coefficient compensation current IHIGHtc (flowing through the scaling resistor 325 and the source-drain path of PFET 350) and couples this current to the output node 365.
Output node 365, from which the ‘corrected’ sense current ICORRECTED is derived, is coupled in common with the output port 223 of the sample and hold circuit 220. NFET 370 has its source-drain path coupled to a node 334 between a second, ‘LOWtc’ scaling resistor 335 and the source-drain current flow path of an NFET 370. Scaling resistor 335 is coupled to ground. Node 334 is coupled to an inverting (−) input 332 of the second auxiliary amplifier 330. As pointed out above, in the present example, the temperature coefficient of resistance of the scaling resistance 335 is lower than the temperature coefficient of resistance of a scaling resistor 325.
Similar to NFET 340, NFET 370 is controlled by the output of the second auxiliary sense amplifier 330 to produce a second scaled version of the sense current ISENSE as a second temperature compensation current ILOWtc. This second temperature compensation current is combined at output port 365 with the sense current ISENSE and the first temperature compensation current IHIGHtc, to realize the temperature corrected, output current ICORRECTED.
In operation, the copy of the current ISENSE provided by auxiliary output 228 flows through programming resistor 310 to produce a voltage VrPROGRAM across the programming resistor. This voltage is applied to the non-inverting (+) inputs of each of the auxiliary sense amplifiers 320 and 330. In response to this voltage, the first auxiliary amplifier 320 drives the gate of NFET 340, to produce a source-drain current IHIGHtc, that flows through scaling resistor 325; in a like manner, the second auxiliary amplifier 330 drives the gate of NFET 370, to produce a source-drain current ILOWtc, that flows through scaling resistor 335.
The value of the drain-source current IHIGHtc through NFET 340 is proportional to the current ISENSE in accordance with the ratio of the resistance (rPROGRAM) of the programming resistor 310 (through which the current ISENSE flows) and the resistance rHIGHtc of the scaling resistor 325 (through which the current IHIGHtc flows). Namely, IHIGHtc=ISENSE*(rPROGARM/rHIGHtc). Similarly, the value of the drain-source current ILOWtc through the NFET 370 is proportional to the current ISENSE in accordance with the ratio of the resistance (rPROGRAM) of the programming resistor 310 and the resistance rLOWtc of the scaling resistor 335 (through which the current ILOWtc flows). Namely, ILOWtc=ISENSE*(rPROGRAM/rLOWtc).
The two currents IHIGHtc and ILOWtc are set at the same value for a particular operating temperature (such as 25° C.). Since current mirror PFET 360 is operative to mirror the temperature compensation current IHIGHtc in the source-drain path of PFET 350 in accordance with the operation of NFET 340, the output node 365 is supplied with three current components: 1—the sense current ISENSE from port 223 of the sample and hold circuit 220; 2—the current IHIGHtc mirrored by PFET 360; and 3—the current ILOWtc produced by NFET 370. Due to the directions of current flow of these three current components relative to output node 365, a composite temperature-compensated output current ICORRECTED can be defined as:
This temperature-compensated current ICORRECTED is coupled to the controller's error amplifier circuitry in place of the sensed current ISENSE, as described above.
Since the temperature coefficient of resistance of resistor 325 is greater than the temperature coefficient of resistance of resistor 335, the ratio of the resistance of resistor 325 to the resistance of programming resistor 310 will increase with temperature faster than the ratio of the resistance of resistor 335 to the resistance of programming resistor 310. As a result, as the temperature increases, the contribution of the current component IHIGHtc into node 365 will decrease faster than the contribution of the current ILOWtc away from node 365, so that the composite current ICORRECTED will decrease.
Thus, for temperatures greater than the current-equality (IHIGHtc=ILOWtc) temperature, ICORRECTED/ISENSE will be less than 1.0, while for temperatures below the current-equality (IHIGHtc=ILOWtc) temperature, ICORRECTED/ISENSE will be greater than 1.0, as shown.
This modified architecture operates in the same manner as current mirror PMOSFETs 350 and 360, but modifies the current output of PMOSFET 520 dependent on temperature.
Resistance rHIGHtc2 has a higher thermal coefficient of resistance than resistance rLOWtc2. At some reference temperature, such as the temperature at which resistance rHIGHtc and resistance rLOWtc are equal, as described above, resistance rHIGHtc2 and resistance rLOWtc2 are equal. At this temperature, the current through the resistance rHIGHtc 325, and NMOSFET 340 into resistance rLOWtc2 530 is replicated by PMOSFET 520 through resistance rHIGHtc2 540. As the temperature increases above this point, the ratio of rHIGHtc2/rLOWtc2 increases and, conversely, the current out of PMOSFET 520 decreases. The current out of PMOSFET 520, or IHIGHtc, becomes equal to: ISENSE*(RPROGRAM/RHIGHtc)*(RLOWtc2/RHIGHtc2).
As described above, the current out of NMOSFET 370, or ILOWtc, is ISENSE*(RPROGRAM/RLOWTC).
The corrected current is ISENSE+IHIGHtc−ILOWtc, or
This gives a higher rate of change with temperature compared to the first embodiment, which is:
It may be noted that additional gain stages such as gain stage 500 may be added for additional increases in thermal gain.
This temperature-compensated current ICORRECTED is coupled to the controller's error amplifier circuitry in place of the sensed current ISENSE, as described above.
As will be appreciated from the foregoing description, the inability of a simple scaling resistor installed between the common node of a DC—DC converter to a controller sense port to provide compensation for the temperature-responsive behavior of the on-state resistance of the lower NFET in the converter, (which may be as high as forty percent over a typical operating range), is successfully addressed by the current-sensing circuit of the invention, which provides programmable, continuous compensation for temperature variations of an output switching MOSFET of a buck mode DC—DC converter.
By coupling copies of the sampled current, that has been sensed through a sense resistor coupled to the common MOSFET node of the DC—DC converter, to prescribed programming and scaling resistors coupled to high and low auxiliary sense amplifiers, which drive ‘high’ temperature coefficient (hightc’) and ‘low’ temperature coefficient (‘lowtc’) associated, controlled ‘hightc’ and ‘lowtc’ current paths, a corrected current can be derived as a combination of the sensed current and the controlled ‘hightc’ and ‘lowtc’ currents. Due to the directions of current flow of these three current components relative to output the node, a composite temperature-compensated output current ICORRECTED can be defined in as:
ICORRECTED=ISENSE−ILOWtc+IHIGHtc or, in terms of the resistors, as:
Thus the ratio of ICORRECTED to ISENSE can be written as:
In a second embodiment an additional gain stage is inserted in place of the current mirror circuitry that is used to supply the replicated current component IHIGHtc to the output node, so that the output current of the PMOSFET is modified in dependence on temperature. The corrected current is ISENSE+IHIGHtc−ILOWtc, or
As noted above, this gives a higher rate of change with temperature compared to the first embodiment, as:
The temperature-compensated current ICORRECTED is coupled to the controller's error amplifier circuitry to track the temperature variations in the drain-source resistance of the lower MOSFET of the converter.
While I have shown and described several embodiments in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art. I therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.
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|U.S. Classification||323/224, 323/907, 323/288, 323/284|
|International Classification||G05F1/613, G05F1/455, G05F1/10, H02M3/155, H02M3/158|
|Cooperative Classification||Y10S323/907, G01R19/0092, H02M2001/0009, G01R31/40, H02M3/156|
|European Classification||H02M3/156, G01R31/40|
|May 5, 2010||AS||Assignment|
Owner name: MORGAN STANLEY & CO. INCORPORATED, NEW YORK
Effective date: 20100427
Free format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC.;AND OTHERS;REEL/FRAME:024335/0465
|Oct 8, 2010||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ISHAM, ROBERT HAYNES;REEL/FRAME:025115/0650
Owner name: INTERSIL AMERICAS INC., CALIFORNIA
Effective date: 20021125
|Jan 20, 2012||FPAY||Fee payment|
Year of fee payment: 8
|Jun 10, 2014||AS||Assignment|
Effective date: 20111223
Free format text: CHANGE OF NAME;ASSIGNOR:INTERSIL AMERICAS INC.;REEL/FRAME:033119/0484
Owner name: INTERSIL AMERICAS LLC, CALIFORNIA