|Publication number||USRE42066 E1|
|Application number||US 11/040,608|
|Publication date||Jan 25, 2011|
|Priority date||Apr 22, 1994|
|Also published as||USRE38918|
|Publication number||040608, 11040608, US RE42066 E1, US RE42066E1, US-E1-RE42066, USRE42066 E1, USRE42066E1|
|Inventors||Lars G. Svensson, William C. Athas, Jeffrey G. Koller|
|Original Assignee||University Of Southern California|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (69), Non-Patent Citations (47), Referenced by (2), Classifications (5), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This Reissue Application, Reissue application Ser. No. 08/986,327, and Reissue application Ser. No. 09/758,631 are all three reissue applications of U.S. Pat. No. 5,473,526, issued Dec. 5, 1995. This application is a continuation of Reissue application Ser. No. 09/758,631, filed Jan. 10, 2001 (now issued as U.S. Reissue Pat. No. RE 38,918, issued Dec. 13, 2005 ), entitled “System And Method For Power-Efficient Charging And Discharging Of A Capacitive Load From A Single Source”, which is a continuation of application Ser. No. 08/986,327, entitled “System And Method For Power-Efficient Charging And Discharging Of A Capacitive Load From A Single Source,” filed Dec. 5, 1997 (now issued as U.S. Reissue Pat. No. RE 37,552, issued Feb. 19, 2002 ).
This invention was made with government support under DABT- 63 - 92 -C- 0052 awarded by ARPA. The government has certain rights in the invention.
1. Field of the Invention
The present invention relates to electronic circuits and systems. More specifically, the present invention relates to power dissipation in electronic circuits and systems.
2. Description of the Related Art
Power dissipation of electronic circuitry is an important design consideration for many applications. Power dissipation provides a measure of the efficiency of the system. The efficiency of the system impacts the design of the power supply for the system. That is, low efficiency leads to higher costs due to the waste of energy and the need for larger power supplies.
For battery powered systems, power dissipation limits battery life. This necessitates larger batteries which increases the cost and weight of the system while limiting the applicability thereof. As an example, consider coronary pacemakers where power dissipation is a critical concern due to the difficultly of accessing the battery for replacement and the cost and inconvenience associated with the use of larger batteries.
In addition, the dissipated energy is released in the form of heat. Accordingly, systems which exhibit considerable power dissipation often require measures such as heat sinks to protect or cool system components from the heat created by the circuit. The use of heat sinks and the like adds to the cost, size and weight of the system and thereby limits the utility of same.
For the CMOS (complementary-metal-oxide semiconductor) based system, used widely in the design of computers, digital logic circuits and the like, capacitive effects are primarily responsible for the dissipation of power. Such capacitive effects arise due to junction capacitances within semiconductor devices, interlead capacitances between lines connecting the circuit to external devices and the capacitance of a load.
In accordance with conventional teachings, power dissipation is directly related to the operating frequency (f), the capacitance (C) and the square of the voltage (V2) applied to the capacitive element.
In addition to the elimination of unnecessary capacitances and the reduction of the switching frequency to the lowest value that supports the functional specification of the circuit, most prior approaches to the problem have focused on reducing the voltage applied to the capacitive elements. However, in addition to costly interfacing issues, attempts to lower the voltage of digital processors and the like have been limited by the fact that the trend is to higher processing speeds which cannot be attained at arbitrarily low operating voltages.
Thus, there is an ongoing need in the art for a system and technique for minimizing the power dissipated by a digital system.
The need in the art is addressed by the present invention which, in a most general sense, provides a system and method for efficiently charging and discharging a capacitive load from a single voltage source. The inventive system includes a first switch for selectively connecting the voltage source to the load and a second switch for selectively providing a short across the load as may be common in the art. A particularly novel aspect of the invention resides in the provision of plural capacitive elements and a switching mechanism for selectively connecting each of the capacitive elements to the load whereby the load is gradually charged or discharged.
In the illustrative embodiment, the switching mechanism includes a set of switches for selectively connecting each of the capacitive elements to the capacitive load and a switch control mechanism for selectively activating the switches.
Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof.
Most of the power dissipation in digital CMOS circuits is due to repeated charging and discharging of capacitive loads including those internal to the circuit and those associated with the output signals.
Econv=QV′=CV (V/2)=CV2/2 
A similar argument applies to the discharge process, so a complete conventional charge-discharge cycle dissipates all the energy provided by the power supply, QV=CV2.
In accordance with the present teachings, power dissipation is reduced by charging the capacitance of the load CL in several steps. This is illustrated in FIG. 2.
If N steps are used, the dissipation per step is again given by the transferred charge and the average voltage drop across the switch resistance:
Estep=QV′=(CV/N) (V/2N)=CV2/2N2 
To charge the capacitance all the way to the supply voltage V, N steps are used, so the total energy dissipation is:
Estepwise = N*Estep 
Again, a full charge-discharge cycle will cause twice the dissipation of the charging only. Thus, according to this simplified analysis, charging by several steps reduces the energy dissipation per charge-discharge cycle and thereby the total power dissipation, by a factor of N.
The multiple supply voltages of
Timing signals are provided by a system clock (not shown) through the latch 22. In practice, the clock rate should be at least (N+1) times the output signal rate. In the preferred embodiment, switches 0-4 are implemented with n-channel MOSFET devices. Switches 5 and 6 are implemented with p-channel devices.
The operation of the circuits of
On the trailing edge of input pulse, a discharge cycle is initiated by when the switches are momentarily closed in reverse order. Thus, switch N is opened and switch N−1 is closed. Then switch N−1 is opened and switch N−2 is closed and etc. On the closure of switch N−1, the associated tank capacitor will receive most of the charge on the load capacitance. Each capacitor down the line will receive a lower charge than the immediately proceeding capacitor. After switch 1 opens, switch 0 closes to complete the cycle dumping the remaining charge on the load CL to ground. Thus, over several cycles the tank capacitors will approach their steady state voltages, for example, the (N−1) th through 1st tank capacitors may have charges of say 5, 4, 3, 2 and 1 volts respectively. Then, at the beginning of the next cycle, on the closure of the first switch, the voltage on the first tank capacitor is applied to the load, then the voltage on the second capacitor is applied to the load and so on. Thus, in the example, first 1 volt is applied to the load, then 2 volts, then three volts and etc. As a result, the voltage on the load will gradually increase as shown in FIG. 5(j).
The circuits of
Since the tank capacitors are much larger than the load, the tank voltages do not change significantly, so the dissipation in the switches will be the same as for the case in
The voltages of the tank capacitor bank are self-stabilizing. To appreciate this, assume that the voltage of one of the tank capacitors is slightly higher than it should be. Then, the charge delivered by this tank capacitor during the charging of the load will be somewhat larger than that given by equation , since the “step” from the voltage below is now slightly larger. During the discharge phase, the step from the voltage above is slightly smaller and the charge received is therefore smaller as well. Therefore, over the full cycle, a net decrease of the charge on the storage capacitor occurs, which causes a decrease in the capacitor voltage. The initial deviance is automatically counteracted.
Even if the tank capacitor voltages differ from the “correct” values, the circuit will work logically correctly, since each charging (discharging) cycle ends by connecting the load to he supply rail (ground). Voltage deviations simply bring higher dissipation. This happens during start-up, before the tank voltages have had time to converge to the even distribution between the supply voltage and ground.
The implementation cost of a driver such as that shown in
The problem of maintaining the appropriate voltages on the tank capacitors is obviated by the fact that the capacitor voltages will converge automatically to the desired voltages. No additional circuitry is required. Only one supply line must be routed to the chip and the power supply need not be any more complicated than a conventional supply. In practice, the tank capacitors would be located off-chip.
For a CMOS implementation, the following design procedure may be followed to provide a driver configuration which exhibits minimal power dissipation.
Equation  indicates that dissipation decreases monotonically with increasing N. The number N cannot, however, be usefully made arbitrarily large because each step requires that a switch be turned on and off, which itself causes dissipation. Also, the energy used to drive each switch depends on the width of the device, which should be just enough to allow the charging to complete before the next step commences. Thus, for a given total allowable charging time ‘T’, there is an optimal number of steps and a set of optimal device sizes which lead to minimal total dissipation determined as follows.
Again, consider the circuit in FIG. 3 and assume the gates of the switch devices are driven conventionally. The load is charged and discharged once; the energy needed to drive the gates of the switch devices is:
Allot each step one Nth of the total charging time T. Then:
Here, m is the number of RC time constants spent waiting for each charging step to complete. From equation , it is evident that all the switch devices should have equal on-resistance: Ri=Rsw. Decreasing the on-resistance of device i by increasing the width means increasing the gate capacitance:
ρi is a quality measure of the switch. It varies with i, since the bulk-to-channel and gate-to-channel voltages are different for different switches. Combining equations , , and  yields:
If N is sufficiently large,
The number N that minimizes Etot is given by:
The corresponding energy dissipation is:
It remains to select the value for m. If it is chosen too small, there will still be a significant voltage across a switch when the next switch is to close. Hence, there is an increase in the average voltage across each switch and therefore a dissipation increase (the first term in equation  is changed slightly). If on the other hand, m is chosen unnecessarily large, time is wasted that could have been used to increase the number of steps. Thus, in general, optimization methods for the value of m vary according to the application, however, one skilled in the art will be able to select a suitable value for m using conventional teachings (e.g., a simulation program).
By using the number of stages given by equation , the designer can minimize the power dissipation of the driver. The minimum is rather shallow, however, so a lower N (as would most often be dictated by practical considerations) will still give a considerable improvement over the conventional case; N=2 already gives almost 50% reduction. Once N and m have been selected, the on-resistance of each switch is given by equation . The corresponding gate capacitance, and thereby the width of the device, is given by equation . The values of ρ for a certain process can be found by circuit simulation or by measuring the on-resistances of test devices of known widths.
Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications applications and embodiments within the scope thereof. For example, the switches may be closed in some other sequence as may be appropriate for a given application without departing from the scope of the present invention. In addition, alternative circuit topologies for the network of tank capacitors and switches may be appropriate. The second terminal of the load may be connected to a potentially variable) voltage other than ground.
It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8300489 *||Jan 12, 2010||Oct 30, 2012||International Business Machines Corporation||Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump|
|US20110170368 *||Jul 14, 2011||International Business Machines Corporation||Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump|
|U.S. Classification||363/60, 307/109|
|Oct 21, 2010||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SVENSSON, LARS;ATHAS, WILLIAM C.;KOLLER, JEFFREY G.;SIGNING DATES FROM 19980608 TO 19980609;REEL/FRAME:025174/0247
Owner name: UNIVERSITY OF SOUTHERN CALIFORNIA, CALIFORNIA