|Publication number||USRE42066 E1|
|Application number||US 11/040,608|
|Publication date||Jan 25, 2011|
|Filing date||Jan 21, 2005|
|Priority date||Apr 22, 1994|
|Also published as||USRE38918|
|Publication number||040608, 11040608, US RE42066 E1, US RE42066E1, US-E1-RE42066, USRE42066 E1, USRE42066E1|
|Inventors||Lars G. Svensson, William C. Athas, Jeffrey G. Koller|
|Original Assignee||University Of Southern California|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (69), Non-Patent Citations (47), Referenced by (2), Classifications (5), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This Reissue Application, Reissue application Ser. No. 08/986,327, and Reissue application Ser. No. 09/758,631 are all three reissue applications of U.S. Pat. No. 5,473,526, issued Dec. 5, 1995. This application is a continuation of Reissue application Ser. No. 09/758,631, filed Jan. 10, 2001 (now issued as U.S. Reissue Pat. No. RE 38,918, issued Dec. 13, 2005 ), entitled “System And Method For Power-Efficient Charging And Discharging Of A Capacitive Load From A Single Source”, which is a continuation of application Ser. No. 08/986,327, entitled “System And Method For Power-Efficient Charging And Discharging Of A Capacitive Load From A Single Source,” filed Dec. 5, 1997 (now issued as U.S. Reissue Pat. No. RE 37,552, issued Feb. 19, 2002 ).
This invention was made with government support under DABT- 63 - 92 -C- 0052 awarded by ARPA. The government has certain rights in the invention.
1. Field of the Invention
The present invention relates to electronic circuits and systems. More specifically, the present invention relates to power dissipation in electronic circuits and systems.
2. Description of the Related Art
Power dissipation of electronic circuitry is an important design consideration for many applications. Power dissipation provides a measure of the efficiency of the system. The efficiency of the system impacts the design of the power supply for the system. That is, low efficiency leads to higher costs due to the waste of energy and the need for larger power supplies.
For battery powered systems, power dissipation limits battery life. This necessitates larger batteries which increases the cost and weight of the system while limiting the applicability thereof. As an example, consider coronary pacemakers where power dissipation is a critical concern due to the difficultly of accessing the battery for replacement and the cost and inconvenience associated with the use of larger batteries.
In addition, the dissipated energy is released in the form of heat. Accordingly, systems which exhibit considerable power dissipation often require measures such as heat sinks to protect or cool system components from the heat created by the circuit. The use of heat sinks and the like adds to the cost, size and weight of the system and thereby limits the utility of same.
For the CMOS (complementary-metal-oxide semiconductor) based system, used widely in the design of computers, digital logic circuits and the like, capacitive effects are primarily responsible for the dissipation of power. Such capacitive effects arise due to junction capacitances within semiconductor devices, interlead capacitances between lines connecting the circuit to external devices and the capacitance of a load.
In accordance with conventional teachings, power dissipation is directly related to the operating frequency (f), the capacitance (C) and the square of the voltage (V2) applied to the capacitive element.
In addition to the elimination of unnecessary capacitances and the reduction of the switching frequency to the lowest value that supports the functional specification of the circuit, most prior approaches to the problem have focused on reducing the voltage applied to the capacitive elements. However, in addition to costly interfacing issues, attempts to lower the voltage of digital processors and the like have been limited by the fact that the trend is to higher processing speeds which cannot be attained at arbitrarily low operating voltages.
Thus, there is an ongoing need in the art for a system and technique for minimizing the power dissipated by a digital system.
The need in the art is addressed by the present invention which, in a most general sense, provides a system and method for efficiently charging and discharging a capacitive load from a single voltage source. The inventive system includes a first switch for selectively connecting the voltage source to the load and a second switch for selectively providing a short across the load as may be common in the art. A particularly novel aspect of the invention resides in the provision of plural capacitive elements and a switching mechanism for selectively connecting each of the capacitive elements to the load whereby the load is gradually charged or discharged.
In the illustrative embodiment, the switching mechanism includes a set of switches for selectively connecting each of the capacitive elements to the capacitive load and a switch control mechanism for selectively activating the switches.
Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof.
Most of the power dissipation in digital CMOS circuits is due to repeated charging and discharging of capacitive loads including those internal to the circuit and those associated with the output signals.
Econv=QV′=CV (V/2)=CV2/2 
A similar argument applies to the discharge process, so a complete conventional charge-discharge cycle dissipates all the energy provided by the power supply, QV=CV2.
In accordance with the present teachings, power dissipation is reduced by charging the capacitance of the load CL in several steps. This is illustrated in FIG. 2.
If N steps are used, the dissipation per step is again given by the transferred charge and the average voltage drop across the switch resistance:
Estep=QV′=(CV/N) (V/2N)=CV2/2N2 
To charge the capacitance all the way to the supply voltage V, N steps are used, so the total energy dissipation is:
Estepwise = N*Estep 
Again, a full charge-discharge cycle will cause twice the dissipation of the charging only. Thus, according to this simplified analysis, charging by several steps reduces the energy dissipation per charge-discharge cycle and thereby the total power dissipation, by a factor of N.
The multiple supply voltages of
Timing signals are provided by a system clock (not shown) through the latch 22. In practice, the clock rate should be at least (N+1) times the output signal rate. In the preferred embodiment, switches 0-4 are implemented with n-channel MOSFET devices. Switches 5 and 6 are implemented with p-channel devices.
The operation of the circuits of
On the trailing edge of input pulse, a discharge cycle is initiated by when the switches are momentarily closed in reverse order. Thus, switch N is opened and switch N−1 is closed. Then switch N−1 is opened and switch N−2 is closed and etc. On the closure of switch N−1, the associated tank capacitor will receive most of the charge on the load capacitance. Each capacitor down the line will receive a lower charge than the immediately proceeding capacitor. After switch 1 opens, switch 0 closes to complete the cycle dumping the remaining charge on the load CL to ground. Thus, over several cycles the tank capacitors will approach their steady state voltages, for example, the (N−1) th through 1st tank capacitors may have charges of say 5, 4, 3, 2 and 1 volts respectively. Then, at the beginning of the next cycle, on the closure of the first switch, the voltage on the first tank capacitor is applied to the load, then the voltage on the second capacitor is applied to the load and so on. Thus, in the example, first 1 volt is applied to the load, then 2 volts, then three volts and etc. As a result, the voltage on the load will gradually increase as shown in FIG. 5(j).
The circuits of
Since the tank capacitors are much larger than the load, the tank voltages do not change significantly, so the dissipation in the switches will be the same as for the case in
The voltages of the tank capacitor bank are self-stabilizing. To appreciate this, assume that the voltage of one of the tank capacitors is slightly higher than it should be. Then, the charge delivered by this tank capacitor during the charging of the load will be somewhat larger than that given by equation , since the “step” from the voltage below is now slightly larger. During the discharge phase, the step from the voltage above is slightly smaller and the charge received is therefore smaller as well. Therefore, over the full cycle, a net decrease of the charge on the storage capacitor occurs, which causes a decrease in the capacitor voltage. The initial deviance is automatically counteracted.
Even if the tank capacitor voltages differ from the “correct” values, the circuit will work logically correctly, since each charging (discharging) cycle ends by connecting the load to he supply rail (ground). Voltage deviations simply bring higher dissipation. This happens during start-up, before the tank voltages have had time to converge to the even distribution between the supply voltage and ground.
The implementation cost of a driver such as that shown in
The problem of maintaining the appropriate voltages on the tank capacitors is obviated by the fact that the capacitor voltages will converge automatically to the desired voltages. No additional circuitry is required. Only one supply line must be routed to the chip and the power supply need not be any more complicated than a conventional supply. In practice, the tank capacitors would be located off-chip.
For a CMOS implementation, the following design procedure may be followed to provide a driver configuration which exhibits minimal power dissipation.
Equation  indicates that dissipation decreases monotonically with increasing N. The number N cannot, however, be usefully made arbitrarily large because each step requires that a switch be turned on and off, which itself causes dissipation. Also, the energy used to drive each switch depends on the width of the device, which should be just enough to allow the charging to complete before the next step commences. Thus, for a given total allowable charging time ‘T’, there is an optimal number of steps and a set of optimal device sizes which lead to minimal total dissipation determined as follows.
Again, consider the circuit in FIG. 3 and assume the gates of the switch devices are driven conventionally. The load is charged and discharged once; the energy needed to drive the gates of the switch devices is:
Allot each step one Nth of the total charging time T. Then:
Here, m is the number of RC time constants spent waiting for each charging step to complete. From equation , it is evident that all the switch devices should have equal on-resistance: Ri=Rsw. Decreasing the on-resistance of device i by increasing the width means increasing the gate capacitance:
ρi is a quality measure of the switch. It varies with i, since the bulk-to-channel and gate-to-channel voltages are different for different switches. Combining equations , , and  yields:
If N is sufficiently large,
The number N that minimizes Etot is given by:
The corresponding energy dissipation is:
It remains to select the value for m. If it is chosen too small, there will still be a significant voltage across a switch when the next switch is to close. Hence, there is an increase in the average voltage across each switch and therefore a dissipation increase (the first term in equation  is changed slightly). If on the other hand, m is chosen unnecessarily large, time is wasted that could have been used to increase the number of steps. Thus, in general, optimization methods for the value of m vary according to the application, however, one skilled in the art will be able to select a suitable value for m using conventional teachings (e.g., a simulation program).
By using the number of stages given by equation , the designer can minimize the power dissipation of the driver. The minimum is rather shallow, however, so a lower N (as would most often be dictated by practical considerations) will still give a considerable improvement over the conventional case; N=2 already gives almost 50% reduction. Once N and m have been selected, the on-resistance of each switch is given by equation . The corresponding gate capacitance, and thereby the width of the device, is given by equation . The values of ρ for a certain process can be found by circuit simulation or by measuring the on-resistances of test devices of known widths.
Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications applications and embodiments within the scope thereof. For example, the switches may be closed in some other sequence as may be appropriate for a given application without departing from the scope of the present invention. In addition, alternative circuit topologies for the network of tank capacitors and switches may be appropriate. The second terminal of the load may be connected to a potentially variable) voltage other than ground.
It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3594627 *||Oct 20, 1969||Jul 20, 1971||Teledyne Inc||Capacitor discharge battery charger|
|US3603898||Feb 2, 1970||Sep 7, 1971||Marconi Co Ltd||N-parallel-path capacitive switched filter in which only incomplete spaced portions of input signal are sampled|
|US3654537||Apr 29, 1970||Apr 4, 1972||Westinghouse Electric Corp||High efficiency power supply for charging capacitors in steps|
|US3836906||Feb 28, 1973||Sep 17, 1974||Sony Corp||Digital-to-analog converter circuit|
|US4082430||Jan 21, 1977||Apr 4, 1978||Bbc Aktiengesellschaft Brown, Boveri & Company, Ltd.||Driving circuit for a matrix-addressed liquid crystal display device|
|US4107757||Jun 30, 1977||Aug 15, 1978||Senichi Masuda||Pulse power source|
|US4109192||Jun 25, 1976||Aug 22, 1978||Hughes Aircraft Company||Low power reactive drive circuit for capacitive loads|
|US4328525||Jun 27, 1980||May 4, 1982||International Business Machines Corporation||Pulsed sine wave oscillating circuit arrangement|
|US4594589||Aug 27, 1982||Jun 10, 1986||Sharp Kabushiki Kaisha||Method and circuit for driving electroluminescent display panels with a stepwise driving voltage|
|US4605999||Mar 11, 1985||Aug 12, 1986||At&T Bell Laboratories||Self-oscillating high frequency power converter|
|US4707692||Nov 30, 1984||Nov 17, 1987||Hewlett-Packard Company||Electroluminescent display drive system|
|US4802739||Feb 27, 1986||Feb 7, 1989||Kabushiki Kaisha Toshiba||Liquid crystal display control device|
|US4818981||Sep 11, 1987||Apr 4, 1989||Fujitsu Limited||Active matrix display device and method for driving the same|
|US4862113||Jan 6, 1988||Aug 29, 1989||International Business Machines Corporation||Sinusoidal oscillator with instant start-up|
|US4893117||Jul 17, 1987||Jan 9, 1990||Stc Plc||Liquid crystal driving systems|
|US4920474||Aug 29, 1989||Apr 24, 1990||North American Philips Corporation||High frequency high voltage power supply with controlled output power|
|US5051668||Aug 1, 1990||Sep 24, 1991||Sony Corporation||Sine wave deflecting circuit|
|US5063340||Oct 25, 1990||Nov 5, 1991||Motorola, Inc.||Capacitive power supply having charge equalization circuit|
|US5095223||May 21, 1991||Mar 10, 1992||U.S. Philips Corporation||Dc/dc voltage multiplier with selective charge/discharge|
|US5105288||Oct 16, 1990||Apr 14, 1992||Matsushita Electronics Corporation||Liquid crystal display apparatus with the application of black level signal for suppressing light leakage|
|US5107136||Mar 29, 1990||Apr 21, 1992||U.S. Philips Corporation||Control circuit for at least one clock electrode of an integrated circuit|
|US5126589||Aug 31, 1990||Jun 30, 1992||Siemens Pacesetter, Inc.||Piezoelectric driver using resonant energy transfer|
|US5150013||May 6, 1991||Sep 22, 1992||Motorola, Inc.||Power converter employing a multivibrator-inverter|
|US5206632||Sep 11, 1990||Apr 27, 1993||Deutsche Thomson-Brandt Gmbh||Actuating circuit for a liquid crystal display|
|US5247376||Nov 9, 1989||Sep 21, 1993||Seiko Epson Corporation||Method of driving a liquid crystal display device|
|US5264752||Jun 1, 1992||Nov 23, 1993||At&T Bell Laboratories||Amplifier for driving large capacitive loads|
|US5293082||Jun 4, 1993||Mar 8, 1994||Western Digital Corporation||Output driver for reducing transient noise in integrated circuits|
|US5339236||Feb 24, 1993||Aug 16, 1994||Nec Corporation||Charge pump circuit for intermediate voltage between power supply voltage and its double voltage|
|US5349366||Oct 27, 1992||Sep 20, 1994||Semiconductor Energy Laboratory Co., Ltd.||Electro-optical device and process for fabricating the same and method of driving the same|
|US5400028||Oct 30, 1992||Mar 21, 1995||International Business Machines Corporation||Charge summing digital to analog converter|
|US5459414||May 28, 1993||Oct 17, 1995||At&T Corp.||Adiabatic dynamic logic|
|US5465054||Apr 8, 1994||Nov 7, 1995||Vivid Semiconductor, Inc.||High voltage CMOS logic using low voltage CMOS process|
|US5473269||Nov 4, 1994||Dec 5, 1995||At&T Corp.||Adiabatic dynamic logic|
|US5473526||Apr 22, 1994||Dec 5, 1995||University Of Southern California||System and method for power-efficient charging and discharging of a capacitive load from a single source|
|US5506520||Jan 11, 1995||Apr 9, 1996||International Business Machines Corporation||Energy conserving clock pulse generating circuits|
|US5508639||Jan 13, 1995||Apr 16, 1996||Texas Instruments Incorporated||CMOS clock drivers with inductive coupling|
|US5510748||Jan 18, 1994||Apr 23, 1996||Vivid Semiconductor, Inc.||Integrated circuit having different power supplies for increased output voltage range while retaining small device geometries|
|US5517145||Oct 31, 1994||May 14, 1996||International Business Machines Corporation||CMOS toggle flip-flop using adiabatic switching|
|US5521538||Mar 30, 1995||May 28, 1996||At&T Corp.||Adiabatic logic|
|US5526319||Jan 31, 1995||Jun 11, 1996||International Business Machines Corporation||Memory with adiabatically switched bit lines|
|US5528256||Aug 16, 1994||Jun 18, 1996||Vivid Semiconductor, Inc.||Power-saving circuit and method for driving liquid crystal display|
|US5559463||Apr 18, 1994||Sep 24, 1996||Lucent Technologies Inc.||Low power clock circuit|
|US5559478||Jul 17, 1995||Sep 24, 1996||University Of Southern California||Highly efficient, complementary, resonant pulse generation|
|US5572211||Jan 18, 1994||Nov 5, 1996||Vivid Semiconductor, Inc.||Integrated circuit for driving liquid crystal display using multi-level D/A converter|
|US5578957||Nov 27, 1995||Nov 26, 1996||Vivid Semiconductor, Inc.||Integrated circuit having different power supplies for increased output voltage range while retaining small device geometries|
|US5602497||Dec 20, 1995||Feb 11, 1997||Thomas; Steven D.||Precharged adiabatic pipelined logic|
|US5604449||Jan 29, 1996||Feb 18, 1997||Vivid Semiconductor, Inc.||Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes|
|US5604454||Sep 29, 1995||Feb 18, 1997||Motorola Inc.||Integrated circuit with low output buffer energy consumption and related method|
|US5657039||Nov 3, 1994||Aug 12, 1997||Sharp Kabushiki Kaisha||Display device|
|US5675263||Nov 21, 1995||Oct 7, 1997||Lucent Technologies Inc.||Hot-clock adiabatic gate using multiple clock signals with different phases|
|US5694445||Sep 20, 1995||Dec 2, 1997||Matshushita Electric Industrial Co., Ltd.||Semiconductor device with means for charge recycling|
|US5734285||Dec 17, 1993||Mar 31, 1998||Harvey; Geoffrey P.||Electronic circuit utilizing resonance technique to drive clock inputs of function circuitry for saving power|
|US5748165||Dec 23, 1994||May 5, 1998||Sharp Kabushiki Kaisha||Image display device with plural data driving circuits for driving the display at different voltage magnitudes and polarity|
|US5754156||Sep 19, 1996||May 19, 1998||Vivid Semiconductor, Inc.||LCD driver IC with pixel inversion operation|
|US5818252||Sep 19, 1996||Oct 6, 1998||Vivid Semiconductor, Inc.||Reduced output test configuration for tape automated bonding|
|US5821923||Feb 23, 1996||Oct 13, 1998||U.S. Philips Corporation||Picture display device|
|US5838203||Dec 6, 1996||Nov 17, 1998||Intel Corporation||Method and apparatus for generating waveforms using adiabatic circuitry|
|US5838289||Sep 26, 1995||Nov 17, 1998||Nippondenso Co., Ltd.||EL display driver and system using floating charge transfers to reduce power consumption|
|US5841299||Feb 6, 1997||Nov 24, 1998||Intel Corporation||Method and apparatus for implementing an adiabatic logic family|
|US5852426||Mar 21, 1996||Dec 22, 1998||Vivid Semiconductor, Inc.||Power-saving circuit and method for driving liquid crystal display|
|US5861861||Jun 28, 1996||Jan 19, 1999||Microchip Technology Incorporated||Microcontroller chip with integrated LCD control module and switched capacitor driver circuit|
|US5870331||Sep 26, 1997||Feb 9, 1999||Advanced Micro Devices, Inc.||Application-specific SRAM memory cell for low voltage, high speed operation|
|US5880602||Feb 28, 1996||Mar 9, 1999||Hitachi, Ltd.||Input and output buffer circuit|
|US5881014||Aug 19, 1997||Mar 9, 1999||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device with a voltage down converter stably generating an internal down-converter voltage|
|US5883538||May 21, 1997||Mar 16, 1999||Micron Technology, Inc.||Low-to-high voltage CMOS driver circuit for driving capacitive loads|
|US5889439||Aug 20, 1997||Mar 30, 1999||U.S. Philips Corporation||Phase-locked loop with capacitive voltage divider for reducing jitter|
|US5892540||Jun 13, 1996||Apr 6, 1999||Rockwell International Corporation||Low noise amplifier for passive pixel CMOS imager|
|US5896117||Jun 27, 1996||Apr 20, 1999||Samsung Electronics, Co., Ltd.||Drive circuit with reduced kickback voltage for liquid crystal display|
|US5900854||Sep 28, 1995||May 4, 1999||International Business Machines Corporation||Drive unit of liquid crystal display and drive method of liquid crystal display|
|1||[Svensson, L.J.] LS. "LCD Driver Test Chip Evaluation," Oct. 21, 1996.|
|2||Ammer, J., M. Bolotski, P. Alveida, T.F. Knight, Jr., "TP12.5: A 160×120 Pixel Liquid-Crystal-on-Silicon Microdisplay with an Adiabatic DACM," In 1999 IEEE Interational Solid-States Circuits Conference Digest of Technical Papers, pp. 212-213.|
|3||Ammer, J., M. Bolotski, P. Alvelda, T.F. Knight, Jr., "TP12.5: A 160×120 Pixel Liquid-Crystal-on-Silicon Microdisplay with an Adiabatic DAC," 1999 ISSCC Slide Supplement, pp. 184-185, 435-.|
|4||Athas, W.C. and L.J. Svensson, Reversible Logic Issues in Adiabatic CMOS, IEEE Worshop on Physics and Computation, Nov. 17-20, 1994 www.isi.edu/acmos.|
|5||Athas, W.C., J. Koller and L. Svensson, "An Energy-Efficient CMOS Line Driver Using Adiabatic Switching," IEEE, pp. 196-199.|
|6||Athas, W.C., J. Koller and L. Svensson, An Energy-Efficient CMOS Line Driver Using Adiabatic Switching, University of Southerm California, Information Sciences Institute Technical Report ACMOS-TR-2, Aug. 15, 1993, pp. 1-16.|
|7||Athas, W.C., L. "J." Svensson and N. Tzartzanis, "A Personal Signal Drive For Two-Phase, Almost-Non-Overlapping Clocks," IEEE International Symposium on Circuits and Systems, May 1996.|
|8||Athas, W.C., N. Tzartzanis, L. Svensson, L., Peterson, H. Li, X. Jiang, P. Wang, W-C. Liu, "AC-1: A Clock-Powered Microprocessor," IEEE Intl. Symposium on Low-Power Electronics and Design, Aug. 1997.|
|9||Athas, William C., "Energy-Recovery CMOS," Chapter 5 in J. Rabaey, M. Pedram (Eds.) Low-Power Design Methodologies, Kluwer Academic Press, 1996.|
|10||Athas, William C., Lars "J." Svensson, Jeffrey G. Koller, Nestoras Tzartzanis and Eric Ying-Chin Chou, "Low-Power Digital Systems Based on Adiabatic-Switching Principles," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, Dec. 1994, pp. 398-407.|
|11||Burr et al., "Energy Considerations in Multichip-Module based Multiprocessors, " IEEE International Conference on Computer Design 1991, pp. 593-600.|
|12||Chandrakasan et al., "Low-Power CMOS Digital Design," IEEE Journal of Solid-State Circuits, Apr. 1992, vol. 27, No. 4, pp. 473-484.|
|13||Davis, Andrew W. "Flat Panel Display Drivers: 'Little Things' Changing The Image Quality Picture," Advanced Imaging, Oct. 1997, vol. 12, No. 10, pp. 10, 12, 62.|
|14||Davis, Andrew W. "Flat Panel Display Drivers: ‘Little Things’ Changing The Image Quality Picture," Advanced Imaging, Oct. 1997, vol. 12, No. 10, pp. 10, 12, 62.|
|15||Dharmasena, Sanjaya and Lars Svensson, "Startup Energies in Energy-Recovery CMOS," in Proceedings of Physics and Computation '96, Boston, MA, Nov. 22-24, 1996.|
|16||Dickinson, Alex G. and John S. Denker, "Adiabatic Dynamic Logic," IEEE, Custom Integrated Circuits Conference, 1994, pp. 282-285.|
|17||Erhart, A. "P-10: Late Poster Paper: A High-Voltage High-Gray-Shade LCD Column Driver Utilizing a Standard 1.2-mum CMOS Process," SID 94 Digest, 1994, pp. 471-474.|
|18||Erhart, A. "P-10: Late Poster Paper: A High-Voltage High-Gray-Shade LCD Column Driver Utilizing a Standard 1.2-μm CMOS Process," SID 94 Digest, 1994, pp. 471-474.|
|19||Erhart, Alex, "Direct Drive Promises Reduced Power Consumption and Improved Image Quality for Notebook AMLCDs," Information Display, Dec. 1996, vol. 12, No. 12, pp. 24-27.|
|20||Flat Panel Display Handbook, Technology Trends & Fundamentals, First Edition, 1999, San Jose: Stanford Resources, 1999.|
|21||Fundaun, I., C. Reese and H.H. Soonpaa (Physics Department , University of North Dakota, Grand Forks), "Charging a capacitor," American Journal of Physics, vol. 60, No. 11, Nov. 1999, pp. 1047-1048.|
|22||Heinrich, F. (Laboratory of Solid State Physics, Swiss Federal Institute of technology ETH), Entrophy Change When Charging A Capacitor: A Demonstration Experiment, American Journal of Physics, vol. 54, No. 8, Aug. 1986, pp. 742-744.|
|23||Jonscher, A.K. (Royal Holloway and Bedford New College, Univ. of London), "Charging and Discharging of Non-Ideal Capacitors," IEEE Transactions on Electrical Insulation, vol. EI-22, No. 4, Aug. 1987, 357-359.|
|24||Kawahara, T., M. Horiguchi, Y. Kawajiri, T. Akiba, G. Kitsukawa, T. Kure, and M. Aoki. "A Charge Recycle Refresh for Gb-scale DRAMs in File Applications," 1993 Symposium on VLSI Circuits, Digest of Technical Papers, May 19-21, 1993, pp. 41-42.|
|25||Koller, Jeffrey G. and William C. Athas, "Adiabatic Switching, Low Energy Computing, and the Physics of Storing and Erasing Information," IEEE Press 1993, pp. 267-270.|
|26||Lieberman, David, "EL Design Yields Brighter Display At Lower Power," Electronic Engineering Times, No. 1021, Aug. 1998, pp. 52-.|
|27||Maksimovic, Dragan, "A MOS Gate Drive With Resonant Transitions," IEEE Press, 1991, pp. 527-532.|
|28||Mateo, D. and A. Rubio, "Quasi-adiabatic ternary CMOS logic," Electronics Letters, vol. 32, No. 2, Jan. 18, 1996, pp. 99-101.|
|29||Mead et al., "Chapter 1, MOS Devices and Circuits," In Introduction to VLSI Systems, 1980, Addison-Wesley, pp. 1-37.|
|30||Morimura, Hiroki and Nobutaro Shibata, "A 1-V 1-Mb SRAM for Portable Equipment," ISLPED, 1996 Monterey CA USA, pp. 61-66.|
|31||Nordin et al., "A Systems Perspective on Digital Interconnection Technology," IEEE Journal of Lightwave Technology, Jun. 1992, vol. 10, No. 6, pp. 811-827.|
|32||RCA Transistor Thyristor & Diode Manual RCA Corporation, 4/71, Technical Series SC-15, 1971, pp. 179-183.|
|33||Schlig, E.S. and J.L. Sanford, "New Circuits for AMLCD Data Line Drivers," 1994.|
|34||Seitz et al., "Hot-Clock nMOS," Proceedings of the 1985 Chapel Hill Conference on VLSI, 1985, pp. 1-17.|
|35||Sekiguchi, Tomonori, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda and Masakazu Aoki, "Low-Noise, High-Speed Data Transmission Using a Ringing-Canceling Output Buffer," IEEE Journal of Solid-State Circuits, vol. 30, No. 12, 1995, pp. 1569-1574.|
|36||Somasekhar, Dinesh, Yibin Ye and Kaushik Roy, "An Energy Recovery Static RAM Memory Core," in IEEE Symposium on Low-Power Electronics, 2d ed., 1995, pp. 62-63.|
|37||Svensson L. et al., Adiabatic Charging Without Inductors, USC/ISI Technical Report ACMOS-TR-3, Dec. 17, 1993.|
|38||Svensson, L. "J." and W.C. Athas, "Stepwise Charging Without Equations," USC/ISI, Feb. 25, 1997, pp. 1-4.|
|39||Svensson, L. "J.", W.C. Athas and R.S.-C. Wen, "A sub-CV 2 pad driver with 10 ns transition time," ISLPED 1996 Monterey CA USA, Aug. 1996, pp. 105-108.|
|40||Tzartzanis, Nestor and William C. Athas "Energy-Recovery for the Design of High-Speed, Low-Power Static RAMs," International Symposium on Low-Power Electronics and Design, Aug. 1996, Monterey CA USA, pp. 55-60.|
|41||Tzartzanis, Nestor and William C. Athas, "Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing, " 20th Anniversary Conference on Advanced Reseach in VLSI, IEEE Computer Society Press, Mar. 1999.|
|42||Tzartzanis, Nestor, Energy-Recovery Techniques for CMOS Microprocessor Design, Ph.D. Dissertation, University of Southern California, Aug. 1998, 163 pp.|
|43||Weste et al., "Principles of CMOS VLSI Design, A Systems Perspective," Chapter 5 in CMOS Circuit and Logic Design, 2d Edition, 1993, Addison-Wesley, pp. 160-231.|
|44||Ye, Yibin and Roy Kaushik, "Energy Recovery Circuits Using Reversible and Partially Reversible Logic," IEEE Transactions on Circuits and Systems-I. Fundamental Theory, vol. 43, No. 9, 1996, pp. 769-778.|
|45||Ye, Yibin and Roy Kaushik, "Energy Recovery Circuits Using Reversible and Partially Reversible Logic," IEEE Transactions on Circuits and Systems—I. Fundamental Theory, vol. 43, No. 9, 1996, pp. 769-778.|
|46||Younis, Saed G. and Thomas F. Knight, Jr., "Non-Dissipative Rail Drivers for Adiabatic Circuits," IEEE, 9/95, pp. 404-414.|
|47||Yuan, Jiren (Linkoping Univeristy), "Low Power and Low Area or High Throughput Single-Ended Bus and I/O Protocols," Proceedings of 1997 IEEE International Symposium on Circuits and Systems: Circuits and Systems in the InformationAge, ISCAS '97, Jun. 9-12, 1997, Hong Kong, pp. 1932-1935.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8300489 *||Jan 12, 2010||Oct 30, 2012||International Business Machines Corporation||Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump|
|US20110170368 *||Jul 14, 2011||International Business Machines Corporation||Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump|
|U.S. Classification||363/60, 307/109|
|Oct 21, 2010||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SVENSSON, LARS;ATHAS, WILLIAM C.;KOLLER, JEFFREY G.;SIGNING DATES FROM 19980608 TO 19980609;REEL/FRAME:025174/0247
Owner name: UNIVERSITY OF SOUTHERN CALIFORNIA, CALIFORNIA