|Publication number||USRE42113 E1|
|Application number||US 12/708,169|
|Publication date||Feb 8, 2011|
|Filing date||Feb 18, 2010|
|Priority date||Aug 5, 2005|
|Also published as||US7332886, US20070031130|
|Publication number||12708169, 708169, US RE42113 E1, US RE42113E1, US-E1-RE42113, USRE42113 E1, USRE42113E1|
|Inventors||Giuseppe Maiocchi, Michele Boscolo, Roberto Bardelli|
|Original Assignee||Stmicroelectronics S.R.L.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (2), Classifications (9), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates in general to mass storage disk devices, such as common hard disk drives (HDD) for example, and more particularly, to a silicon integrated control system for a spindle motor that rotates a disk and for a motor that positions an arm that carries read/write heads.
Voice coil motors (VCM) are commonly used for moving an arm that carries read/write heads over a spinning disk from a rest position on a parking ramp to a desired position, and vice-versa. Commonly, the disk is rotated by a brushless spindle motor such to position the heads over the tracks of a certain sector of the disk from which data is to be read or written.
Voice-coil motors are used in a number of applications. They are substantially composed of a winding immersed in a magnetic field generated by a permanent magnet. By forcing a certain current through the winding, the winding receives a displacing force. The displacement of the winding may be controlled with great precision.
In a disk storage device, it is important to control with high precision both the brushless spindle motor and the VCM. Modern fabrication technologies permit fabrication of integrated devices containing in a single package the power switches (bipolar junction or MOS transistors) of the output drivers of the brushless motor, and of the VCM for positioning the heads together with the control circuitries of both motors.
With these technologies allowing fabrication in a single chip through a single process logic CMOS devices, bipolar junction signal transistors, vertical or lateral power MOS or BJT devices, it has been possible to digitally implement many control functions. By using powerful CAD tools it has been possible to implement rather complex functions and controls of extremely high precision and performances in these integrated devices, commonly known as “power combo”.
Co-integrated control architectures based exclusively on digital techniques and circuits and output power stages make these devices adaptable to the user needs, and to different schemes of partitioning of the mass storage support.
The circuit for driving the brushless spindle motor for rotating the disk is generally composed of fully digital circuit blocks. Improvements toward a complete digitalization also of the control circuit of the VCM have been achieved, and they are leading to the realization of a control architecture of the VCM motor called “digital power processing voltage mode” or DPPV.
The function of the different circuit blocks and of the main signals of the two control systems, used in various commercial devices of STMicroelectronics, depicted in
Self Adapt. T.O.
Circuit for rephrasing automatically the current in the
spindle with its BEMF in order to optimize the motor
Circuit for determining the direction of the flow of the
current in the spindle.
Analog-to-digital converter of the supply voltage and
of other main voltages.
Enables the rephasing of the current of the spindle and
of the relative BEMF upon a user input or upon a
signal coming from the Self Adapt T.O.
Circuit for feed-forward compensating differences
between the supply voltage and the nominal value.
It generates the address of the data stored in “Memory
2 × 3 profile” corresponding to the instantaneous
values of the voltage to be given to the phases of the
spindle for generating an appropriate voltage
Memory 2 by 3
Look up table that stores the data sequences that
generate an appropriate voltage waveform (called
2 × 3) to be supplied to the phases of the spindle
during its rotation.
A digital multiplier that allows modulation of the
amplitude of each phase voltage of the spindle as a
function of the value coming from the speed controller
for allowing the control of the speed.
In case of three-phase motors, it converts three digital
data with N bits in three phase modulated digital data
Power stage for driving (in switched mode) the
Bank of registers for controlling the various functions
of the spindle.
Determines the duration in electrical degrees of the
period between two consecutive zero-crosses of the
BEMF in one or more phases of the spindle.
Masks by an appropriate duration each switching or
the PSM signals generated by the block PWM
Masks by an appropriate duration in degrees each time
a tristate condition is forced for reading correctly the
Back electromotive force induced in the windings of
the brushless motor.
Filter for eliminating spurious switching of a zero-
cross signal ZC generated at each zero-cross of the
ZC comp. + ZC
In this block the zero-cross signal is generated and
all the maskings forced by the signals Mask Win and
Mask PWM and by the current limiter are enabled.
Block for measuring inductances of the three phases of
the used spindle, in the start-up phase, for identifying
the position of the rotor.
This signal is completely asynchronous with the other
signals of the system.
Integrated automatic start-up of the spindle.
Block for selecting the output signals of the blocks
inductive sense and ZC filter.
Brushless motor that rotates the disk.
Analog-to-digital converter of the supply voltage level.
Circuit for compensating variations of resistance of the
winding of the VCM in respect to the nominal value.
Circuit that displaces the VCM in the rest position when a
Power on Reset is asserted.
Bank of registers for controlling the various functions of the
Infinite impulse response filter.
Circuit for feed-forward compensating supply voltage shifts
from the nominal value.
Converts an N bit digital datum in two phase-shift
modulated (PSM) signals for driving the VCM.
Power stage for driving the VCM.
Circuit for compensating the back electromotive force
induced in the winding of the VCM.
Charges/discharges the VCM on/from the parking ramp
with temporaneous interruption of the current for reading
In the depicted example, the driving circuit of the VCM is realized according to a digital voltage mode. This requires dedicated additional control blocks for compensating unavoidable variations of the three main variables that, in this case, are not controlled, as it happens with a current feedback loop, namely: the back electromotive force induced in the winding, the supply voltage, and the resistance in the winding of the motor.
Obviously, if the control architecture of the VCM is based on a more traditional current control loop, the circuit blocks of
These integrated devices are known as a power combo, despite the efforts for implementing control functions, safety functions for ensuring the integrity of the power stages and any other possible function in a digital mode. They require the presence of other analog circuits besides the integrated structures of the output power devices.
Constantly improved fabrication technologies for reaching larger and larger scales of integration, especially for digital circuits, have allowed a reduction in the size of devices and in their footprint. These are important factors for the manufacturers of mass storage disk devices.
Despite the new possibilities of greater compactness of the control digital circuitry offered by the new fabrication technologies, these extreme process technologies do not allow the fabrication of power devices and of related analog driving circuits of utmost performance in terms of power consumption. Further reductions of the size must be combined with the need of preserving acceptable performances of the power stages and of the related driving circuits.
For the same performances, significantly reduced silicon area occupancy may be achieved by realizing a complete system for controlling and driving the rotation brushless spindle motor and the VCM of the read/write heads of a disk mass storage device, instead of on a single chip of silicon, as has long become a standard with modern fabrication processes. Instead, two distinct chips of silicon are assembled in a single package.
There is a relocation of the various functional blocks of the whole power combo system, or more precisely, of the two distinct control systems of the respective motors (i.e., the brushless spindle motor and VCM) for positioning the heads carrying arm. This even accounts for the need of realizing appropriate interfaces for exchanging electrical signals between the two distinct chips, and concentrates on the chip that stores the main control circuitries. This is practically the whole logic circuitry. On the second chip is formed the power devices and the relative driving circuitry as well as the circuits for detecting parameters and signals to be used by the logic control circuitry. This results in a reduction of the required silicon area, and obtains an enhanced performance of the power stages without requiring a significant increase of silicon area.
In the studied prototype, for fabricating the digital control chip, it has been possible to use a 0.13 μm row definition technology, that is much more compact than the present BCD (bipolar-CMOS-DMOS) technology at 0.35 μm currently used for fabricating Smart Power™ devices of acceptable power efficiency, achieving a significant saving of the total silicon area requirement without sacrificing the performances of the power stages that were realized in BCD technology at 0.35 μm, as in the commonly used BCD technique.
The net silicon area saving and the consequent reduction of fabrication costs of these devices is substantially optimized by grouping in one and in the other chip the circuitries of the various functional blocks of the two control systems, such to allow the maximum silicon area saving, having accounted for the area required by the additional interfaces required in the two distinct integrated circuits for exchanging signals.
The invention is described in detail referring to the attached drawings, wherein:
As stated above, the main advantage of this architecture is that the chips 2_DISP, which integrates all the logic circuits, may be realized with a technology of relatively large integration scale, typically a 0.13 μm minimum line width CMOS technology, while the chip 1_DISP that integrates the output power devices is realized with a common BCD technology, typically with a 0.35 μm minimum line width, for a high power efficiency performance of the output power devices.
Notwithstanding the fact that the invention requires the integration of two additional interfaces, one on every chip, it has been found that the silicon area that is saved by integrating all the logic circuits in a separated integrated device largely exceeds the silicon area required for the integration of the two added interfaces.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5760563||Jun 28, 1996||Jun 2, 1998||Western Digital Corporation||Method and apparatus for providing thermal feedback between an analog power chip and a digital controller chip in a disk controller system|
|US6730610||Dec 20, 2002||May 4, 2004||Taiwan Semiconductor Manufacturing Co., Ltd||Multiple thickness hard mask method for optimizing laterally adjacent patterned layer linewidths|
|US20050194453||Dec 21, 2004||Sep 8, 2005||Storcard, Inc.||Enhanced smart card with rotating storage|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US9385639 *||May 22, 2014||Jul 5, 2016||Stmicroelectronics S.R.L.||Switching controller for electric motors and related method of controlling electric motors|
|US20140354201 *||May 22, 2014||Dec 4, 2014||Stmicroelectronics S.R.L.||Switching controller for electric motors and related method of controlling electric motors|
|U.S. Classification||318/599, 388/804, 318/600, 318/811|
|Cooperative Classification||G11B5/5526, G11B19/28|
|European Classification||G11B5/55D1, G11B19/28|
|Jul 29, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Jul 28, 2015||FPAY||Fee payment|
Year of fee payment: 8