|Publication number||USRE42182 E1|
|Application number||US 11/174,421|
|Publication date||Mar 1, 2011|
|Filing date||Jul 1, 2005|
|Priority date||Apr 24, 2002|
|Also published as||US6750842, US20030201967, US20110084991|
|Publication number||11174421, 174421, US RE42182 E1, US RE42182E1, US-E1-RE42182, USRE42182 E1, USRE42182E1|
|Original Assignee||Beyond Innovation Technology Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (2), Classifications (22), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to a multi-lamps LCD back-light control circuit. More particularly, the invention provides a control circuit that can simplify the circuitry of dimensionally larger LCD devices.
Compared to traditional white thermal lamps, cold cathode fluorescent lamps (CCFL) have many advantages such as higher efficiency and longer service life. Therefore, an important number of liquid crystal display (LCD) presently uses CCFL as light source. To achieve a stable operation of the CCFL, the power frequency needed is about 30 KHz through 80 KHz without the stringed wave from the DC current part while the operating voltage is approximately constant. The illumination of the lamp is determined according to the tube current there through. The voltage needed to turn on the lamp is higher than the normal stable operating voltage 2 to 2.5 times. The turn on voltage and operating voltage of the CCFL are determined from the size of the CCFL. Traditional 14″, 15″ LCD screens incorporate CCFL that require a turn-on voltage of about 1400 Vrms, and an operating voltage of about 650 Vrms at the highest normal current of 7 mA. To regulate the CCFL, a common control method is the use of an electrical stabilizer such as a typical fixed frequency operation full bridge phase shift converter that can convert direct current to alternating current.
As shown in
However, the present use of traditional fixed frequency operation full bridge phase shift converter in LCD screens presents several problems. Within present LCD devices, the DC voltage provided by the circuit is only about 10 to 20 volts. The electrical stabilizer of the CCFL of
It is therefore a first object of the invention to provide a CCFL control circuit that is adapted to a dimensional increase of the LCD devices.
It is a second object of the invention to provide a CCFL control circuit that incorporates a step-up voltage transformer so that the number of high-voltage resistant elements can be reduced within the control circuit.
Furthermore, it is third object of the invention to provide a CCFL control circuit that incorporates PMOSFET as power switches so that additional step-up circuits are not needed to directly drive the switches.
Still, it is a fourth object of the invention to provide a CCFL control circuit in which the cycle of ground switches is fixed so as to change the cycle of the power switches, thereby the voltage conversion is more efficient.
Furthermore, it is a fifth object of the invention to provide a CCFL control circuit in which the cycle of ground switches is fixed so as to change the cycle of the power switches, thereby most of the circuit current flows through the ground switches. Loss increase due to higher resistivity of PMOS-FET power switches is therefore favorably reduced.
Still, it is a sixth object of the invention to provide a CCFL control circuit in which stabilization of the lamp current is achieved via pulse width modulation (PWM) feedback control.
Yet, it is a seventh object of the invention to provide a CCFL control circuit in which constant frequency and frequency synchronization are implemented to reduce frequency retardation interference within the multi-lamp circuit, caused by the use of different driving circuits.
Furthermore, it is an eighth object of the invention to provide a CCFL control circuit in which constant frequency and phase synchronization are implemented to reduce phase retardation interference within the multi-lamp circuit, caused by the use of different driving circuits.
Still, it is a ninth object of the invention to provide a CCFL control circuit in which the principal control elements can be fabricated on a same integrated circuit.
To provide a further understanding of the invention, the following detailed description illustrates embodiments and examples of the invention, this detailed description being provided only for illustration of the invention.
The drawings included herein provide a further understanding of the invention. A brief introduction of the drawings is as follows:
FIG. 2A and
FIG. 7A and
Wherever possible in the following description, like reference numerals will refer to like elements and parts unless otherwise illustrated.
As shown in
Among the full bridge switches, the switches 317, 320 connected to the power source 335 (also called “power switches”) are PMOSFET switches, while the switches 318, 319 connected to the ground (also called “ground switches”) are NMOSFET switches. Within the full bridge switches, the change and output of the duty cycle of the switches 317, 320 are controlled via a PWM controller 302. In turn, the duty cycle of the switches 318, 319 is constant and further must be controllable above 50%. Furthermore, the phase relationship between the control signal of the NMOSFET ground switches 318, 319 and the control signal of the PMOSFET power switches 317, 320 is invariant. More particularly with respect to the above NMOSFET and PMOSFET having a common drain connection, when said NMOSFET is turned on, said PMOSFET is oppositely turned off. With respect to the NMOSFET and PMOSFET without common drain connection, said PMOSFET is turned on only after a preset delay after the turn on of the NMOSFET.
A triangular wave generator 336 is further connected to an input of the PWM controller 302. The operating frequency of the triangular wave generator 336 can be controlled through an external synchronous signal delivered through a control terminal FSYN. A ½ divider circuit 306 is further used to generate a time sequence as driving input of the ground switches 318, 319. The phase of the ½ divider circuit 306 can be synchronized via an external synchronous signal delivered through the control terminal PSYN.
With reference to
Within the CCFL control circuit as shown in
The triangular generator 336 generates a triangular wave output 344 which configuration is shown in
The full bridge circuit of the invention hence is driven via driving signals, formed from a set of constant duty cycles greater than 50%, that are further accompanied with the output of the PWM controller generating an appropriate change of the duty cycle. In the invention, the control signals of constant cycles drive the NMOSFET 318, 319 as described below.
By means of the ½ frequency divider 306, the clock triangular signal 601 from the triangular wave generator is transformed to a clock signal 604 (also called “half clock signal”) having a frequency equal to half the frequency of the triangular signal 601. The inverter 334 then inverts the half clock signal 604 to an inverted half clock signal 605. Both clock signals 604, 605 are delivered through outputs 339, 340 to delays 312, 311 and OR logic 316, 315 to generate signals 606, 608 of duty cycle greater than 50%, delivered through the outputs NOUT1, NOUT2. The signals 606, 608 have a duty cycle that is delayed a delay time 610 behind the half clock signals 604, 605. If needed, this delay time can be adjusted by means of a time delay controller element 333.
To drive the full bridge switches, the changed duty cycle from the PWM controller is combined with the driving signals of constant cycle in the manner described hereafter. A Boolean AND is applied to the half clock signals 340, 339 and the output 341 of the PWM controller 302 by means of the AND logic 307, 308, so that the PWM output 341 is in outputting configuration only when the half clock signals are in the logic state “1”. The time delays of the delays 309, 310 can be controlled via the controller elements 333. AND logic 348, 349 enable the PWM output 341 to be turned on only after a delay time 611 behind the turn on of the NMOSFET. Because the PMOSFET and NMOSFET respectively are driven via low and high voltages, inverters 313, 314 therefore invert the PWM output to infer the PMOSFET. Within the above circuitry, the control signal 607 driving the PMOSFET 320 at the output POUT2 is in turn-on state (logic “0”) only if the control signal 606 driving the NMOSFET 318 at the output NOUT1 is in turn-on state (logic “1”). Similarly, the control signal 609 driving the PMOSFET 317 at the output POUT1 is in turn-on state (logic “0”) only if the control signal 608 driving the NMOSFET 319 at the output NOUT2 is in turn-on state (logic “1”).
As described above, another characteristic of the invention is a synchronous operation of the frequency and phase. As shown in
FIG. 7A and
The raising edge detector circuit 802 further includes an AND gate 812 which inputs are connected to the output 505 of the comparator 810 and the output 815 of the raising edge detector circuit 802. The output 813 of the AND gate 812 is inputted to the NAND gate 814 to control the operation of the triangular generator.
It should be apparent to those skilled in the art that the above description is only illustrative of specific embodiments and examples of the invention. The invention should therefore cover various modifications and variations made to the herein-described structure and operations of the invention, provided they fall within the scope of the invention as defined in the following appended claims.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8648789 *||Jun 7, 2006||Feb 11, 2014||Nxp, B.V.||Control device for controlling the output of one or more full-bridges|
|US20100277408 *||Jun 7, 2006||Nov 4, 2010||Nxp B.V.||Control device for controlling the output of one or more full-bridges|
|U.S. Classification||345/102, 345/61, 315/100, 345/87, 345/213, 345/98, 315/209.00R, 345/211, 345/100, 345/89, 345/88, 345/212, 315/291|
|International Classification||G09G3/36, H05B41/392, H05B41/282, G09G3/34|
|Cooperative Classification||H05B41/3927, H05B41/2828, Y02B20/186|
|European Classification||H05B41/392D8, H05B41/282P4|