|Publication number||USRE42250 E1|
|Application number||US 09/927,426|
|Publication date||Mar 29, 2011|
|Filing date||Aug 10, 2001|
|Priority date||Dec 29, 1994|
|Publication number||09927426, 927426, US RE42250 E1, US RE42250E1, US-E1-RE42250, USRE42250 E1, USRE42250E1|
|Inventors||William A. Phillips, Mario Paparo, Piero Capocelli|
|Original Assignee||Stmicroelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (24), Classifications (11)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a Reissue of application Ser. No. 08/897,187, filed on Jul. 21, 1997, which is a Continuation of application Ser. No. 08/595,512, filed on Feb. 1, 1996, which has been abandoned, which is a continuation of Ser. No. 08/411,556, filed on Mar. 28, 1995, which has been abandoned, which is a Continuation In Part of Ser. No. 08/365,685, filed Dec. 29, 1994, and entitled A DELAY CIRCUIT AND METHOD, which is a pending application.
1. Field of the Invention
This invention relates to electronic circuits used to delay signals and more specifically to circuits used to delay the turn-on of a power transistor in a bridge configuration.
2. Description of the Relevant Art
The problem addressed by this invention is encountered when power transistors are used to drive a prior art bridge configuration such as in FIG. 1. The bridge configuration 2 can be used to power motors, drive solenoids, and the like. The bridge configuration 2 is characterized by the high side driver transistor 4 being connected in series to a low side driver transistor 6 across the voltage of a power supply. In this configuration, node 12 is driven to the power supply voltage when the high side transistor 4 is on and transistor 6 is off. Conversely, node 12 is sunk to ground when high side transistor 4 is off and lowside transistor 6 is on. If the high side and low side transistors are both turned off, then node 12 is at a high impedance state. However, if both high side 4 and low side 6 transistors are turned on, then the transistors are shorting the power supply voltage to ground which would draw an excessive amount of current and would damage one or both of the transistors. The bridge configuration is never used with both high side and low side drivers on at the same time because of the potentially disastrous results. Consequently, it is common to use a delay circuit is part of the control logic in the control block 9 to prevent the turn-on of one driver transistor until the other driver is turned off. In principle, one of the drivers is turned off while the other driver is turned on, but only after the delay circuit has delayed the turn-on by an amount of time which will guarantee that the other driver is in fact turned off.
Therefore, the rising signal on the input of the delay circuit 20 is passed on to the output of the delay signal 33, but only after the delay created by the time constant of resistor 26 and capacitor 28. However, prior art delay circuit 20 is limited since it often requires relatively large capacitors and/or resistors to obtain long delays. The requirement of a large capacitor or resistor is undesirable since a large capacitor or resistor typically requires large amounts of silicon on an integrated circuit or requires an external connection for an external capacitor. Since the cost of a integrated circuit is directly proportional to the die size, it is desirable to reduce the size of a circuit whenever possible.
Therefore, it is an object of the invention to provide relatively long delays without requiring a large capacitor or a large resistor.
It is further an object of this invention to provide a delay circuit which provides relatively long delays and without requiring large area on an integrated circuit.
It is further an object of this invention to provide a delay circuit which reduces the cost of a delay circuit by reducing the die area necessary to implement the circuit.
These and other objects, features, and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read with the drawings and appended claims.
Referring now to
In operation, an input signal is received at the gates of transistors 48 and 50. If the input signal is at a low voltage, transistor 48 turns on which allows for transistors 46 and 54 to conduct a constant current through transistor 54. The constant current through transistor 54 discharges capacitor 56. Conversely, capacitor 56 is charged when the input signal is at a high voltage since this high input voltage turns transistor 48 off and rums transistor 50 on. Therefore, transistors 46 and 54 are held off while transistors 42 and 52 are turned on. Thus, transistor 52 charges capacitor 56 with the constant current source formed by transistor 42, resistor 44, and transistor 52. The voltage on capacitor 56 buffered to the output by two inverters formed with transistors 58, 60, 62, and 64. In short, an input signal is received by transistors 48 and 50, delayed by the constant current sources or drains in combination with the capacitor, and then buffered by two inverters to the output of the delay circuit 40.
More specifically, transistors 42, 52 and 50 combine with resistor 44 to form a constant current source when the input to the delay circuit is at a high voltage. In this state, transistor 50 draws current through resistor 44 which turns on the current mirror formed by transistors 42 and 52. In the preferred embodiment, Vdd is about 5 volts and R44 is approximately 84 Kohms which defines the current through transistor 42 at about 40 microamps. Transistor 42 has an w/l (area) of 180/9 and transistor 52 has an w/l (area) of 9/9. Thus, the current through transistor 42 is approximately 20 times the current through transistor 52. Thus the current in transistor 52 is approximately 2 microamps. This constant current charges capacitor 56 when the input voltage is high. In general, the time delay can be approximately described as
time delay=(switch voltage/Vr44) (C56) (R44) (current ratio)
switch voltage=the switch voltage for the inverter
Vr44=the voltage drop across R44
C56=the capacitance of capacitor 56
R44=the resistance of resistor 44
current ratio=the current ratio of the applicable current mirror.
In an embodiment, a 10 picofarad capacitor, 84 kilo-ohm resistor, and current ratio of 20 are used which yields a delay of approximately (2.5 v/4 v) (10 pF) (84 k) (20)=10.5 microseconds. (Note that the voltage drop across resistor 44 is reduced from Vdd by the voltage drop across the transistors in the current path, which in this case totals to around 1 volts.)
Conversely, transistors 48, 46, and 54 combine with resistor 44 to form a constant current drain for discharging capacitor 56. When the input of delay circuit 40 is at a low voltage, transistor 50 is off and transistor 48 is on. This allows current to flow through transistor 48 and resistor 44, thus, turning on transistors 46 and 54. With an 84 kohm resistor and 5 volt Vdd, the current through transistor 46 is approximately equal to 40 microamps. Transistor 46 has 20 times the area as transistor 54 so that the current through transistor 54 is about 2 microamps. Therefore, capacitor 56 is discharged at the rate of 2 microamps which creates a delay of about 10.5 microseconds when the input of delay circuit is low.
Transistors 58 and 60 are configured to invert the voltage on the capacitor 56. When the voltage on the gates of transistors 58 and 60 are low, the voltage on output is low and vice versa. Transistors 62 and 64 are also configured as an inverter with the gates configured as the input and the drain of transistor 62 connected to the drain of transistor 64 to form the output of the inverter. The first and second inverter form the output stage of the delay circuit and buffer the voltage on the capacitor to the output of the delay circuit 40. It is understood that numerous circuits can be used for buffering voltages without departing from the spirit and scope of the invention.
The embodiment of the invention offers the advantage providing a delay which over 12 times longer than the delay created by a prior art circuit using the same resistor and capacitor value. Alternatively, this embodiment of the invention creates the equivalent delay, but uses a resistor and/or capacitor which is approximately 12 times smaller than is required by the prior art circuit to achieve the same time delay.
In operation, this embodiment operates in an analogous manner to the previous embodiment, but with the added feature that capacitor 56 can now be charged or discharged by one or more pairs of current mirrors. Transistors 48 and 50 are the input transistors; transistors 42 and 46 are the bias transistors; transistors 82, 86, 90, and 94 are the constant-current source transistors; and transistors 84, 88, 92, and 96 are the constant-current drains, for this embodiment.
More specifically, an input signal enters the circuit through the gate of transistor 48 which turns on transistor 42. Since the gate of transistor 42 is connected to the gates of transistors 82, 86, 90, and 94, transistor 42 provides the bias voltage for transistors 82, 86, 90, and 94 such that the current flow in the respective transistor is proportional (mirrored) to the current through transistor 42. However, transistors 82, 86, 90, and 94 will only be turned on if programmable delay control circuit 80 has enabled one of those transistors by providing the source of the respective transistor with a positive voltage. Therefore, the rate of delay or the rate of charging capacitor 56 is controlled by the programmable delay control circuit 80 and the relative ratios of transistors 42 to transistors 82, 86, 90, and 94. Inversely, when the input signal goes low, transistor 50 turns on bias transistor 46 which thereby provides the bias voltage to turn on transistors 84, 88, 92, and 96 to remove the charge from capacitor 56. Again, transistors 84, 88, 92, and 96 will not drain any current from capacitor 56 unless the transistors have been enabled by programmable delay control circuit 80 providing a sufficiently low voltage to the respective transistors drain. In this disclosure, it is assumed that the enable signals from the programmable delay control signal are digital in nature with sufficient current drive to drive the MOSFET transistors.
It will be clear to persons skilled in the art that additional transistor pairs can be added to the circuit to increase the range of programmability. Four transistor pairs are disclosed for illustrative purposes and could easily be modified to less pairs or more pairs by persons skilled in the art. Additionally, persons skilled in the art can vary the ratio of the current mirrors to further increase the range of programmability. By adjusting the current mirror ratios and/or increasing the number of transistor pairs persons skilled in the art can easily design a programmable delay which meets a given design criteria for versatility as well as flexibility.
Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4740743||Sep 29, 1986||Apr 26, 1988||Siemens Aktiengesellschaft||Switchable bipolar current source|
|US4806804||Mar 9, 1987||Feb 21, 1989||Deutsche Itt Industries Gmbh||Mosfet integrated delay line for digital signals|
|US4812687 *||Jul 13, 1988||Mar 14, 1989||International Business Machines Corporation||Dual direction integrating delay circuit|
|US4875020||Dec 21, 1988||Oct 17, 1989||Sgs-Thomson Microelectronics S.R.L.||Analog integrated circuit having intrinsic topologies and characteristics selectable by a digital control|
|US5006738||Jun 13, 1990||Apr 9, 1991||Sony Corporation||Delay circuit for integrated circuit|
|US5057722||Jun 20, 1990||Oct 15, 1991||Nec Corporation||Delay circuit having stable delay time|
|US5068628||Nov 13, 1990||Nov 26, 1991||Level One Communications, Inc.||Digitally controlled timing recovery loop|
|US5081380 *||Oct 16, 1989||Jan 14, 1992||Advanced Micro Devices, Inc.||Temperature self-compensated time delay circuits|
|US5118965 *||Mar 7, 1990||Jun 2, 1992||Nokia Mobile Phones Ltd.||Analog pulse converter from square to triangular to cos2 wave|
|US5136260 *||Mar 8, 1991||Aug 4, 1992||Western Digital Corporation||PLL clock synthesizer using current controlled ring oscillator|
|US5175452||Sep 30, 1991||Dec 29, 1992||Data Delay Devices, Inc.||Programmable compensated digital delay circuit|
|US5227679||Jan 2, 1992||Jul 13, 1993||Advanced Micro Devices, Inc.||Cmos digital-controlled delay gate|
|US5231319||Aug 22, 1991||Jul 27, 1993||Ncr Corporation||Voltage variable delay circuit|
|US5300837||Sep 17, 1992||Apr 5, 1994||At&T Bell Laboratories||Delay compensation technique for buffers|
|US5317219||Oct 8, 1992||May 31, 1994||Data Delay Devices, Inc.||Compensated digital delay circuit|
|US5382840||Sep 30, 1992||Jan 17, 1995||Siemens Aktiengesellschaft||Analog delay circuit configuration|
|US5477182 *||Apr 1, 1994||Dec 19, 1995||U.S. Philips Corporation||Delay circuit for delaying differential signals includes separately controllable first and second load and clamp circuits for effecting different delay times|
|US5926051 *||Sep 6, 1996||Jul 20, 1999||Mitsubishi Denki Kabushiki Kaisha||Self refresh timer|
|EP0405319A1||Jun 20, 1990||Jan 2, 1991||Nec Corporation||Delay circuit having stable delay time|
|EP0535359A1||Aug 21, 1992||Apr 7, 1993||Siemens Aktiengesellschaft||Analog delay circuit arrangement|
|JP4144309B2||Title not available|
|JPH01161913A||Title not available|
|JPH01279624A *||Title not available|
|JPH04144309A||Title not available|
|U.S. Classification||327/285, 327/278, 327/263, 327/288|
|International Classification||H03K5/13, G05F3/24|
|Cooperative Classification||H03K5/131, H03K5/133, G05F3/242|
|European Classification||H03K5/13B, H03K5/13D2|