|Publication number||USRE42293 E1|
|Application number||US 12/141,850|
|Publication date||Apr 12, 2011|
|Filing date||Jun 18, 2008|
|Priority date||Dec 9, 2000|
|Also published as||US7096373, US20020073351|
|Publication number||12141850, 141850, US RE42293 E1, US RE42293E1, US-E1-RE42293, USRE42293 E1, USRE42293E1|
|Inventors||Jang Geun Oh|
|Original Assignee||Lg Electronics Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Classifications (25), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a reissue patent application of U.S. Pat. No. 7,096,373, which is issued from U.S. application Ser. No. 10/003,345.
1. Field of the Invention
The present invention relates to an apparatus and a method of controlling clock frequency generation, and more particularly, to an apparatus and a method for a portable device.
2. Background of the Related Art
In general, a portable device such as a notebook computer can be supplied with its necessary electric energy either by a battery or an AC power line. However, because battery capacity is limited, a notebook cannot be used for more than a few hours if its power is supplied from the battery.
A PLL (Phase Lock Loop) circuit 110 is embedded in the CPU 11. The PLL circuit 110 multiplies the 100 MHz clock from the clock generator 10 differently based on a current power supplying mode. For example, the PLL circuit 110 multiplies the 100 MHz clock 1 by a factor of six to produce a 600 MHz internal clock if an AC power mode (PWR mode) is detected, and it multiplies the 100 MHz clock 1 by a factor of five to produce a 500 MHz clock if a battery power mode is detected.
Because power consumption of a CPU 11 is proportional to the speed of a clock driving the CPU 11, if a 500 MHz internal clock is used in a battery supplying mode, processing speed is lowered and power dissipation is decreased in comparison with a 600 MHz internal clock. Therefore, battery life is extended.
However, in a related portable computer, a host bus 3 to which both a CPU 11 and a bridge controller 12 are connected is driven by a bus clock to bridge controller 12 whose speed is fixed regardless of power supplying mode. Therefore, power saving in a battery supplying mode is less effective.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a method of reducing clock speed of a bus in order to extend battery suppliable time longer when electric energy is fed to a portable computer such as a notebook from an equipped battery.
In order to achieve at least the above-described objects of the present invention in a whole or in part, there is provided a portable device having a CPU and a bridge controller operating in one of AC power mode or battery power mode, wherein the improvement includes a clock generator generating a first clock signal for the CPU and a second clock signal for the bridge controller, wherein first and second clock signals are two distinct clock signals outputted by the clock generator and have different frequencies.
To further achieve at least the above-described objects of the present invention in a whole or in parts, there is provided a portable device having a CPU and a bridge controller, wherein the improvement includes a clock generator generating a first clock signal, and a clock adjustor operating in one of AC power mode or battery power mode, said clock adjustor generating a second clock signal for the CPU and a third clock signal for the bridge controller, wherein the second and third clock signals are two distinct clock signals outputted by the clock adjustor and have different frequencies.
To further achieve at least the above-described objects of the present invention in a whole or in parts, there is provided a method for optimizing clock speed generation, including receiving a base clock signal, multiplying the base clock signal by a first factor to produce a first higher frequency clock signal, wherein the first higher frequency clock signal is phase-locked with the base clock signal, receiving a power mode signal indicating either an AC or a battery source, and selectively outputting the first higher frequency clock signal to a first device when the AC source is indicated and outputting the base clock signal to the first device when the battery source is indicated.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:
In order that the invention may be fully understood, preferred embodiments thereof will now be described with reference to the accompanying drawings.
The clock generator 20 may provide the CPU 11 with a 100 MHz CPU clock signals 101, the bridge controller 22 with a 66.7 MHz host clock signals 102 (lower in frequency than the 100 MHz CPU clock 101), and the video processor 23 with a 33.33 MHz clock signal 103 (lower in frequency than a conventional 66 MHz AGP clock).
A PLL circuit 210 may be included in the CPU 11. As aforementioned, the PLL circuit 110 may multiply the 100 MHz CPU clock 101 from the clock generator 20 selectively based on the current power supplying mode. For example, the PLL circuit 110 may multiply the frequency of a 100 MHz clock 101 by six if an external AC power is fed, and it may multiply the frequency by five if a battery is supplying necessary electric energy.
In addition, another PLL circuit 220 may be embedded in the bridge controller 22. The PLL circuit 220 may multiply the frequency of the 66.7 MHz host clock 102 from the clock generator 20 by one and a half to produce a 100 MHz PCI bus clock in an AC power supplying mode, and may use the 66.7 MHz host clock 102 as it is without frequency multiplication in a battery supplying mode.
The PLL comparator 221 may output a DC signal to increase or decrease the frequency of the internal oscillating clock generated by VCO 222 in proportion to the phase difference between two applied signals, so that the two applied signals become in phase exactly. Therefore, the frequency of the internal oscillating clock may be six times as high as that of the inputted 66.7 MHz host clock 102 while its phase is locked with the host clock 102. Accordingly, if the internal oscillating clock frequency is divided by 4, a 100 MHz clock whose phase is locked with the inputted host clock 102 may be produced and it can be used as a bus clock of a host bus through the bridge controller 22.
The switch 225 may select the 66.7 MHz host clock 102 when the power supplying mode is indicative of the battery mode, while it may select the 100 MHz clock 102a divided from the internal oscillating clock in the external AC supplying mode. If a battery is supplying electric energy, the above elements 221, 222, 223, and 224 need not be operative, thus it may be preferable to cut off power supply for them in that mode.
The video processor 23 may also include PLL circuit 230. The PLL circuit 230 of the video processor 23 may multiply the 33.33 MHz clock from the clock generator 20 by two to produce a 66.7 MHz AGP video clock in AC power supplying mode, and may use the 33.33 MHz clock without frequency multiplication in battery supplying mode.
The structure of the PLL circuit 230 may be similar to that shown in
In the portable computer configured as above, if a battery is supplying electric energy, the frequency of a bus clock provided to a host bus by the bridge controller 22 may be decreased to 66.7 MHz from 100 MHz, and the frequency of an internal clock used by the video processor 23 may also be decreased to 33.33 MHz from 66.7 MHz. This clock speed reduction results in extension of battery life.
A detecting means, which outputs a signal indicating power supplying mode after detecting which power source between an external AC power and a battery is supplied at present, can be integrated into the bridge controller 22 or may be implemented as a separate device.
However, a PLL circuit 110 for producing 600 MHz or 500 MHz by multiplying 100 MHz differently may be embedded in the CPU 11 as mentioned above.
The frequency 33.33 MHz of the basic clock 114 applied to the PLL block 40 from the clock generator 30 may be equal to the lowest among clock frequencies the PLL block 40 provides in battery supplying mode. The PLL block 40 may be configured as in
A phase comparator 421 of
In phase-locked state of the 200 MHz clock, a 100 MHz clock may be produced from a ½ divider 423 dividing the 200 MHz clock by two, and 66.7 MHz clock may also be produced from a ⅓ divider 425 dividing the 200 MHz clock by three. Therefore, the 100 MHz clock 111 from the ½ divider 423 may be applied to the CPU 11 at all times.
In the circuit of
If electric power is fed from a battery, ‘B’ terminals are chosen; therefore, the host clock 112 and the AGP clock 113 become 66.7 MHz and 33.33 MHz, respectively.
Accordingly, lower frequency clocks in battery mode than in AC mode may be provided for corresponding devices, which means that power consumption is reduced when a battery is supplying necessary electric energy.
In the embodiments of
As can be appreciated, based on the disclosure of the preferred embodiments, the output of the clock generators 20 and 30 of
In another embodiment, the clock frequency adjusting means may be integrated into a clock generator 30. The clock frequency adjusting means mentioned here is a device which adjusts or maintains frequency of an input clock based on which power source is feeding electric energy, and applies the frequency-adjusted or -maintained clock to external devices.
An alternative embodiment of the invention, the frequency adjusting means may be embedded in other combinations of the clock generator, PLL ASIC, CPU, bridge controller, video processor, and/or other devices.
The bus clock controlling apparatus of a portable computer according to the present invention reduces speed of a bus clock and a device clock in battery mode. Therefore, electric energy stored in a battery is saved, extending battery life.
In addition, the present invention can be applied to a PCI bus for data communication among peripheral devices connected to the PCI bus by providing the clock to another Bridge controller for a PCI bus in the same way as for the host bus.
The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.
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|U.S. Classification||713/320, 713/323, 713/322, 711/154, 713/600, 327/44|
|International Classification||G06F13/00, H03L7/23, G06F1/08, H03L7/18, G06F1/32, G06F1/06|
|Cooperative Classification||G06F1/324, G06F1/08, H03L7/18, G06F1/3203, G06F1/06, G06F1/263, Y02B60/1217|
|European Classification||G06F1/32P, G06F1/06, G06F1/08, H03L7/18, G06F1/32P5F, G06F1/26B|