|Publication number||USRE42363 E1|
|Application number||US 12/557,643|
|Publication date||May 17, 2011|
|Priority date||Sep 5, 2003|
|Also published as||CN1846311A, EP1685600A1, EP1685600A4, US7180165, US20050051903, WO2005027225A1|
|Publication number||12557643, 557643, US RE42363 E1, US RE42363E1, US-E1-RE42363, USRE42363 E1, USRE42363E1|
|Inventors||Mark Ellsberry, Charles E. Schmitz, Chi She Chen, Victor Allison, Jon Schmidt|
|Original Assignee||Sanmina-Sci Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (89), Referenced by (8), Classifications (35), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Various embodiments of the invention pertain to stackable electronic assemblies. At least one embodiment of the invention pertains to a memory module using these stackable assemblies that enables higher memory densities.
Semiconductor dice, such as memory dice, are often packaged for protection and ease of use. One type of package is a ball grid array package (BGA) in which a semiconductor die is mounted on a substrate. The semiconductor die has a plurality of bond pads that are electrically connected, via wires bonded between the metal traces on the substrate and on the die. The traces on the substrate terminate at contact pads where conductive elements, such as solder balls, are attached. The BGA package can then be mounted on a circuit board and electrically connected via the conductive elements. The BGA package may be electrically connected to metal traces on the circuit board in various ways, including applying heat or ultrasound to the conductive elements (e.g., solder balls).
One consideration when packaging semiconductor dice is thermal cracking. Thermal cracking may occur when the differences between the thermal coefficients of expansion for two materials causes solder points between them to crack. For instance, if a semiconductor die was directly soldered onto a substrate having a substantially different coefficient of expansion, temperature cycling may eventually cause soldered points, such as solder balls, to crack thus causing an electrical discontinuities. To solve this problem when packaging semiconductor dice, the area between the semiconductor die and the substrate is often underfilled, with epoxies and/or other materials, to assist in preventing thermal cracking.
Additionally, semiconductor dice are typically quite fragile, sensitive to physical impact, and environmental conditions. Thus, a die or silicon chip is typically encapsulated in an epoxy or plastic to absorb and dissipate impact forces and to protect it from environmental conditions.
However, both underfilling and/or encapsulating a device or die increases the heat retained by the device. Maintaining a low operating temperature typically increases the reliability, performance, and life of an electronic device. Thus, the increase in temperature resulting from underfilling and/or encapsulation is an undesirable side effect of increasing the reliability by protecting an electronic device.
One type of semiconductor component is a memory component, which typically includes a memory die mounted on a substrate with or without encapsulation. Over the years, memory components have remained the same dimensional size while providing increased storage capacity. Generally, this has been accomplished by reducing the size of the individual storage elements on the memory component.
Memory components are often used in memory modules, where a number of these memory components are mounted on a single substrate. However, the number of memory components that may be placed on a substrate is limited by the size of the module. Modules must typically meet the functional and physical specifications established by industry standards or other limitations imposed by a particular application. Thus, the storage capacity of a memory module is often limited by physical size restrictions. In particular, the surface area available on the memory module limits the number of memory components that can be mounted thereon.
One technique to increase the storage capacity of memory modules has been to stack surface area. However, the number of memory components that may be stacked is limited by the height restrictions on the memory module as well as the complexities of accessing stacked memory devices using existing bus interfaces designed for non-stacked architectures.
Thus, the prior art is still seeking an economical solution for increasing the stacking of memory devices while addressing the packaging requirements of memory modules.
One aspect of the invention provides a stackable semiconductor device architecture with each semiconductor device soldered onto a chip-scale ball grid array package. A second aspect of the invention provides a way to reduce thermal cracking of soldered points by using controlled thermal expansion substrates that substantially match the coefficient of expansion of semiconductor devices mounted thereon. A third aspect of the invention provides a semiconductor die mounting technique that improves heat dissipation by exposing all six surfaces of the semiconductor die mounted on a chip-scale package. A fourth aspect of the invention provides a chip-scale ball grid array package that permits mounting of components, such as capacitors and resistors, thereon. A fifth aspect the invention provides a staggered routing scheme that enables the use of the same trace routing at every level of the stacked architecture.
One implementation of the invention provides a memory module with stacked chip-scale ball grid array packages that increase the memory capacity of the module, while conforming to module dimensional requirements.
In the following description numerous specific details are set forth in order to provide a thorough understanding of the invention. However, one skilled in the art would recognize that the invention may be practiced without these specific details. In other instances, well known methods, procedures, and/or components have not been described in detail so as not to unnecessarily obscure aspects of the invention.
In the following description, certain terminology is used to describe certain features of one or more embodiments of the invention. For instance, “die” refers to a semiconductor device, such as a silicon memory device, that is not packaged or covered in a protective plastic, epoxy, or other material. The term “underside coupling members” is used to refer to such relatively rigid electrical coupling members as conductive bumps, conductive balls (e.g., solder or gold balls), and conductive rods.
One aspect of the invention provides a stackable semiconductor device architecture with each semiconductor device soldered onto a chip-scale package (CSP) having ball grid array connections. A second aspect of the invention provides a way to reduce thermal cracking of soldered points by using controlled thermal expansion substrates that substantially match the coefficient of expansion of semiconductor die mounted thereon. A third aspect of the invention provides a die mounting technique that improves heat dissipation by exposing all six surfaces of a die mounted in a chip-scale package. A fourth aspect of the invention provides a chip-scale package that permits mounting of signal conditioning (filtering) components, such as capacitors and resistors, thereon. A fifth aspect the invention provides a staggered routing scheme that enables the use of the same trace routing for every level of the stacked architecture.
One implementation of the invention provides a memory module with stacked memory components that increases the memory capacity of the module, while conforming to module dimensional requirements.
One aspect of an implementation of the invention provides that the solder balls 108 have a higher profile than the semiconductor die 102 to mechanically protect the semiconductor die 102, from direct impact, etc., without the disadvantages of encapsulation. The solder balls 108 should be sufficiently large so that they rise above the semiconductor die 102 on the first surface of the chip-scale substrate 104. Mounting the semiconductor die 102 on the same side as solder balls 108 creates a flip chip assembly, where the semiconductor package can then be coupled to other substrates via the solder balls. Additionally, the higher profile solder balls permit the package 100 to be mounted on other substrates without interference from the semiconductor die 102.
Another aspect of the invention provides a way to reduce thermal cracking in the contacts between a semiconductor die and the substrate on which it is mounted. Conventional chip mounting techniques typically utilize wire bonds to electrically couple the semiconductor die to a contact point on the substrate. However, such mounting techniques typically require that the space between the semiconductor die and the mounting surface be underfilled or injected with a securing material, such as an epoxy, to fasten the semiconductor die to the substrate. However, as previously discussed, this is undesirable because it tends to hinder heat dissipation from the semiconductor device.
As illustrated in
Typical mounting substrates have a coefficient of expansion of approximately sixteen (16) to eighteen (18) parts per million per degree Celsius (ppm/° C.) while silicon semiconductors have a nominal coefficient of expansion of approximately three (3) ppm/° C. Through temperature cycling, such disparity in coefficients of expansion often leads to cracks in electrical interconnects between such mounting substrates and silicon semiconductor devices. Employing a Coffin-Manson-type analysis, for instance, an adequate range of “matching” coefficients of expansion may be determined. An acceptable match will vary depending on the ranges of temperatures over which the materials will be cycled, the number of temperature cycles expected in the life of a device, the dimensions of the substrate, the material employed to couple a first substrate to a second substrate, etc. The closer the two materials (e.g., silicon semiconductor and mounting substrate) are to an exact match, the better the situation. Application-specific thermal-mechanical reliability may be readily tailored to meet the requirements of the specific operating environment (e.g., solder and/or gold ball interconnections and/or conductive polymer materials).
In one implementation of the invention, a chip-scale ball grid array package includes a controlled CTE mounting substrate, having a coefficient of expansion of between six (6) and nine (9) ppm/° C., and a silicon semiconductor device having a nominal coefficient of expansion of approximately three (3) ppm/° C. The coefficient of expansion of the mounting substrate may be adjusted by varying its composition.
According to a Coffin-Manson-type analysis of a CTE material known as Thermount 85 NT, a coefficient of expansion of approximately eight (8) ppm/° C. is acceptable for memory modules using silicon semiconductor devices having a coefficient of expansion of approximately three (3) ppm/° C. Such match is acceptable for dual in-line memory module (DIMM) applications, for instance.
Generally, the invention employs substrate materials made from a tailored CTE to assure the reliability for a given device in an operating environment. Some of the types of materials that may be used include:
Another aspect of the invention provides improved heat dissipation from the semiconductor die 102 by leaving all six surfaces of the die exposed. Unlike the prior art that is typically underfilled or completely encapsulated, the present invention exposes all six sides of a semiconductor die, including a substantial portion of the underside of the semiconductor die. That is, by mounting the semiconductor die 102 using solder balls, under bump metallization, and/or other similar electrically coupling members 106, a gap is created between the chip-scale substrate 104 and the underside of the semiconductor die 102. Because all of the surfaces of the die 102, including the underside surface, are now exposed to airflow, the semiconductor die 102 has improved heat dissipation. Note that the fact that the solder balls 108 have a higher profile than the mounted semiconductor die 102 means that the upper surface of the semiconductor die 102 is also exposed to airflow.
One aspect of the invention provides a chip-scale ball grid array package that permits mounting of components, such as capacitors and resistors, thereon. By mounting the semiconductor die 305 on the substrate 304 using connects 303, surface space is freed on the substrate above semiconductor die 305. In one implementation, the surface space above the semiconductor die always includes pads 306 on which signal conditioning components may be mounted. This surface area may have one or more pads 306 for connecting signal filtering components thereon. This permits mounting on-chip electrical components 310, such as capacitors and resistors, which may be used for signal conditioning to and!or from the semiconductor die 305. Being able to mount components 310 on the package substrate itself (e.g., chip-scale substrate) is an advantage over the prior art that was limited to mounting said components only external to the package. In one implementation of the invention, such components 310 are signal conditioning capacitors and pull-up/pull-down resistors.
According to other implementations, other ball grid array configurations may be employed without deviating from the invention.
In one implementation of the invention, the outboard columns of balls/electrical interconnections (e.g., 404 and 406) is two wide per side times whatever length is required to effectively address the maximum number of chip-scale packages to be stacked. For example, the basic I/O count required for a typical two hundred and fifty-six (256) Megabyte (Mb) synchronous dynamic (SD) random access memory (RAM) silicon device is forty-eight (48), two of which are for unique “addressing”. Hence, in a one high implementation, only forty-eight (48) I/O ball/electrical interconnections 404 and 406 would be required. Since each additional device requires unique clock enable and chip select addressing interconnects, a two high stack would require that all chip-scale packages in that stack have fifty (50) interconnects 404 and 406. A four-high stack would require fifty-four (54) ball/electrical interconnections 404 and 406 and so forth.
In one implementation of the invention, the semiconductor devices (e.g., 102) may be random access memory devices mounted on stacked chip-scale packages (e.g., 602, 604, 606, 608, 610, and 612). The stacked packages (e.g., 602, 604, 606, 608, 610, and 612) are then mounted on either or both sides of a substrate to form a memory module 600, such as a single inline memory module (SIMM) or dual inline memory module (DTMM). The dimensional requirements of the memory module 600 may limit the number of packages (e.g., 100) that may be stacked.
In yet other implementations, the stacked packages may be mounted directly on a computer motherboard or other type of module.
According to one embodiment of the invention, identical chip-scale package substrates 701a-d are employed at each level of the stacked package 700 with the semiconductor dice 703a-d mounted in the same manner on each chip-scale substrate 701a-d. Using identical substrates 701a-d for every level of the stacked package 700 and mounting the dice 703a-d in an identical manner avoids the costs and difficulties of having to customize each level. Thus, a plurality of chip-scale ball grid array packages 701a-d may be manufactured and later assembled into a stack without regard as to any particular order.
The use of identical chip-scale packages at every level of a stack package 700 is made possible by a novel routing scheme that permits accessing each semiconductor die 703a-d independently and without customization of the substrates 701a-d. The novel routing scheme provides cascading connections through all levels of the stack package 700 to electrically couple each semiconductor die 703a-d to a primary access point (e.g., the solder balls on substrate 701a).
According to implementation of the novel routing scheme, each substrate 701a-d includes a plurality of solder balls 705 mounted on a first surface of the substrate 701a-d and a plurality of corresponding pads 707 on a second opposite surface of the substrate 701a-d. Interconnects 709 serve to electrically couple the solder balls 705 to the pads 707. A cascading scheme, as illustrated in
Note that the solder balls may be cascaded in different ways and utilizing different solder ball layouts without deviating from the invention. For example, a cascading routing scheme may be implemented using chip-scale packages similar to that illustrated in
In yet other implementations, only part of the solder balls are interconnected using a cascading scheme while part of the remaining solder balls are connected in a non-cascading manner across the stacked package. That is, some of the solder balls in the same position across all layers of a stack may be commonly connected.
Oftentimes, the size of a stacked memory or semiconductor package is limited by the space available on which to mount it in a particular implementation. Thus, one implementation of the invention employs tightly spaced components to maximize semiconductor or memory density of a stack package. For instance, in one implementation of the invention, the substrate (e.g., 104 in
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications are possible. Those skilled, in the art will appreciate that various adaptations and modifications of the just described preferred embodiment can be configured without departing from the scope and spirit of the invention. For example, while a semiconductor die has been used to illustrate the invention, any other electronic device or component may be used instead, with one or more aspects of the invention, without deviating from the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.
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|U.S. Classification||257/686, 438/109, 257/777, 257/685, 257/778, 438/108, 361/760|
|International Classification||H01L23/02, H01L23/498, H01L25/065|
|Cooperative Classification||H01L2224/16225, H01L2225/1023, H01L2225/1058, H01L2225/0652, H01L2924/15192, H01L2225/06572, H01L24/16, H01L2924/19105, H01L2924/19106, H01L2924/19043, H01L2924/15331, H01L23/49816, H01L23/49838, H01L2924/10253, H01L23/50, H01L2924/3511, H01L2924/15311, H01L2225/06541, H01L2225/06517, H01L2924/19041, H01L2924/1532, H01L25/105, H01L2924/01079|
|European Classification||H01L23/498C4, H01L25/10J|
|Jun 5, 2014||AS||Assignment|
Owner name: US BANK NATIONAL ASSOCIATION, AS NOTES COLLATERAL
Free format text: SECURITY INTEREST;ASSIGNORS:SANMINA CORPORATION, AS GRANTOR;SANMINA CORPORATION, F/K/A SANMINA-SCI CORPORATION, AS GRANTOR;HADCO SANTA CLARA, INC., AS GRANTOR;AND OTHERS;REEL/FRAME:033094/0826
Effective date: 20140604
|Jul 23, 2014||FPAY||Fee payment|
Year of fee payment: 8
|May 20, 2016||AS||Assignment|
Owner name: SANMINA-SCI CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHMIDT, JON;REEL/FRAME:038661/0580
Effective date: 20100208
Owner name: SANMINA-SCI CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ELLSBERRY, MARK;SCHMITZ, CHARLES E.;CHEN, CHI SHE;AND OTHERS;SIGNING DATES FROM 20040122 TO 20040202;REEL/FRAME:038661/0535