|Publication number||USRE42363 E1|
|Application number||US 12/557,643|
|Publication date||May 17, 2011|
|Priority date||Sep 5, 2003|
|Also published as||CN1846311A, EP1685600A1, EP1685600A4, US7180165, US20050051903, WO2005027225A1|
|Publication number||12557643, 557643, US RE42363 E1, US RE42363E1, US-E1-RE42363, USRE42363 E1, USRE42363E1|
|Inventors||Mark Ellsberry, Charles E. Schmitz, Chi She Chen, Victor Allison, Jon Schmidt|
|Original Assignee||Sanmina-Sci Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (89), Referenced by (8), Classifications (35), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Various embodiments of the invention pertain to stackable electronic assemblies. At least one embodiment of the invention pertains to a memory module using these stackable assemblies that enables higher memory densities.
Semiconductor dice, such as memory dice, are often packaged for protection and ease of use. One type of package is a ball grid array package (BGA) in which a semiconductor die is mounted on a substrate. The semiconductor die has a plurality of bond pads that are electrically connected, via wires bonded between the metal traces on the substrate and on the die. The traces on the substrate terminate at contact pads where conductive elements, such as solder balls, are attached. The BGA package can then be mounted on a circuit board and electrically connected via the conductive elements. The BGA package may be electrically connected to metal traces on the circuit board in various ways, including applying heat or ultrasound to the conductive elements (e.g., solder balls).
One consideration when packaging semiconductor dice is thermal cracking. Thermal cracking may occur when the differences between the thermal coefficients of expansion for two materials causes solder points between them to crack. For instance, if a semiconductor die was directly soldered onto a substrate having a substantially different coefficient of expansion, temperature cycling may eventually cause soldered points, such as solder balls, to crack thus causing an electrical discontinuities. To solve this problem when packaging semiconductor dice, the area between the semiconductor die and the substrate is often underfilled, with epoxies and/or other materials, to assist in preventing thermal cracking.
Additionally, semiconductor dice are typically quite fragile, sensitive to physical impact, and environmental conditions. Thus, a die or silicon chip is typically encapsulated in an epoxy or plastic to absorb and dissipate impact forces and to protect it from environmental conditions.
However, both underfilling and/or encapsulating a device or die increases the heat retained by the device. Maintaining a low operating temperature typically increases the reliability, performance, and life of an electronic device. Thus, the increase in temperature resulting from underfilling and/or encapsulation is an undesirable side effect of increasing the reliability by protecting an electronic device.
One type of semiconductor component is a memory component, which typically includes a memory die mounted on a substrate with or without encapsulation. Over the years, memory components have remained the same dimensional size while providing increased storage capacity. Generally, this has been accomplished by reducing the size of the individual storage elements on the memory component.
Memory components are often used in memory modules, where a number of these memory components are mounted on a single substrate. However, the number of memory components that may be placed on a substrate is limited by the size of the module. Modules must typically meet the functional and physical specifications established by industry standards or other limitations imposed by a particular application. Thus, the storage capacity of a memory module is often limited by physical size restrictions. In particular, the surface area available on the memory module limits the number of memory components that can be mounted thereon.
One technique to increase the storage capacity of memory modules has been to stack surface area. However, the number of memory components that may be stacked is limited by the height restrictions on the memory module as well as the complexities of accessing stacked memory devices using existing bus interfaces designed for non-stacked architectures.
Thus, the prior art is still seeking an economical solution for increasing the stacking of memory devices while addressing the packaging requirements of memory modules.
One aspect of the invention provides a stackable semiconductor device architecture with each semiconductor device soldered onto a chip-scale ball grid array package. A second aspect of the invention provides a way to reduce thermal cracking of soldered points by using controlled thermal expansion substrates that substantially match the coefficient of expansion of semiconductor devices mounted thereon. A third aspect of the invention provides a semiconductor die mounting technique that improves heat dissipation by exposing all six surfaces of the semiconductor die mounted on a chip-scale package. A fourth aspect of the invention provides a chip-scale ball grid array package that permits mounting of components, such as capacitors and resistors, thereon. A fifth aspect the invention provides a staggered routing scheme that enables the use of the same trace routing at every level of the stacked architecture.
One implementation of the invention provides a memory module with stacked chip-scale ball grid array packages that increase the memory capacity of the module, while conforming to module dimensional requirements.
In the following description numerous specific details are set forth in order to provide a thorough understanding of the invention. However, one skilled in the art would recognize that the invention may be practiced without these specific details. In other instances, well known methods, procedures, and/or components have not been described in detail so as not to unnecessarily obscure aspects of the invention.
In the following description, certain terminology is used to describe certain features of one or more embodiments of the invention. For instance, “die” refers to a semiconductor device, such as a silicon memory device, that is not packaged or covered in a protective plastic, epoxy, or other material. The term “underside coupling members” is used to refer to such relatively rigid electrical coupling members as conductive bumps, conductive balls (e.g., solder or gold balls), and conductive rods.
One aspect of the invention provides a stackable semiconductor device architecture with each semiconductor device soldered onto a chip-scale package (CSP) having ball grid array connections. A second aspect of the invention provides a way to reduce thermal cracking of soldered points by using controlled thermal expansion substrates that substantially match the coefficient of expansion of semiconductor die mounted thereon. A third aspect of the invention provides a die mounting technique that improves heat dissipation by exposing all six surfaces of a die mounted in a chip-scale package. A fourth aspect of the invention provides a chip-scale package that permits mounting of signal conditioning (filtering) components, such as capacitors and resistors, thereon. A fifth aspect the invention provides a staggered routing scheme that enables the use of the same trace routing for every level of the stacked architecture.
One implementation of the invention provides a memory module with stacked memory components that increases the memory capacity of the module, while conforming to module dimensional requirements.
One aspect of an implementation of the invention provides that the solder balls 108 have a higher profile than the semiconductor die 102 to mechanically protect the semiconductor die 102, from direct impact, etc., without the disadvantages of encapsulation. The solder balls 108 should be sufficiently large so that they rise above the semiconductor die 102 on the first surface of the chip-scale substrate 104. Mounting the semiconductor die 102 on the same side as solder balls 108 creates a flip chip assembly, where the semiconductor package can then be coupled to other substrates via the solder balls. Additionally, the higher profile solder balls permit the package 100 to be mounted on other substrates without interference from the semiconductor die 102.
Another aspect of the invention provides a way to reduce thermal cracking in the contacts between a semiconductor die and the substrate on which it is mounted. Conventional chip mounting techniques typically utilize wire bonds to electrically couple the semiconductor die to a contact point on the substrate. However, such mounting techniques typically require that the space between the semiconductor die and the mounting surface be underfilled or injected with a securing material, such as an epoxy, to fasten the semiconductor die to the substrate. However, as previously discussed, this is undesirable because it tends to hinder heat dissipation from the semiconductor device.
As illustrated in
Typical mounting substrates have a coefficient of expansion of approximately sixteen (16) to eighteen (18) parts per million per degree Celsius (ppm/° C.) while silicon semiconductors have a nominal coefficient of expansion of approximately three (3) ppm/° C. Through temperature cycling, such disparity in coefficients of expansion often leads to cracks in electrical interconnects between such mounting substrates and silicon semiconductor devices. Employing a Coffin-Manson-type analysis, for instance, an adequate range of “matching” coefficients of expansion may be determined. An acceptable match will vary depending on the ranges of temperatures over which the materials will be cycled, the number of temperature cycles expected in the life of a device, the dimensions of the substrate, the material employed to couple a first substrate to a second substrate, etc. The closer the two materials (e.g., silicon semiconductor and mounting substrate) are to an exact match, the better the situation. Application-specific thermal-mechanical reliability may be readily tailored to meet the requirements of the specific operating environment (e.g., solder and/or gold ball interconnections and/or conductive polymer materials).
In one implementation of the invention, a chip-scale ball grid array package includes a controlled CTE mounting substrate, having a coefficient of expansion of between six (6) and nine (9) ppm/° C., and a silicon semiconductor device having a nominal coefficient of expansion of approximately three (3) ppm/° C. The coefficient of expansion of the mounting substrate may be adjusted by varying its composition.
According to a Coffin-Manson-type analysis of a CTE material known as Thermount 85 NT, a coefficient of expansion of approximately eight (8) ppm/° C. is acceptable for memory modules using silicon semiconductor devices having a coefficient of expansion of approximately three (3) ppm/° C. Such match is acceptable for dual in-line memory module (DIMM) applications, for instance.
Generally, the invention employs substrate materials made from a tailored CTE to assure the reliability for a given device in an operating environment. Some of the types of materials that may be used include:
Another aspect of the invention provides improved heat dissipation from the semiconductor die 102 by leaving all six surfaces of the die exposed. Unlike the prior art that is typically underfilled or completely encapsulated, the present invention exposes all six sides of a semiconductor die, including a substantial portion of the underside of the semiconductor die. That is, by mounting the semiconductor die 102 using solder balls, under bump metallization, and/or other similar electrically coupling members 106, a gap is created between the chip-scale substrate 104 and the underside of the semiconductor die 102. Because all of the surfaces of the die 102, including the underside surface, are now exposed to airflow, the semiconductor die 102 has improved heat dissipation. Note that the fact that the solder balls 108 have a higher profile than the mounted semiconductor die 102 means that the upper surface of the semiconductor die 102 is also exposed to airflow.
One aspect of the invention provides a chip-scale ball grid array package that permits mounting of components, such as capacitors and resistors, thereon. By mounting the semiconductor die 305 on the substrate 304 using connects 303, surface space is freed on the substrate above semiconductor die 305. In one implementation, the surface space above the semiconductor die always includes pads 306 on which signal conditioning components may be mounted. This surface area may have one or more pads 306 for connecting signal filtering components thereon. This permits mounting on-chip electrical components 310, such as capacitors and resistors, which may be used for signal conditioning to and!or from the semiconductor die 305. Being able to mount components 310 on the package substrate itself (e.g., chip-scale substrate) is an advantage over the prior art that was limited to mounting said components only external to the package. In one implementation of the invention, such components 310 are signal conditioning capacitors and pull-up/pull-down resistors.
According to other implementations, other ball grid array configurations may be employed without deviating from the invention.
In one implementation of the invention, the outboard columns of balls/electrical interconnections (e.g., 404 and 406) is two wide per side times whatever length is required to effectively address the maximum number of chip-scale packages to be stacked. For example, the basic I/O count required for a typical two hundred and fifty-six (256) Megabyte (Mb) synchronous dynamic (SD) random access memory (RAM) silicon device is forty-eight (48), two of which are for unique “addressing”. Hence, in a one high implementation, only forty-eight (48) I/O ball/electrical interconnections 404 and 406 would be required. Since each additional device requires unique clock enable and chip select addressing interconnects, a two high stack would require that all chip-scale packages in that stack have fifty (50) interconnects 404 and 406. A four-high stack would require fifty-four (54) ball/electrical interconnections 404 and 406 and so forth.
In one implementation of the invention, the semiconductor devices (e.g., 102) may be random access memory devices mounted on stacked chip-scale packages (e.g., 602, 604, 606, 608, 610, and 612). The stacked packages (e.g., 602, 604, 606, 608, 610, and 612) are then mounted on either or both sides of a substrate to form a memory module 600, such as a single inline memory module (SIMM) or dual inline memory module (DTMM). The dimensional requirements of the memory module 600 may limit the number of packages (e.g., 100) that may be stacked.
In yet other implementations, the stacked packages may be mounted directly on a computer motherboard or other type of module.
According to one embodiment of the invention, identical chip-scale package substrates 701a-d are employed at each level of the stacked package 700 with the semiconductor dice 703a-d mounted in the same manner on each chip-scale substrate 701a-d. Using identical substrates 701a-d for every level of the stacked package 700 and mounting the dice 703a-d in an identical manner avoids the costs and difficulties of having to customize each level. Thus, a plurality of chip-scale ball grid array packages 701a-d may be manufactured and later assembled into a stack without regard as to any particular order.
The use of identical chip-scale packages at every level of a stack package 700 is made possible by a novel routing scheme that permits accessing each semiconductor die 703a-d independently and without customization of the substrates 701a-d. The novel routing scheme provides cascading connections through all levels of the stack package 700 to electrically couple each semiconductor die 703a-d to a primary access point (e.g., the solder balls on substrate 701a).
According to implementation of the novel routing scheme, each substrate 701a-d includes a plurality of solder balls 705 mounted on a first surface of the substrate 701a-d and a plurality of corresponding pads 707 on a second opposite surface of the substrate 701a-d. Interconnects 709 serve to electrically couple the solder balls 705 to the pads 707. A cascading scheme, as illustrated in
Note that the solder balls may be cascaded in different ways and utilizing different solder ball layouts without deviating from the invention. For example, a cascading routing scheme may be implemented using chip-scale packages similar to that illustrated in
In yet other implementations, only part of the solder balls are interconnected using a cascading scheme while part of the remaining solder balls are connected in a non-cascading manner across the stacked package. That is, some of the solder balls in the same position across all layers of a stack may be commonly connected.
Oftentimes, the size of a stacked memory or semiconductor package is limited by the space available on which to mount it in a particular implementation. Thus, one implementation of the invention employs tightly spaced components to maximize semiconductor or memory density of a stack package. For instance, in one implementation of the invention, the substrate (e.g., 104 in
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications are possible. Those skilled, in the art will appreciate that various adaptations and modifications of the just described preferred embodiment can be configured without departing from the scope and spirit of the invention. For example, while a semiconductor die has been used to illustrate the invention, any other electronic device or component may be used instead, with one or more aspects of the invention, without deviating from the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3746934||May 6, 1971||Jul 17, 1973||Siemens Ag||Stack arrangement of semiconductor chips|
|US4698267 *||Mar 13, 1986||Oct 6, 1987||E. I. Du Pont De Nemours And Company||High density para-aramid papers|
|US4773868||Mar 18, 1987||Sep 27, 1988||Chemie Und Filter Gmbh||Apparatus for use with stackable processor modules|
|US5130894||Nov 26, 1990||Jul 14, 1992||At&T Bell Laboratories||Three-dimensional circuit modules|
|US5172303||Nov 23, 1990||Dec 15, 1992||Motorola, Inc.||Electronic component assembly|
|US5222014||Mar 2, 1992||Jun 22, 1993||Motorola, Inc.||Three-dimensional multi-chip pad array carrier|
|US5334875||Mar 2, 1993||Aug 2, 1994||Hitachi, Ltd.||Stacked semiconductor memory device and semiconductor memory module containing the same|
|US5394303||Sep 9, 1993||Feb 28, 1995||Kabushiki Kaisha Toshiba||Semiconductor device|
|US5434745||Jul 26, 1994||Jul 18, 1995||White Microelectronics Div. Of Bowmar Instrument Corp.||Stacked silicon die carrier assembly|
|US5455385||Jun 28, 1993||Oct 3, 1995||Harris Corporation||Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses|
|US5502667||Sep 13, 1993||Mar 26, 1996||International Business Machines Corporation||Integrated multichip memory module structure|
|US5544017||Jul 19, 1994||Aug 6, 1996||Fujitsu Limited||Multichip module substrate|
|US5574630 *||May 11, 1995||Nov 12, 1996||International Business Machines Corporation||Laminated electronic package including a power/ground assembly|
|US5586010||Mar 13, 1995||Dec 17, 1996||Texas Instruments Incorporated||Low stress ball grid array package|
|US5666272||Jun 3, 1996||Sep 9, 1997||Sgs-Thomson Microelectronics, Inc.||Detachable module/ball grid array package|
|US5699234||Jan 28, 1997||Dec 16, 1997||General Electric Company||Stacking of three dimensional high density interconnect modules with metal edge contacts|
|US5701233||Jan 23, 1995||Dec 23, 1997||Irvine Sensors Corporation||Stackable modules and multimodular assemblies|
|US5702984||Nov 14, 1996||Dec 30, 1997||International Business Machines Corporation||Integrated mulitchip memory module, structure and fabrication|
|US5712768||Oct 26, 1995||Jan 27, 1998||Interconnect Systems, Inc.||Space-saving assemblies for connecting integrated circuits to circuit boards|
|US5715144||May 24, 1996||Feb 3, 1998||International Business Machines Corporation||Multi-layer, multi-chip pyramid and circuit board structure|
|US5721671||Oct 24, 1995||Feb 24, 1998||Gec Alsthom Transport Sa||Subrack for electronic circuit boards and its support|
|US5748452||Jul 23, 1996||May 5, 1998||International Business Machines Corporation||Multi-electronic device package|
|US5781415||Jul 9, 1996||Jul 14, 1998||Nec Corporation||Semiconductor package and mounting method|
|US5783870||Nov 14, 1995||Jul 21, 1998||National Semiconductor Corporation||Method for connecting packages of a stacked ball grid array structure|
|US5798567 *||Aug 21, 1997||Aug 25, 1998||Hewlett-Packard Company||Ball grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors|
|US5854507 *||Jul 21, 1998||Dec 29, 1998||Hewlett-Packard Company||Multiple chip assembly|
|US5857858||Dec 23, 1996||Jan 12, 1999||General Electric Company||Demountable and repairable low pitch interconnect for stacked multichip modules|
|US5883426 *||Apr 18, 1997||Mar 16, 1999||Nec Corporation||Stack module|
|US5898575||Sep 19, 1996||Apr 27, 1999||Lsi Logic Corporation||Support assembly for mounting an integrated circuit package on a surface|
|US5907903||Jan 8, 1998||Jun 1, 1999||International Business Machines Corporation||Multi-layer-multi-chip pyramid and circuit board structure and method of forming same|
|US5953210 *||Jul 8, 1997||Sep 14, 1999||Hughes Electronics Corporation||Reworkable circuit board assembly including a reworkable flip chip|
|US5963430||Feb 3, 1998||Oct 5, 1999||International Business Machines Corporation||Multi-electronic device package comprising at least two substrates and at least four layers of electrically conductive circuitry|
|US5973392 *||Mar 3, 1998||Oct 26, 1999||Nec Corporation||Stacked carrier three-dimensional memory module and semiconductor device using the same|
|US5977640 *||Jun 26, 1998||Nov 2, 1999||International Business Machines Corporation||Highly integrated chip-on-chip packaging|
|US5995379 *||Oct 23, 1998||Nov 30, 1999||Nec Corporation||Stacked module and substrate therefore|
|US6014316||Jun 10, 1998||Jan 11, 2000||Irvine Sensors Corporation||IC stack utilizing BGA contacts|
|US6025648 *||Apr 16, 1998||Feb 15, 2000||Nec Corporation||Shock resistant semiconductor device and method for producing same|
|US6049467||Aug 31, 1998||Apr 11, 2000||Unisys Corporation||Stackable high density RAM modules|
|US6093029||Sep 8, 1998||Jul 25, 2000||S3 Incorporated||Vertically stackable integrated circuit|
|US6125039||Mar 29, 1999||Sep 26, 2000||Taiyo Yuden Co., Ltd.||Hybrid module|
|US6133626||Sep 24, 1998||Oct 17, 2000||Gennum Corporation||Three dimensional packaging configuration for multi-chip module assembly|
|US6137164 *||Sep 22, 1999||Oct 24, 2000||Texas Instruments Incorporated||Thin stacked integrated circuit device|
|US6163462||Dec 8, 1997||Dec 19, 2000||Analog Devices, Inc.||Stress relief substrate for solder ball grid array mounted circuits and method of packaging|
|US6180881 *||May 5, 1998||Jan 30, 2001||Harlan Ruben Isaak||Chip stack and method of making same|
|US6188127 *||Feb 20, 1996||Feb 13, 2001||Nec Corporation||Semiconductor packing stack module and method of producing the same|
|US6195268||Feb 26, 1998||Feb 27, 2001||Floyd K. Eide||Stacking layers containing enclosed IC chips|
|US6222265||Dec 17, 1999||Apr 24, 2001||Micron Technology, Inc.||Method of constructing stacked packages|
|US6239496 *||Jan 18, 2000||May 29, 2001||Kabushiki Kaisha Toshiba||Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same|
|US6265772||Jun 15, 1999||Jul 24, 2001||Nec Corporation||Stacked semiconductor device|
|US6274929 *||Sep 1, 1998||Aug 14, 2001||Texas Instruments Incorporated||Stacked double sided integrated circuit package|
|US6297960 *||Jun 30, 1999||Oct 2, 2001||Micron Technology, Inc.||Heat sink with alignment and retaining features|
|US6303997 *||Apr 7, 1999||Oct 16, 2001||Anam Semiconductor, Inc.||Thin, stackable semiconductor packages|
|US6331939||Oct 12, 1999||Dec 18, 2001||Micron Technology, Inc.||Stackable ball grid array package|
|US6339254 *||Aug 31, 1999||Jan 15, 2002||Texas Instruments Incorporated||Stacked flip-chip integrated circuit assemblage|
|US6381141||Oct 15, 1998||Apr 30, 2002||Micron Technology, Inc.||Integrated device and method for routing a signal through the device|
|US6388333 *||Jun 27, 2000||May 14, 2002||Fujitsu Limited||Semiconductor device having protruding electrodes higher than a sealed portion|
|US6414391 *||Jun 30, 1999||Jul 2, 2002||Micron Technology, Inc.||Module assembly for stacked BGA packages with a common bus bar in the assembly|
|US6437990 *||Mar 20, 2000||Aug 20, 2002||Agere Systems Guardian Corp.||Multi-chip ball grid array IC packages|
|US6448506 *||Dec 28, 2000||Sep 10, 2002||Amkor Technology, Inc.||Semiconductor package and circuit board for making the package|
|US6451624 *||Aug 7, 2001||Sep 17, 2002||Micron Technology, Inc.||Stackable semiconductor package having conductive layer and insulating layers and method of fabrication|
|US6462421 *||Apr 10, 2000||Oct 8, 2002||Advanced Semicondcutor Engineering, Inc.||Multichip module|
|US6477058||Jun 28, 2001||Nov 5, 2002||Hewlett-Packard Company||Integrated circuit device package including multiple stacked components|
|US6504241 *||Oct 14, 1999||Jan 7, 2003||Sony Corporation||Stackable semiconductor device and method for manufacturing the same|
|US6507107 *||May 15, 2001||Jan 14, 2003||Micron Technology, Inc.||Semiconductor/printed circuit board assembly|
|US6521984 *||Apr 10, 2001||Feb 18, 2003||Mitsubishi Denki Kabushiki Kaisha||Semiconductor module with semiconductor devices attached to upper and lower surface of a semiconductor substrate|
|US6522022 *||Nov 27, 2001||Feb 18, 2003||Shinko Electric Industries Co., Ltd.||Mounting structure for semiconductor devices|
|US6525943 *||Aug 29, 2001||Feb 25, 2003||Micron Technology, Inc.||Heat sink with alignment and retaining features|
|US6525945||Aug 21, 2000||Feb 25, 2003||International Business Machines Corporation||Method and system for wide band decoupling of integrated circuits|
|US6529385||Aug 25, 1999||Mar 4, 2003||Intel Corporation||Component array adapter|
|US6531337 *||Jul 24, 2000||Mar 11, 2003||Micron Technology, Inc.||Method of manufacturing a semiconductor structure having stacked semiconductor devices|
|US6538332 *||Oct 9, 2001||Mar 25, 2003||Shinko Electric Industries, Co., Ltd.||Semiconductor device and method of production of same|
|US6542393||Apr 24, 2002||Apr 1, 2003||Ma Laboratories, Inc.||Dual-bank memory module with stacked DRAM chips having a concave-shaped re-route PCB in-between|
|US6545868||Oct 16, 2000||Apr 8, 2003||Legacy Electronics, Inc.||Electronic module having canopy-type carriers|
|US6549421||Aug 30, 2001||Apr 15, 2003||Micron Technology, Inc.||Stackable ball grid array package|
|US6583503||May 2, 2002||Jun 24, 2003||Micron Technology, Inc.||Semiconductor package with stacked substrates and multiple semiconductor dice|
|US6597062 *||Aug 5, 2002||Jul 22, 2003||High Connection Density, Inc.||Short channel, memory module with stacked printed circuit boards|
|US6617695 *||Nov 3, 2000||Sep 9, 2003||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device and semiconductor module using the same|
|US6703697 *||Dec 7, 2001||Mar 9, 2004||Intel Corporation||Electronic package design with improved power delivery performance|
|US6714418 *||Nov 1, 2002||Mar 30, 2004||Infineon Technologies Ag||Method for producing an electronic component having a plurality of chips that are stacked one above the other and contact-connected to one another|
|US6717812 *||Feb 19, 2003||Apr 6, 2004||Institute Of Microelectronics||Apparatus and method for fluid-based cooling of heat-generating devices|
|US6740981 *||Mar 26, 2001||May 25, 2004||Kabushiki Kaisha, Toshiba||Semiconductor device including memory unit and semiconductor module including memory units|
|US6781241 *||Oct 17, 2002||Aug 24, 2004||Fujitsu Limited||Semiconductor device and manufacturing method thereof|
|US6809421 *||Aug 20, 1999||Oct 26, 2004||Kabushiki Kaisha Toshiba||Multichip semiconductor device, chip therefor and method of formation thereof|
|US20010008482||Oct 15, 1998||Jul 19, 2001||David J. Corisis||Integrated device and method for routing a signal through the device|
|US20010028114||Mar 26, 2001||Oct 11, 2001||Kabushiki Kaisha Toshiba||Semiconductor device including memory unit and semiconductor module including memory units|
|US20010036063||Mar 2, 2001||Nov 1, 2001||Ibiden Co., Ltd.||Electronic part module mounted on|
|US20020075662||Feb 8, 2001||Jun 20, 2002||Abocom Systems, Inc.||Stack-type expansible electronic device|
|US20020176233||Feb 27, 2002||Nov 28, 2002||Stmicroelectronics Limited||Stackable module|
|US20030022464 *||Jul 24, 2002||Jan 30, 2003||Naohiko Hirano||Transfer-molded power device and method for manufacturing transfer-molded power device|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8199510 *||Jan 12, 2010||Jun 12, 2012||National Chip Implementation Center||Multi-layer SoC module structure|
|US8288852 *||Oct 9, 2009||Oct 16, 2012||Elpida Memory, Inc.||Semiconductor device|
|US8344492 *||Feb 9, 2010||Jan 1, 2013||Shinko Electric Industries Co., Ltd.||Semiconductor device and method of manufacturing the same, and electronic apparatus|
|US9159647 *||Jan 25, 2013||Oct 13, 2015||Novachips Canada Inc.||Method and apparatus for connecting memory dies to form a memory system|
|US20100090325 *||Oct 9, 2009||Apr 15, 2010||Elpida Memory, Inc.||Semiconductor device|
|US20100200975 *||Feb 9, 2010||Aug 12, 2010||Shinko Electric Industries Co., Ltd.||Semiconductor device and method of manufacturing the same, and electronic apparatus|
|US20110096506 *||Apr 28, 2011||National Chip Implementation Center National Applied Research Laboratories||Multi-layer soc module structure|
|US20130193582 *||Jan 25, 2013||Aug 1, 2013||Mosaid Technologies Incorporated||Method and apparatus for connecting memory dies to form a memory system|
|U.S. Classification||257/686, 438/109, 257/777, 257/685, 257/778, 438/108, 361/760|
|International Classification||H01L23/02, H01L23/498, H01L25/065|
|Cooperative Classification||H01L2224/16225, H01L2225/1023, H01L2225/1058, H01L2225/0652, H01L2924/15192, H01L2225/06572, H01L24/16, H01L2924/19105, H01L2924/19106, H01L2924/19043, H01L2924/15331, H01L23/49816, H01L23/49838, H01L2924/10253, H01L23/50, H01L2924/3511, H01L2924/15311, H01L2225/06541, H01L2225/06517, H01L2924/19041, H01L2924/1532, H01L25/105, H01L2924/01079|
|European Classification||H01L23/498C4, H01L25/10J|
|Jun 5, 2014||AS||Assignment|
Owner name: US BANK NATIONAL ASSOCIATION, AS NOTES COLLATERAL
Effective date: 20140604
Free format text: SECURITY INTEREST;ASSIGNORS:SANMINA CORPORATION, AS GRANTOR;SANMINA CORPORATION, F/K/A SANMINA-SCI CORPORATION, AS GRANTOR;HADCO SANTA CLARA, INC., AS GRANTOR;AND OTHERS;REEL/FRAME:033094/0826
|Jul 23, 2014||FPAY||Fee payment|
Year of fee payment: 8