US RE42387 E1 Abstract The invention concerns a method for compensating the non-linearity of a sigma-delta analog-to-digital converter (A
2) with quantization at N levels comprising a digital-to-analog converter (24). The method comprises a calibrating step which consists in transforming the multibit sigma-delta analog-to-digital converter (A2) into a sigma-delta analog-to-digital converter with quantization at three levels, then at two levels. The correction values of each level to be corrected are accurately measured. The method also comprises a normal functioning phase which consists, when the sigma-delta an analog-to-digital converter (A2) is operating with quantization at N levels, in producing an instantaneous correction of errors of the analog-to-digital converter (24) using said correction values.Claims(35) 1. A method of compensating the non-linearity of a sigma-delta analog-to-digital converter with a quantizer having N quantizing levels, and including a digital-to-analog converter in a feedback loop, comprising:
a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values C
_{i}, where i is a positive integer from 1 to N−2; anda calibration phase in which the correction values C
_{i }are calculated from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels;wherein during the calibration phase the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels X
_{m}, X_{M}, and X_{i}, where i is from 1 to N−2;wherein, during a period P
1 _{i }of the calibration phase, a predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the values from the output of the quantizer of the sigma-delta analog-to-digital converter are processed digitally;wherein the calibration phase is executed N−2 times, retaining the levels X
_{m }and X_{M}, and taking successively for the level X_{i}, the N−2 levels other than the levels X_{m }and X_{M}; andwherein the correction values C
_{i }of the N−2 levels other than X_{m }and X_{M }are calculated using a sum of the processed values, the N−2 correction values C_{i }being adapted to modify the N−2 levels other than X_{m }and X_{M }during the normal operation phase.2. The method of
_{i}, at least one step F during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with two quantizing levels X_{m }and X_{M}, during a period P2, wherein the predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the successive values of the output of the sigma-delta analog-to-digital converter are processed digitally.3. The method of
4. The method of
_{i }is added to each level X_{i }present at the output of the quantizer.5. The method of
2 _{i }equal to each period P1 _{i}, and a sum S2 _{i }is calculated of all the values leaving the sigma-delta analog-to-digital converter during each execution, after which a correction value C_{i }corresponding to the value X_{i }is calculated from the equation: C_{i}=(S2 _{i}−S1 _{i})/N_{i}.6. The method of
1 _{i}, for each level X_{i}, is equal to the period needed to count the number N_{i }of values equal to X_{i }at the output of the sigma-delta analog-to-digital converter until the number N_{i }is equal to a given number N_{0}.7. The method of
_{i }for each level X_{i}, the number N_{i }of values equal to X_{i }and the total number NT_{i }of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S1 _{i }of the NT_{i }values is calculated.8. The method of
1 _{i}, for each level X_{i}, is equal to the period needed to count the number N_{i }of values equal to X_{i }at the output of the sigma-delta analog-to-digital converter until the number N_{i }is equal to a given number N_{0}.9. The method of
_{m }and X_{M }are respectively the minimum value and the maximum value of the N quantizing levels.10. The method of
_{m }and X_{M }are respectively the minimum value and the maximum value of the N quantizing levels.11. The method of
_{i }is added to each level X_{i }present at the output of the quantizer.12. The method of
1 _{i }for each level X_{i}, the number N_{i }of values equal to X_{i }and the total number NT_{i }of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S1 _{i }of the NT_{i }values is calculated.13. The method of
_{m }and X_{M }are respectively the minimum value and the maximum value of the N quantizing levels.14. The method of
_{i }is added to each level X_{i }present at the output of the quantizer.15. The method of
1 _{i }for each level X_{i}, the number N_{i }of values equal to X_{i }and the total number NT_{i }of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S1 _{i }of the NT_{i }values is calculated.16. A system for compensating the non-linearity of a sigma-delta analog-to-digital converter having a quantizer with N quantizing levels, comprising:
a digital-to-analog converter in a feedback loop and a digital filter, wherein the digital-to-analog converter comprises means for calculating correction values C
_{i}, where i is a positive integer from 1 to N−2, during a calibration phase, and from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and by converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels, and means for modifying a plurality of digital values corresponding to a plurality of quantizing levels by applying the correction values C_{i }during a normal operation phase;wherein the calculating and modifying means comprise:
counter means for counting the values leaving the quantizer of the sigma-delta analog-to-digital converter;
at least one accumulator for summing the values leaving the quantizer of the sigma-delta analog-to-digital converter;
storage means for memorizing numbers delivered by the counter means and the accumulator;
processor means for performing calculations on the memorized numbers and generating control signals in the system for controlling the various phases;
a correction module between the quantizer and the digital filter, communicating with the processor means; and
comparators and a digital processor module internal to the N-level quantizer and capable of converting the quantizer into a quantizer with fewer than N quantizing levels.
17. A method of compensating the non-linearity of a sigma-delta analog-to-digital converter with a quantizer having N quantizing levels and including a digital-to-analog converter in a feedback loop, comprising:
a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values C
_{i}, where i is a positive integer from 1 to N−2; anda calibration phase in which the correction values C
_{i }are calculated from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels;wherein during the calibration phase the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels X
_{m}, X_{M}, and X_{i}, where i is from 1 to N−2;wherein, during a period P
1 _{i }of the calibration phase, a predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the values from the output of the quantizer of the sigma-delta analog-to-digital converter are processed digitally;wherein the calibration phase is executed N−2 times, retaining the levels X
_{m }and X_{M}, and taking successively for the level X_{i}, the N−2 levels other than the levels X_{m }and X_{M}; andwherein the correction values C
_{i }of the N−2 levels other than X_{m }and X_{M }are calculated using the processed values, the N−2 correction values C_{i }being adapted to modify the N−2 levels other than X_{m }and X_{M }during the normal operation phase.18. The method of
_{i}, at least one step F during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with two quantizing levels X_{m }and X_{M}, during a period P2, wherein the predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the successive values of the output of the sigma-delta analog-to-digital converter are processed digitally.19. A method of compensating the non-linearity of a sigma-delta analog-to-digital converter, the method comprising:
during a normal operation phase:
operating a quantizer with N quantizing levels;
generating a digital output value for each of the N quantizing levels, wherein the N quantizing levels include a minimum quantizing level X
_{m}, a maximum quantizing level X_{M}, and N−2 remaining quantizing levels X_{i}, where i is from 1 to N−2; andmodifying each of the digital output values that correspond to the N−2 remaining quantizing levels using a respective one of N−2 correction values generated during a first portion of a calibration phase that is executed N−2 times;
during the first portion of the calibration phase:
digitally processing the digital output values with a digital-to-analog converter retained in a feedback loop of the sigma-delta analog-to-digital converter;
calculating each respective N−2 correction value using a first sum of the digitally processed digital output values;
operating the quantizer with three quantizing levels comprising X
_{m}, X_{M}, and one of the remaining quantizing levels X_{i};providing a predetermined input value to the sigma-delta analog-to-digital converter;
retaining the levels X
_{m }and X_{M}, and taking successively for the level X_{i}, the N−2 levels other than the levels X_{m }and X_{M}; andcalculating the correction values of the N−2 levels other than X
_{m }and X_{M }using a sum of the processed values.20. The method of claim 19, further comprising during a second portion of the calibration phase, operating the quantizer with two quantizing levels: X
_{m }and X_{M}.21. The method of claim 20, wherein the quantizer is operated with a number of quantizing levels less than N by modifying internal quantizing threshold values and by performing said digital processing using comparator circuits internal to the quantizer.
22. The method of claim 20, further comprising executing the calibration phase N−2 times, wherein a time to execute the second portion of the calibration phase is substantially equal to a time to execute the first portion of the calibration phase, and wherein during the second portion, a second sum (S2
_{i}) is calculated from all of the digital output values during each execution, wherein each correction value (C_{i}) corresponding to each remaining quantizing level X_{i }is calculated by C_{i}=(S2_{i}−S1_{i})/N_{i}, where N_{i }comprises a number of occurrences in which the digital output values are equal to X_{i}.23. The method of claim 22, wherein the time to execute the second portion of the calibration phase is substantially equal to the period used to count the number N
_{i }until the number N_{i }is equal to the number N_{0}.24. The method of claim 19, wherein during the normal operation phase, said modifying includes adding the respective correction value to each digital output value corresponding to each remaining quantizing level X
_{i}.25. The method of claim 19, wherein the predetermined input value is equal to zero, and wherein during the first portion of the calibration phase, for each remaining quantizing level X
_{i}, the number N_{i }of values equal to X_{i }and the total number NT_{i }of all the digital output values are counted and a first sum S1_{i }of the NT_{i }values is calculated.26. The method of claim 19, wherein during each of the N−2 executions of the first portion of the calibration phase, each of the respective correction values for the N−2 remaining quantizing levels is calculated using a first sum (S1
_{i}) of a number N_{0 }of the digital output values, where N_{0 }comprises a number of occurrences in a given period of time in which the digital output values are equal to X_{i}.27. A system for compensating the non-linearity of a sigma-delta analog-to-digital converter, the system comprising:
a quantizer configured to operate in a normal operation phase and a first portion of a calibration phase, wherein the quantizer is configured to operate during the normal operation phase with a plurality of quantizing levels (N) including a minimum quantizing level X _{m}, a maximum quantizing level X_{M}, and N−2 remaining quantizing levels X_{i}, where i is from 1 to N−2, wherein the quantizer is configured to output a plurality of digital output values, each digital output value corresponding to one of the plurality of quantizing levels, and wherein the quantizer is further configured to operate with three quantizing levels comprising X_{m}, X_{M}, and one of the remaining quantizing levels X_{i }during the first portion of the calibration phase that is executed N−2 times;a digital-to-analog converter coupled in a feedback loop to the quantizer during the first portion of the calibration phase, wherein the digital-to-analog converter is configured to digitally process the plurality of digital output values, wherein during the first portion of the calibration phase, the plurality of digital output values of the quantizer are based on a predetermined input value; a control device coupled to the quantizer and configured, during the first portion of the calibration phase, to retain the levels X _{m }and X_{M }and take successively for the level X_{i }the N−2 levels other than the levels X_{m }and X_{M}, and to calculate a respective correction value from the plurality of digital output values for each of the digital output values that corresponds to the N−2 remaining quantizing levels; anda corrector module coupled to the quantizer, wherein the corrector module is configured, during the normal operation phase, to modify each of the digital output values that corresponds to the N−2 remaining quantizing levels using a respective one of the N−2 correction values. 28. The system of claim 27, wherein the control device comprises:
a counter circuit configured to count ones of the plurality of output digital values of the quantizer; an accumulator configured to sum the plurality of output digital values of the quantizer; storage device coupled to the counter circuit and to the accumulator, wherein the storage device is configured to store values provided by the counter circuit and the accumulator; and a processor module coupled to the storage device and configured to perform calculations on the values stored within the storage device and to generate control signals for controlling the quantizer. 29. The system of claim 28, wherein the quantizer includes a comparator circuit coupled to a processor module, wherein the quantizer is configured to operate with fewer than N quantizing levels depending upon the control signals.
30. The system of claim 27, wherein during each of the N−2 executions of the first portion of the calibration phase, the control device is further configured to calculate each of the respective correction values for the N−2 remaining quantizing levels using a first sum (S1
_{i}) of a number N_{0 }of the digital output values, where N_{0 }comprises a number of occurrences in a given period of time in which the digital output values are equal to X_{i}.31. The method of claim 30, wherein the quantizer is further configured to operate with two quantizing levels: X
_{m }and X_{M }during a second portion of the calibration phase.32. A system for compensating the non-linearity of a sigma-delta analog-to-digital converter, the system comprising:
a quantizer configured to operate in a normal operation phase and a first portion of a calibration phase, wherein the quantizer is configured to operate during the normal operation phase with a plurality of quantizing levels (N) and to generate a digital output value for each of the N quantizing levels, wherein the N quantizing levels include a minimum quantizing level X _{m}, a maximum quantizing level X_{M}, and N−2 remaining quantizing levels X_{i}, where i is from 1 to N−2, and wherein the quantizer is further configured to operate with three quantizing levels comprising X_{m}, X_{M}, and one of the remaining quantizing levels X_{i }during the first portion of the calibration phase that is executed N−2 times;a digital-to-analog converter coupled in a feedback loop to the quantizer during the first portion of the calibration phase; means for retaining the levels X _{m }and X_{M }and for taking successively for the level X_{i }the N−2 levels;means for calculating, during the first portion of the calibration phase, a respective correction value from the plurality of digital output values for each of the digital output values that corresponds to the N−2 remaining quantizing levels, wherein the digital output values are processed digitally by the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter; wherein the means for calculating comprises:
counter means for counting specific ones of the digital output values of the quantizer;
at least one accumulator for summing the digital output values of the quantizer;
storage means for storing numbers delivered by the counting means and the at least one accumulator; and
processor means for performing calculations on the stored numbers and generating control signals for controlling the quantizer; and
means for modifying, during the normal operation phase, each of the digital output values that correspond to the N−2 remaining quantizing levels using a respective one of the N−2 correction values;
wherein the means for modifying comprises:
a correction module coupled between the quantizer and a digital filter, wherein the correction module communicates with the processor means; and
within the quantizer, a comparator circuit and a digital processor module are configured to operate the quantizer with fewer than N quantizing levels.
33. The system of claim 32, wherein during each of the N−2 executions of the first portion of the calibration phase, the means for calculating is further configured to calculate each of the respective correction values for the N−2 remaining quantizing levels using a first sum (S1
_{i}) of a number N_{0 }of the digital output values, where N_{0 }comprises a number of occurrences in a given period of time in which the digital output values are equal to X_{i}.34. The method of claim 33, wherein during a second portion of the calibration phase, the quantizer is further configured to operate with two quantizing levels: X
_{m }and X_{M}.35. The method of claim 32, wherein the digital output values are based on a predetermined value provided to an input of the sigma-delta analog-to-digital converter.
Description More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,653,958. The present application, U.S. patent application Ser. No. 11/487,666, is a continuation of U.S. patent application Ser. No. 11/287,568, filed Nov. 23, 2005, now abandoned. 1. Field of the Invention The present invention concerns a method and a system for compensating the non-linearity of a sigma-delta analog-to-digital converter. 2. Description of the Related Art Equipment in all fields, electronic or otherwise, consumer or professional, increasingly employs digital rather than analog processing. This choice is often justified by technical advantages that are now well known, such as very stable parameters, excellent reproducibility of results, and increased functionality. The external world being inherently analog, in most cases analog-to-digital converters (ADC) and digital-to-analog converters (DAC) provide at some level the interface between the external world and the digital core of the equipment. The development of powerful digital processors has created a need for a high-resolution analog-to-digital converter compatible with CMOS VLSI (Very Large Scale Integration) technologies. The sigma-delta modulation converter in particular has exploited technological developments. As shown in The fundamental principle of the sigma-delta analog-to-digital converter consists firstly of oversampling the signal using the analog sample-and-hold device, pushing the quantizing noise power maximum outside the pass-band of the signal, by integrating the quantizer into a feedback loop, and then filtering the signal obtained by means of a digital filter Using a multibit quantizer associated with a multibit digital-to-analog converter in the feedback loop of a sigma-delta analog-to-digital converter is beneficial because it improves the signal/noise ratio and dynamic range of the sigma-delta analog-to-digital converter. However, the performance of the sigma-delta analog-to-digital converter is highly dependent on the linearity of the sigma-delta analog-to-digital converter One prior art solution that has been proposed for calibrating the multibit digital-to-analog converter regardless of the number of levels is described by SARHANG-NEJAD and G. C. TEMES, “A High Resolution Multibit Sigma Delta ADC with Digital Correction and Relaxed Amplifier Requirements”, IEEE Journal of solid state circuits, vol. 28, N 6, June 1993, pages 648-660. It proposes to improve the performance of the sigma-delta analog-to-digital converter by measuring the non-linearities of the digital-to-analog converter Each correction value represents a digital error caused by the digital-to-analog converter The above technique has a number of drawbacks, associated with the manner in which the correction values are measured. In the calibration phase ( During the calibration phase, the digital-to-analog converter is therefore connected to the input E The invention aims to solve the above problem by retaining the structure of the sigma-delta analog-to-digital converter during the calibration phase and using only digital signals. The invention proposes a method of compensating the non-linearity of a sigma-delta analog-to-digital converter with N quantizing levels and including a digital-to-analog converter in a feedback loop. N is an integer greater than two. The method includes a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values Ci, where i is a positive integer from 1 to N−2, calculated during a calibration phase. According to a general feature of the invention, the correction values Ci are calculated from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels, for example modifiable levels. The number N is a positive integer greater than 2. The correction values C The method in accordance with the invention of compensating non-linearity includes a calibration phase during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels X The levels X The method can further include, during the calibration phase and before calculating the correction values Ci, at least one step F during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with two quantizing levels X For example, if step F is performed only once, the periods P The calibration phase presupposes that X In accordance with the invention the sigma-delta analog-to-digital converter with N quantizing levels is converted into a sigma-delta analog-to-digital converter with a number of quantizing levels less than N by modifying quantizing threshold values and by digital processing using internal comparators. In the general case the sigma-delta analog-to-digital converter with N quantizing levels is converted into a sigma-delta analog-to-digital converter with three quantizing levels, and if the optional step F (offset voltage correction) is implemented, it is also converted into a sigma-delta analog-to-digital converter with two quantizing levels. According to one advantageous feature of the invention, the levels X In one embodiment of the invention, during the normal operation phase, its correction value C In one advantageous variant of the invention, said predetermined value is equal to zero and, during the calibration phase, and during the period P
The period P If step F is executed only once (in which case all the periods P
There are various ways to calculate the correction values Ci. The invention also proposes a system for compensating the non-linearity of a sigma-delta analog-to-digital converter with N quantizing levels including a digital-to-analog converter and a digital filter. According to a general feature of the invention, the system includes means for implementing the various phases previously described. In a preferred embodiment, the calculating and modifying means include: -
- counter means for counting the values leaving the sigma-delta analog-to-digital converter,
- at least one accumulator for summing the values leaving the sigma-delta analog-to-digital converter,
- storage means for memorizing numbers delivered by the counting means and the accumulator,
- processor means for performing calculations on the memorized numbers and generating control signals in the system for controlling the various phases,
- a correction module between the quantizer and the digital filter and communicating with the processor means, and
- comparators and a digital processor module internal to the N-level quantizer and capable of converting the quantizer into a quantizer with fewer than N quantizing levels.
Other advantages and features of the invention will become apparent on examining the detailed description of one non-limiting embodiment and the accompanying drawings in which: Although the invention is not limited to it, one example of the method and the system according to the invention for compensating the non-linearity of a sigma-delta analog-to-digital converter with three quantizing levels will now be described. The The first part A In the second part A The third part A In normal operation, the digital-to-analog converter The three analog points do not usually correspond ideally to the values −1, 0 and 1. For example, the analog point leaving the digital-to-analog converter whose ideal value is 0 can be corrected. The correction of the 0 point is independent of the zero value at the input During the first calibration phase the switch The accumulator The second calibration phase consists of converting the sigma-delta analog-to-digital converter with three quantizing levels into a sigma-delta analog-to-digital converter with two quantizing levels. For this it suffices to convert the three-level quantizer The division is simple to effect in the digital processor module Once these two calibration phases have been completed, the phase of normal operation of the sigma-delta analog-to-digital converter with three quantizing levels begins. The switch
Thus if the digital value 0 is present at the output of the quantizer
To convert the three-level quantizer
In fact, only the comparator The non-linearity of the sigma-delta analog-to-digital converter described above can be compensated by carrying out a calibration phase without modifying the structure of the sigma-delta analog-to-digital converter. For example, in a simulation for a signal to be converted of maximum amplitude and no correction in accordance with the invention, a sigma-delta analog-to-digital converter with three quantizing levels sampled at a frequency of 2 048 kHz had a signal/noise ratio of 46 dB. The results obtained after applying the first calibration phase with N Executing the second calibration phase yielded a sum S A signal/noise ratio of 105 dB was then obtained in normal operation for a signal to be converted of maximum amplitude and with correction in accordance with the invention. The method described above performs a calibration phase using a three-level quantizer and then a two-level quantizer but retains the general structure of the sigma-delta analog-to-digital converter. The calibration phase is effected simply by controlling the various switches. Patent Citations
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