|Publication number||USRE42403 E1|
|Application number||US 12/139,020|
|Publication date||May 31, 2011|
|Priority date||Jun 16, 2004|
|Also published as||US7061057, US20050280101|
|Publication number||12139020, 139020, US RE42403 E1, US RE42403E1, US-E1-RE42403, USRE42403 E1, USRE42403E1|
|Inventors||Jeff Babcock, Johan Agus Darmawan, John Mason|
|Original Assignee||Rovec Acquisitions Ltd., LLC|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Referenced by (2), Classifications (22), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is related to co-pending applications Ser. No. 10/870,753, filed Jun. 16, 2004, entitled LDMOS TRANSISTOR WITH IMPROVED GATE SHIELD, Ser. No. 10/870,012, filed Jun. 16, 2004, entitled LDMOS TRANSISTOR HAVING GATE SHIELD AND TRENCH SOURCE CAPACITOR, and Ser. No. 10/870,795, filed Jun. 16, 2004, entitled LATERALLY DIFFUSED MOS TRANSISTOR HAVING INTEGRAL SOURCE CAPACITOR AND GATE SHIELD, all of which are incorporated herein by reference for all purposes.
This invention relates generally to semiconductor transistors, and more particularly the invention relates to laterally diffused MOS (LDMOS) transistors.
The LDMOS transistor is used in RF/microwave power amplifiers. The device is typically fabricated in an epitaxial silicon layer (P−) on a more highly doped silicon substrate (P+). A grounded source configuration is achieved by a deep P+ sinker diffusion from the source region to the P+ substrate, which is grounded. (See, for example, U.S. Pat. No. 5,869,875.)
The source resistance of the LDMOS transistor is determined in part by the mobility of positive carriers, or holes, in the P+ substrate. The source resistance is also sensitive to the drain-source voltage (Vds) and its effects. Further, a gold backside contact to the P+ substrate can require expensive preform compounds during packaging to maintain low source resistance.
The present invention is directed to reducing or eliminating these characteristics with conventional LDMOS transistors.
In accordance with the present invention, a LDMOS transistor is fabricated on an N-doped substrate having a P-doped epitaxial layer grown on the substrate with a buried P-doped layer in the epitaxial layer. The transistor is fabricated in the P-doped epitaxial layer.
A source contact is provided through the epitaxial layer and buried layer to the N-doped substrate. The contact also ohmically engages a P-doped channel region and a P+ sinker, if present. Thus, the electrical carriers are now electrons in the N-doped substrate rather than holes in a P-doped substrate. Since electrons have higher mobility in a semiconductor than do holes, the source resistance is reduced. Further, a gold backside contact to the N-doped substrate is readily made without the need for preform compounds. Additionally, the drain extension region (the epitaxial layer and P buried layer) allows electrical junction isolation of the drain from the body and source contact.
The invention and objects and features thereof will be more readily apparent when the following detailed description and appended claims when taken with the drawings.
Source contact 26 ohmically contacts N-doped source region 14 and an extension of P− doped channel region 20 and ohmically contacts P+ substrate 10 through a P+ doped sinker 32 which extends through P-doped epitaxial layer 12 to P+ substrate 10. A source contact can be provided for the transistor on the backside of substrate 10. P+ sinker 32 is not needed in a low power application but helps prevent a depletion region from the drain the sinker can be formed by out diffusion from the trench contact.
It is desirable to have the source resistance as low as possible. As noted above, source resistance of the LDMOS transistor is determined in part by the mobility of positive carriers, or holes, in P+ substrate 10. The source resistance is also sensitive to the drain-source voltage (Vds) and its effects. Further, a metal such as a gold backside contact to P+ substrate 10 can require expensive preform compounds during packaging to maintain low source resistance.
Fabrication of the N+ source trench contact to the underlying N+ substrate is readily implemented using conventional semiconductor processing.
Photoresist mask 70 is removed as shown if
The use of an N+ substrate in the LDMOS structure provides advantages in reducing source contact resistance as described above. While the invention has been described with reference to a specific embodiment, the description is illustrative of the invention, and is not to be construed to be as limiting of the invention. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
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|U.S. Classification||257/401, 257/344, 257/408, 257/330, 257/329, 257/328, 257/342|
|International Classification||H01L29/76, H01L29/40, H01L29/78, H01L21/336, H01L29/10, H01L29/417|
|Cooperative Classification||H01L29/41766, H01L29/1045, H01L29/66659, H01L29/1087, H01L29/402, H01L29/4175, H01L29/7835|
|European Classification||H01L29/78F3, H01L29/66M6T6F11H|
|Jul 23, 2008||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CREE MICROWAVE, LLC;REEL/FRAME:021282/0420
Effective date: 20080501
Owner name: ROVEC ACQUISITIONS LTD. L.L.C., DELAWARE
Owner name: CREE MICROWAVE, LLC, NORTH CAROLINA
Free format text: CORPORATE CONVERSION UNDER NORTH CAROLINA LAW;ASSIGNOR:CREE MICROWAVE, INC.;REEL/FRAME:021288/0247
Effective date: 20050623
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BABCOCK, JEFF;DARMAWAN, JOHAN AGNUS;MASON, JOHN;SIGNING DATES FROM 20040525 TO 20040528;REEL/FRAME:021282/0415
Owner name: CREE MICROWAVE, INC., CALIFORNIA
|Jul 10, 2012||CC||Certificate of correction|
|Jan 24, 2014||REMI||Maintenance fee reminder mailed|
|Jun 13, 2014||LAPS||Lapse for failure to pay maintenance fees|