|Publication number||USRE42615 E1|
|Application number||US 12/624,053|
|Publication date||Aug 16, 2011|
|Filing date||Nov 23, 2009|
|Priority date||Feb 24, 1997|
|Also published as||EP0865019A2, EP0865019A3, US5796392, US6320574, USRE40859, USRE41192, USRE43573|
|Publication number||12624053, 624053, US RE42615 E1, US RE42615E1, US-E1-RE42615, USRE42615 E1, USRE42615E1|
|Inventors||Alexander J. Eglit|
|Original Assignee||Genesis Microchip (Delaware) Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (100), Non-Patent Citations (20), Classifications (21), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,320,574. The reissue applications are application Ser. Nos. 10/720,001, 11/408,528, and 11/408,669, the latter two of which are divisional reissues of Ser. No. 09/082,070, filed May 20, 1998, now U.S. Pat. No. 6,320,574, and the present application Ser. No. 12/624,053 is a Continuation of Divisional Reissue No. 11/408,669 filed Apr. 21, 2006 now U.S. Pat. No. R,E41,192.
The present application is related to co-pending U.S. Patent Application entitled, “A Method and Apparatus for Upscaling an Image”, Filed Concurrently with the present application, Serial Number UNASSIGNED, Attorney Docket Number: PRDN-0001, and is incorporated in its entirety herewith.
The present application is also related to and is a continuation of application Ser. No. 08/803,824 filed Feb. 24, 1997, now U.S. Pat. No. 5,796,392, entitled, “Method and Apparatus for Clock Recovery in a Digital Display Unit.”
1. Field of the Invention
The present invention relates to graphics system, and more specifically to a method and apparatus for recovering a clock signal associated with an analog display data received in a digital display unit (e.g., flat-panel monitor) of a graphics system.
2. Related Art
Digital display units are often used to display images. A flat-panel monitor generally used in lap-top computers is an example of such a digital display unit. A flat-panel monitor typically receives a source image from a graphics controller circuit and displays the source image. Flat-monitors which are being increasingly deployed with desk-top computers is another example of such a digital display unit. The source image is usually received in the form of analog data such as RGB signals well-known in the art.
Digital display devices often need to convert the received analog data into a sequence of pixel data. The need for such a conversion can be appreciated by understanding the general layout of a typical digital display device, which is explained below.
Digital display devices generally include a display screen including a number of horizontal lines.
The number of horizontal and vertical lines defines the resolution of the corresponding digital display device. Resolutions of typical screens available in the market place include 640×480, 1024×768 etc. At least for the desk-top and lap-top applications, there is a demand for increasingly bigger size display screens. Accordingly, the number of horizontal display lines and the number of pixels within each horizontal line has also been generally increasing.
Thus, to display a source image, the source image is divided into a number of points and each point is displayed on a pixel. Each point may be represented as a pixel data element. Display signals for each pixel in display 100 may be generated using the corresponding display data element. However, as noted earlier, the source image may be received in the form of an analog signal. Thus, the analog data needs to be converted into pixel data for display on a digital display screen.
It is helpful to understand the typical format of the analog data to appreciate the usual conversion process. Generally, each source image is transmitted as a sequence of frames, with each frame including a number of horizontal scan lines. Image is generated on display screen 100 by displaying these successive frames.
Usually, a time reference signal is provided in parallel to divide the analog signal into horizontal scan lines and frames. In the VGA/SVGA environments known in the art, the reference signals include VSYNC and HSYNC. The VSYNC signal indicates the beginning of a frame and the HSYNC signal indicates the beginning of a next source scan line. The relationship between HSYNC and the analog signal data is illustrated further with reference to
Signal 150 of
Such transitions are typically indicated by another signal (e.g., HSYNC signal in computer displays). Pulses 103B, 104B, and 105B represent such transitions. Thus, after a transition, the display portion of the signal may be sampled a number of times. The exact number may be proportional to the number of pixels on each horizontal line on display screen 100. Each display portion is generally sampled the same number of times to generate samples for each pixel.
Thus, to convert the source image received in analog signal form to pixel data suitable for display on a digital display device, each horizontal scan line is converted to a number of pixel data. For such a conversion, each horizontal scan line of analog data is sampled a predetermined number of times. The sampled value is represented as a number, which constitutes a pixel data element.
Each horizontal scan line is typically sampled using a sampling clock signal. That is, the horizontal scan line is usually sampled during each cycle of the sampling clock. Accordingly, the sampling clock is designed to have a frequency such that the display portion of each horizontal scan line is sampled a desired number of times. The desired number can correspond to the number of pixels on each horizontal display line of the display screen. However, the desired number can be different that the number of pixels on each horizontal display line.
Using the sampling scheme described above, each horizontal scan line of a source frame is represented as a number of pixel data. It will be readily appreciated that the relative position of source image points needs to be properly maintained when displaying the source image. Otherwise, some of the lines will appear skewed in relation to the other on the display screen.
To maintain a proper relative position of the source image pixels, the sampling clock may need to be synchronized with the reference signal. That is, assuming for purposes of explanation that HSYNC signal is used as a time reference, the beginning of sampling of analog data for a horizontal display line may need to be synchronized with HSYNC signal pulse. Once such a synchronization is achieved, the following pixels in the same horizontal lines may also be properly aligned with corresponding pixels in other lines.
Phase-locked loop (PLL) circuits implemented using analog components have conventionally been used to achieve such a synchronization.
Phase detector 210 provides on line 212 a signal having a difference of the frequencies of f1 and f2. The signal on line 212 may also include several harmonics of the difference frequency. Filter 220 is generally designed as a low pass filter to eliminate undesirable components. When the frequencies f1 and f2 are close, but not equal, line 223 will carry a signal with the difference frequency. VCO 240 is designed to generate a signal with a predetermined frequency. However, the frequency is altered depending on the voltage level received on line 234.
Amplifier 230 amplifies the signal on line 223 to provide a desired level of voltage on line 234 to modify the frequency of VCO 240. The voltage level is generated so as to achieve a synchronization of the frequencies f1 and f2. Frequency divider 250 divides the frequency of clock signal received on line 245 by a factor of n. By choosing an appropriate value of n, analog signal data for each horizontal source scan line can be sampled a desired number of times. The signal on line 245 can be used for such a sampling.
However, it is well known in the art, the reference frequency (HSYNC) can vary by a slight value from an average frequency during normal operating conditions. In addition, the reference frequency can drift over a prolonged period of time due to, for example, temperature changes in the circuits generating the analog source image data. Further, jitter may be present in both the reference signal and the clock signal generated by the analog PLL.
In general, it is desirable that the PLL of
Some prior approaches have placed the capacitor external to the integrated circuit, with the capacitor being coupled to the integrated circuit by pads. One problem with this approach is that noise is introduced into the analog PLL loop due to the external couplings. Analog PLLs are generally sensitive to such noises, leading to instability in the PLL loop. Without a low bandwidth in the loop, PLL 200 may be unable to track deviations in the reference signal closely, which may be unacceptable in some situations as explained below.
Deviations of about 5 to 20 nano-seconds in time reference period can be common in a typical graphics environment. These deviations are usually more problematic for larger size display screens. To illustrate this point with an example, a 640×480 size display screen has a pixel processing period (i.e., average time to display each pixel) of 40 nano-seconds, while a large 1280×1080 size monitor can have a pixel processing period of about 8-9 nano-seconds. A deviation of 20 nano-seconds may not have a perceptible impact on the display of a 640×480 screen due to the relatively larger pixel processing period, whereas the same amount of deviation can cause the display on the large monitor to be skewed by two pixels.
Such a skew between lines is generally perceptible for the human eye and the resulting display quality may be unacceptable. The display quality is further exacerbated if the number of such skews is larger. As is well known in the art, the display quality problems can be ameliorated by a circuit which can track the time reference signal more closely. Therefore, what is needed is a circuit which tracks the time reference signal closely.
The present invention is directed to a clock recovery circuit implemented in a digital display unit. The digital display unit receives an analog signal data and an associated time reference signal. Together, they represent an image to be displayed on a digital display screen usually provided in the digital display unit.
The clock recovery circuit provides a sampling clock based on the time reference signal. The sampling clock is used to sample the analog signal data, and the resulting pixel data is used to generate display signals on the display screen.
The clock recovery circuit includes a digital phase-locked loop (PLL). The bandwidth of the PLL can be instantaneously changed because of the digital implementation. In addition, the long term frequency and the temporary phase fluctuations are tracked using different control loops. As a result, considerable flexibility is available to a designer to track the time reference signal.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
The present invention will be described with reference to the accompanying drawings, wherein:
1. Overview and Discussion of the Invention
The present invention is described in the context of clock recovery circuit 300 (
In operation, PLL circuit 310 receives as input a time reference 301 and generates output signal 312. While generating the output signal, PLL signal 310 attempts to synchronize the output signal 312 with time reference. Analog filter 320 filters any undesirable spectral components in the output signal 312 and provides the filtered signal as input to PLL circuit on input 302.
PLL circuit 310 is implemented using digital components and a designer is provided considerable flexibility to specify the degree or manner in which output signal 312 should track reference signal 301. Due to such a flexibility, the bandwidth of PLL circuit 310 can be dynamically varied such that PLL circuit 310 can be made to adequately track reference signal 301. Such a close tracking may prevent relative skewing among the display lines.
As PLL circuit 310 is implemented using digital components, the circuit can be implemented to have a narrow bandwidth loop. Conventional analog PLLs may require large capacitors to implement an equivalent circuit. As already explained in the background section, integration of large capacitors into a semiconductor integrated circuit may be problematic.
Analog filter 320 can be conventional and is implemented using analog components in a known way. The output signal of analog signal corresponds to the clock (e.g., sampling clock) synchronized with the time reference REF. The output signal is divided by K, where K may correspond to the number of samples taken per each horizontal source image line.
Before describing the invention in great detail, it is useful to describe an example environment in which the invention can be implemented. The details of implementation and operation of clock recovery circuit 300 are then explained in detail.
2. Example Environment
In a broad sense, the invention can be implemented in any graphics system having a digital display unit. Such systems include, without limitation, lap-top and desk-top personal computer systems (PCS), work-stations, special purpose computer systems, central purpose computer systems, and many others. The invention may be implemented in hardware, software, firmware, or combination of the like. One or more embodiments which can use the clock recovery circuit of the present invention is described in the co-pending application entitled, “A Method and Apparatus for Upscaling an Image”, which is referred to in the section above entitled “Related Applications.”
Graphics controller 760 generates analog image data and a corresponding reference signal, and provides both to digital display unit 200. The analog image data can be generated, for example, based on pixel data received from CPU 710 or from an external encoder (not shown). In one embodiment, the analog image data is provided in RGB format and the reference signal includes the VSYNC and HSYNC signals well known in the art and explained above. However, it should be understood that the present invention can be implemented with analog image data and/or reference signals in other formats. For example, analog image data can include video signal data also with a corresponding time reference signal.
Digital display unit 770 can include a display screen having pixels as explained with reference to
CPU 710, RAM 720 and peripherals 730 are conventional in one embodiment of the present invention. CPU 710 can be, for example, a processor such as a Pentium Processor available from Intel Corporation. RAM 720 represents the system/main memory for storing instructions and data. The instructions and data may be read from a peripheral device such a hard-disk. CPU 710 executes the instructions using the data to provide various functions. As a part of executing the instructions, CPU 710 may send commands to graphics controller 710, which generates analog display signal data in a known way. The manner in which an example embodiment of digital display unit 770 displays the image corresponding to the analog display signal will be explained in further detail below.
3. Example Embodiment of Digital Display Unit 770 of the Present Invention
In one embodiment, digital display unit 770 is implemented to operate with a computer system. Digital display unit 770 can be in the form of a flat-panel monitor used in lap-top (note-book computers), a flat-monitor used in desk-top computers and workstations, among other forms. However, it will be apparent to one skilled in the relevant arts how to implement a digital display unit for other graphics system environments such as flat monitor television systems by reading the description provided herein.
In operation, ADC 810 receives analog signal data on line 801 and a sampling clock signal on line 851. ADC 810 is conventional and samples the analog signal data according to the sampling clock signal. ADC 810 provides the pixel data on line 812 to upscaler 820.
Upscaler 820 uses the pixel data received on line 812 to optionally upscale the image represented by the pixel data. The image may be upscaled, for example, due to the lager size of display screen 100. An embodiment of upscaler 820 is described in co-pending application entitled, “A Method and Apparatus for Upscaling an Image”, which is referred to above in the section entitled “Related Applications.” In the co-pending application, upscaler 820 may be described as including the clock generation circuit 850 also.
Clock generator 802 generates the clock signals to ADC 810, upscaler 820 and panel interface 830. The individual clock signals may have different frequencies depending on the overall design. One or more the individual clock signals may be synchronized with time reference signal 802 by using the clock recovery circuit of the present invention. The manner in which different frequencies may be computed in one embodiment is also described in the co-pending application entitled, “A method and apparatus for upscaling an image.”
In one embodiment, time reference signal 802 may correspond to HSYNC signal. In another embodiment, time reference signal 802 may correspond to VSYNC signal. However, it should be understood that time reference signal 802 may correspond to any other signal (including a combination of HSYNC and VSYNC) as suited in the specific environment.
Display screen 100 is explained in detail above. Display screen 100 may be implemented using any digital screen technologies such as active/passive liquid crystal display (LCD) technologies. Panel interface 830 is designed to generate display signals to display image on display screen 100. Panel interface 830 can be implemented in a known way to generate display signals to display screen 100 from the pixel data received from upscaler 820.
The manner in which the clock recovery circuit synchronizes (or attempts to synchronize) the generated clock with the time reference will now be explained in detail. Specifically, PLL circuit 310 will be explained first. Then, analog filter 320 will be explained. For purpose of illustration, the time reference will be assumed to include a HSYNC signal. However, the present invention can be practiced with other types of reference signals as well.
4. Overview of Digital PLL Circuit of the Present Invention
In operation, PFD 410 compares the phase and frequency of time reference (HSYNC) signal and feedback signal. PFD 410 is conventional and generates signals on EARLY and LATE lines depending on whether reference signal lags or leads the feedback signal. In one embodiment, a pulse is generated according to the lead or lag and the duration of the pulse is proportional to the amount of lead or lag.
The resynchronization process is achieved by having two separate blocks for correcting long term frequency drifts and phase jitters in the reference signal. By having two separate blocks, the designer may have more control over the resynchronization process.
In general, frequency correction logic 420 is designed to correct the long term frequency drifts in the reference signal. The frequency drifts generally correspond to a change in the reference frequency, typically in the range of few hertz. The drifts can be a result of, for example, temperature fluctuations in the source system generating the source image. Frequency correction logic 420 can be advantageously designed to track the reference signal over a prolonged period.
Adder 440 adds (subtracts) the frequency correction number provided by frequency correction logic 430 to Pnom frequency. Pnom corresponds to an expected frequency of the sampling clock and is used during the frequency acquisition phase. Frequency acquisition phase refers to a time duration during which the PLL loop is stabilizing and locking with the frequency of the reference signal. By providing the Pnom signal, the frequency acquisition period can be decreased.
However, digital PLL 310 can operate without Pnom signal. In this case, the frequency acquisition can take an extended period of time. After the frequency acquisition period is complete, Pnom may not be used. Phase correction logic 430 tracks phase fluctuations in the time reference. The output of phase correction logic 430 represents the degree (or amount) of phase by which the clock signal being generated should be corrected due to the phase difference between time reference signal and feedback signal.
The output of adder 440 represents the current frequency of the loop. The outputs of phase correction logic 420 and adder 440 are added using adder 450. Thus, the output of adder 450 represents the total of Pnom, frequency correction provided by frequency correction logic 420, and phase correction provided by phase correction logic 430. This total represents how far the phase in DTO 460 is advanced per DTO clock cycle. This total can change during each reference clock cycle.
DTO 460 is conventional and is also known as a phase accumulator. DTO 460 generates as an output a ramp signal having a fundamental frequency and other undesirable spectral components. The fundamental frequency represents the frequency of the clock which is synchronized with the time reference signal. The spectral frequencies are undesirable as they may contribute to clock jitter. Accordingly, these spectral frequencies are eliminated using the analog filter 320. DAC 470 converts the digital output of DTO into an analog form suited for processing by analog filter. Analog filter 320 is explained in further detail below. Before describing analog filter 320 in detail, an implementation of digital PLL circuit 310 is explained first.
5. An Implementation of Digital PLL
From the overview provided above, several alternative embodiments of digital PLL can be implemented without departing from the scope and spirit of the present invention. One of such embodiments will now be described with reference to
As to phase comparison, PFD 603 has two output signal lines early 604 and late 605 indicating whether the feedback signal (FBACK) is early or late in phase in relation to time reference signal REF. In one embodiment, PFD 603 generates a pulse on early 604, with the pulse having a duration which is proportional to the phase by which FBACK signal is early in comparison to REF signal. The pulse duration is measured in number of reference clock periods, where reference clock refers to a clock of which PLL circuit 310 operates. The pulses on early signal 604 and late signal 605 will be generally referred to as an error pulse. Late signal 605 is similarly explained.
PFD 603 stops comparing REF and FBACK signal when STOP signal is asserted. When the comparison is stopped, both LATE and EARLY signals are unasserted. Charge/discharge control 650 causes STOP signal to be asserted when the phase correction integrator can overflow. Comparison signal limiter 610 causes STOP signal to be asserted when the phase difference exceeds a predetermined number.
As to the frequency correction, frequency correction control 620, multiplexor 630, adder 627 and flip-flops 625 operate to provide the frequency correction. When PLL circuit is initialized (e.g., during the beginning of phase acquisition) as indicated by INIT signal, frequency correction control 620 causes multiplexor 630 to select as output the value on input having number 2. At the same time, A/S (Add/Subtract) signal is asserted to low, causing adder 627 to be set to a zero value by subtracting current accumulator value from itself.
Frequency correction control 620 then causes multiplexor 630 to select the Pnom value. Pnom corresponds to an expected frequency of the sampling block being generated. Accordingly, the frequency acquisition period is reduced to a few cycles assuming that the REF signal has a frequency which is in slight deviation from the expected frequency. Without Pnom, frequency acquisition may take several cycles.
After frequency acquisition, frequency correction control 620 causes Fdp value to be selected by multiplexor 630. The Fdp value is added/subtracted during each reference clock cycle there is the error pulse. Addition of the Fdp value causes the clock frequency to be increased and subtraction causes the clock frequency to be decreased.
Fdp value is provided from a register. The Fdp value represents the loop bandwidth. A higher value of Fdp implies that the PLL 310 will respond faster to changes and lower value implies that the PLL 310 will be more stable. However, as the Fdp value can be changed instantaneously (i.e., within a reference clock cycle) by setting the register, the loop bandwidth can also be changed instantaneously.
Accordingly, a designer of the digital PLL 310 is given considerable flexibility to change the loop bandwidth depending on the specific situation. For example, during phase acquisition loop, Fdp value can be set fairly high, and it can be set to a low value once the loop stabilizes. In addition, Fdp can be based on adaptive schemes which base individual Fdp values on the historical values of phase corrections. The manner in which Fdp value is set in one embodiment will be explained below. Frequency correction control 620 enables FC-CE signal only during the length of the error pulse. The output of flip-flop 625 represents the current average frequency of the clock being generated.
As to the phase correction, phase correction is broadly explained first. Charge/discharge control 650 along with the associated circuitry may be viewed as a leaky integrator, but implemented in digital domain. The integrator is charged to a level using the PPDP value. The level to which it is charged depends on the duration of the error pulse length. After it is charged, the integrator is slowly discharged using the NPDP value. The NPDP value is smaller in value in comparison to PPDP value and thus the discharge occurs during an extended period of time. The phase correction is performed during the discharge cycles. The manner in which charging and discharging are performed is explained in further detail below. The manner in which NPDP and PPDP values are computed in one embodiment will then be explained.
Charge/discharge control 650, multiplexor 655, adder 660, and flip-flop 665 together determine the charge on the integrator. It should be noted that flip-flop 665 (and other flip-flops described here) in reality includes several flip-flops, with each flip-flop storing one bit. The value in adder 660 is cleared at the beginning of each time reference cycle (e.g., when a HSYNC pulse is received). The PPDP value is added to adder 660 during each reference cycle (i.e., the internal clock of PLL) the error pulse is present. If the result of the addition exceeds a predetermined threshold, the integrator is determined to have overflown, and the integrator overflow detector 673 causes the STOP signal coupled to PFD 603 be asserted. When the end of the error pulse is encountered, flip-flop 665 stores a value indicative of the charge on the integrator.
After the charging is complete, the discharge phase is begun. Phase correction of the clock is performed during the discharge phase. During the discharge phase, charge/discharge control 650 causes NPDP value subtracted iteratively from accumulator 660 during each reference clock cycle. During each discharge clock cycle, inactive REMINDER signal causes NPDP value to be selected by multiplexor 652. Also, phase correction control 675 provides PCORR signal so as to gate the output of AND logic 677 to adder 680. Otherwise, PCORR signal is set at low signal level (logical value of 0) to set the output of AND logic 677 to zero. Phase correction control 675 asserts the A/S input of adder 680 to cause the output of adder 677 to be added or subtracted. The value is added if the REF signal is ahead of FBACK signal and subtracted otherwise.
As NPDP value is subtracted during each reference clock cycle, it is possible that the result after the subtraction may be a negative number. In this case, the clock signal has been over corrected. Accordingly, sign and zero crossing detector 670 detects that the phase has been over corrected and causes charge/discharge control 650 to take corrective action. The negative number is stored in flip-flop 674.
Charge/discharge control 650 asserts REMINDER signal to 1 to cause multiplexor 652 to select the value stored in flip-flop 674. The selected value to provided to adder 680, which corrects the overcorrection. Phase correction control 675 switches the value on the A/S input to adder 680. That is, if previously the a 0 value is provided, a value of 1 is provided when forwarding the overcorrection parameter.
The operation of DTO has been explained above with reference to
LUT 690 is conventional and translates the phase output of DTO 460 to an amplitude value. The phase value may be converted to either a sine wave or a triangle as is also known well in the art. DAC 695 converts the output of LUT 690 to an analog signal for suitable processing by analog filter 320. An embodiment of analog filter 320 is explained later.
It is again noted, that the above description of
6. Computation of the loop parameters
Pnom can be calculated based on the number of reference clocks in the hor line (Hor_Rcount):
where Trclk represents the clock period of reference clock and Th represents the horizontal period (time between two successive Hsync pulses).
Here, Qdto is DTO module, (i.e., 2**n, where n is the number of bits in DTO). It should be noted that Pnom isn't dependent on locking scheme. That is, the clock signal can be locked on HSYNC, VSYNC, or the like.
Positive slope (Charging) parameter for phase correction loop is derived from Pnom. It is also independent of the locking scheme. Kpdp controls damping of phase correction loop. For optimal tracking it may be set to 3 or 3.
Negative slope parameter (discharging) is derived from Ppdp. NPDP is usually close to Ppdp if loop is unlocked and several times smaller (8 . . . 16) if loop is locked (to minimize phase jumps).
Knpdp=2 . . . 16
Frequency correction parameter is dependent on locking scheme. It means amount of frequency adjustment per one Rclk phase tracking error.
If the FBACK signal is locked on HSYNC pulses as a time reference
If FBACK signal is locked in Vsync pulses as a time reference
Here Vdiv is vertical Hsync divider (1 . . . n). If Vdiv is 1, every Hsync is used for comparison. If Vdiv is 2, every other Hsync is used, etc. Vtotal is number of lines in the source frame if VSYNC locking is used.
7. Analog Filter 320
As noted above, analog filter 320 is designed to preserve the fundamental frequency generated by DTO while eliminating the other frequencies. Analog filter 320 can be implemented using active or passive filters or using a phase-locked loop as is well-known in the art. An example embodiment of analog filter 320 is illustrated with reference to
Analog filter 320 is conventional and includes a DAC reconstruction filter 510. Schmidt trigger 520 slices the sine-wave in a known way to convert the sine-wave into digital signal (two level quantization). The PLL loop comprising PFD 530, charge pump 540, loop filter 550, VCO 560, and divider 580 is designed to eliminate all the undesirable frequencies, while preserving the fundamental frequency. The value of N in divider 580 is kept relatively small (at or below 8). VCO 560 may be designed to generate sampling clock signal, which can be used to sample the analog signal data. Dividers 570 and 580 may be used to shift the Vco frequency into the operating range of Vco 560.
Thus, the output of analog filter 320 includes filtered signal with well-suppressed spurious spectral components.
While various embodiments of the present invention have been described above, it should he understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4018990||Feb 13, 1975||Apr 19, 1977||Consolidated Video Systems, Inc.||Digital video synchronizer|
|US4346407||Jun 16, 1980||Aug 24, 1982||Sanders Associates, Inc.||Apparatus for synchronization of a source of computer controlled video to another video source|
|US4432009||Sep 24, 1981||Feb 14, 1984||Rca Corporation||Video pre-filtering in phantom raster generating apparatus|
|US4462024||Sep 24, 1981||Jul 24, 1984||Rca Corporation||Memory scanning address generator|
|US4488170||Jul 12, 1982||Dec 11, 1984||U.S. Philips Corporation||Synchronizing circuit for a television receiver|
|US4527145||Sep 8, 1982||Jul 2, 1985||Siemens Aktiengesellschaft||Method and apparatus for the digital control of the phase of the system clock of a digital signal processing system|
|US4554582||Aug 31, 1983||Nov 19, 1985||Rca Corporation||Apparatus for synchronizing a source of computer controlled video to another video source|
|US4590602||Aug 18, 1983||May 20, 1986||General Signal||Wide range clock recovery circuit|
|US4616259||Apr 27, 1984||Oct 7, 1986||General Electric Company||Instant phase correction in a phase-locked loop|
|US4686560||May 30, 1986||Aug 11, 1987||Rca Corporation||Phase locked loop system including analog and digital components|
|US4694327||Mar 28, 1986||Sep 15, 1987||Rca Corporation||Digital phase locked loop stabilization circuitry using a secondary digital phase locked loop|
|US4700217||Aug 5, 1986||Oct 13, 1987||Rca Corporation||Chrominance signal phase locked loop system for use in a digital television receiver having a line-locked clock signal|
|US4703340||May 2, 1986||Oct 27, 1987||Rca Corporation||Frequency division multiplexed analog to digital converter|
|US4720745||Jun 22, 1983||Jan 19, 1988||Digivision, Inc.||Method and apparatus for enhancing video displays|
|US4802009||Jul 13, 1987||Jan 31, 1989||Rca Licensing Corporation||Digitally controlled phase locked loop system|
|US4893319||Dec 19, 1988||Jan 9, 1990||Planar Systems, Inc.||Clock regeneration circuit employing digital phase locked loop|
|US4906941||Oct 19, 1988||Mar 6, 1990||Kabushiki Kaisha Toshiba||Digital phase locked loop circuit|
|US4952125||Mar 30, 1989||Aug 28, 1990||Hitachi, Ltd.||Nonlubricated screw fluid machine|
|US5005079||Mar 13, 1990||Apr 2, 1991||Sanyo Electric Co., Ltd.||Automatic frequency control circuit|
|US5010403||Apr 12, 1990||Apr 23, 1991||Tektronix, Inc.||Measurement of timebase jitter for component video|
|US5027212||Dec 6, 1989||Jun 25, 1991||Videologic Limited||Computer based video/graphics display system|
|US5029017||Jun 7, 1990||Jul 2, 1991||Konishiroku Photo Industry Co., Ltd.||Image processing apparatus capable of enlarging/reducing apparatus|
|US5086295||Jan 12, 1988||Feb 4, 1992||Boettcher Eric R||Apparatus for increasing color and spatial resolutions of a raster graphics system|
|US5101197||Aug 17, 1988||Mar 31, 1992||In Focus Systems, Inc.||Electronic transparency method and apparatus|
|US5184091||Jun 4, 1991||Feb 2, 1993||Zenith Electronics Corporation||Circuit for phase locking an oscillator within any one of a plurality of frequency ranges|
|US5185603||Jul 13, 1990||Feb 9, 1993||Medin David L||Apparatus for synchronizing computer and video images to be simultaneously displayed on a monitor and method for performing same|
|US5202669||Jan 11, 1990||Apr 13, 1993||Sharp Kabushiki Kaisha||Display control device for superimposing data with a broadcast signal on a television screen|
|US5227882||Sep 25, 1991||Jul 13, 1993||Sharp Kabushiki Kaisha||Video display apparatus including display device having fixed two-dimensional pixel arrangement|
|US5276515||Sep 8, 1992||Jan 4, 1994||Hitachi, Ltd.||Compatible wide aspect ratio receiver with spatial filtering for variable zoom|
|US5280345||Apr 3, 1992||Jan 18, 1994||Matsushita Electric Industrial Co., Ltd.||Jitter correction circuit for reducing jitter components of a luminance signal in video information compression|
|US5331346||Oct 7, 1992||Jul 19, 1994||Panasonic Technologies, Inc.||Approximating sample rate conversion system|
|US5335018||Oct 25, 1993||Aug 2, 1994||U.S. Philips Corporation||Digital phase-locked loop|
|US5335295||May 8, 1991||Aug 2, 1994||International Business Machines Corporation||System and method for scaling a digital image|
|US5349385||Aug 6, 1992||Sep 20, 1994||Florida Atlantic University||Adaptive scan converter|
|US5359366||Dec 24, 1992||Oct 25, 1994||Victor Company Of Japan, Ltd.||Time base correction apparatus|
|US5369376||Nov 29, 1991||Nov 29, 1994||Standard Microsystems, Inc.||Programmable phase locked loop circuit and method of programming same|
|US5406308||Feb 1, 1994||Apr 11, 1995||Nec Corporation||Apparatus for driving liquid crystal display panel for different size images|
|US5410357||Apr 12, 1993||Apr 25, 1995||The United States Of America As Represented By The Secretary Of The Navy||Scan converter and method|
|US5455628||Sep 16, 1993||Oct 3, 1995||Videologic Limited||Converter to convert a computer graphics signal to an interlaced video signal|
|US5459766||Apr 1, 1994||Oct 17, 1995||U.S. Philips Corporation||Digital phase-locked loop|
|US5469223||Mar 4, 1994||Nov 21, 1995||Auravision Corporation||Shared line buffer architecture for a video processing circuit|
|US5497202||Mar 13, 1995||Mar 5, 1996||Samsung Electronics Co., Ltd.||Automatic digital frequency control circuit|
|US5515108||Aug 17, 1994||May 7, 1996||Samsung Electronics Corporation||Digital automatic frequency control method and circuit therefor|
|US5528305||Sep 8, 1994||Jun 18, 1996||Samsung Electronics Co., Ltd.||Method for reducing empty sides of a wide screen and an apparatus thereof|
|US5528307||Feb 27, 1995||Jun 18, 1996||Canon Kabushiki Kaisha||Clock generator|
|US5534934||Jun 16, 1994||Jul 9, 1996||Hitachi, Ltd.||Television receiver capable of enlarging and compressing image|
|US5534936||Feb 17, 1995||Jul 9, 1996||Goldstar Co., Ltd.||Apparatus for reducing flickers of encoder when digitally converting video signals from non-interlaced to interlaced format|
|US5535018||Nov 30, 1995||Jul 9, 1996||Canon Kabushiki Kaisha||Information processing apparatus|
|US5539473||Oct 13, 1995||Jul 23, 1996||Hewlett-Packard Company||Dot clock generation with minimal clock skew|
|US5574406||Apr 19, 1994||Nov 12, 1996||Rca Thomson Licensing Corporation||Phase lock loop with error measurement and correction in alternate periods|
|US5574572||Sep 7, 1994||Nov 12, 1996||Harris Corporation||Video scaling method and device|
|US5587742||Aug 25, 1995||Dec 24, 1996||Panasonic Technologies, Inc.||Flexible parallel processing architecture for video resizing|
|US5594467||May 30, 1991||Jan 14, 1997||Video Logic Ltd.||Computer based display system allowing mixing and windowing of graphics and video|
|US5600347||Dec 30, 1993||Feb 4, 1997||International Business Machines Corporation||Horizontal image expansion system for flat panel displays|
|US5623311||Oct 28, 1994||Apr 22, 1997||Matsushita Electric Corporation Of America||MPEG video decoder having a high bandwidth memory|
|US5638131||Oct 7, 1994||Jun 10, 1997||Brooktree Corporation||Method to synchronize video modulation using a constant time base|
|US5646696||May 28, 1996||Jul 8, 1997||Intel Corporation||Continuously changing image scaling performed by incremented pixel interpolation|
|US5703618||Nov 22, 1995||Dec 30, 1997||Cirrus Logic, Inc.||Method and apparatus for upscaling video images when pixel data used for upscaling a source video image are unavailable|
|US5710573||May 4, 1995||Jan 20, 1998||Winbond Electronics Corp.||Scaled video output overlaid onto a computer graphics output|
|US5719633||Dec 20, 1995||Feb 17, 1998||Matsushita Electric Industrial Co., Ltd.||Video signal format conversion apparatus using simplified shifting and processing control|
|US5739808||Oct 25, 1995||Apr 14, 1998||Canon Kabushiki Kaisha||Display control method and apparatus|
|US5781241||Nov 8, 1996||Jul 14, 1998||Chrontel, Inc.||Apparatus and method to convert computer graphics signals to television video signals with vertical and horizontal scaling requiring no frame buffers|
|US5790096||Sep 3, 1996||Aug 4, 1998||Allus Technology Corporation||Automated flat panel display control system for accomodating broad range of video types and formats|
|US5790614||Jul 2, 1996||Aug 4, 1998||Alcatel Network Systems, Inc.||Synchronized clock using a non-pullable reference oscillator|
|US5796392||Feb 24, 1997||Aug 18, 1998||Paradise Electronics, Inc.||Method and apparatus for clock recovery in a digital display unit|
|US5838381||Dec 20, 1996||Nov 17, 1998||Hitachi, Ltd.||Image display apparatus capable of displaying personal computer signals and television signal by conversion into a signal of a higher number of pixels|
|US5841430||Jun 24, 1997||Nov 24, 1998||Icl Personal Systems Oy||Digital video display having analog interface with clock and video signals synchronized to reduce image flicker|
|US5874937||Oct 10, 1996||Feb 23, 1999||Seiko Epson Corporation||Method and apparatus for scaling up and down a video image|
|US5909205||Nov 29, 1996||Jun 1, 1999||Hitachi, Ltd.||Liquid crystal display control device|
|US5914753||Jun 25, 1998||Jun 22, 1999||Chrontel, Inc.||Apparatus and method to convert computer graphics signals to television video signals with vertical and horizontal scaling requiring no frame buffers|
|US5926174||May 23, 1996||Jul 20, 1999||Canon Kabushiki Kaisha||Display apparatus capable of image display for video signals of plural kinds|
|US5940061||Sep 20, 1996||Aug 17, 1999||Kabushiki Kaisha Toshiba||Liquid-crystal display|
|US5953074||Oct 10, 1997||Sep 14, 1999||Sage, Inc.||Video adapter circuit for detection of analog video scanning formats|
|US6002446||Nov 17, 1997||Dec 14, 1999||Paradise Electronics, Inc.||Method and apparatus for upscaling an image|
|US6002810||Apr 15, 1996||Dec 14, 1999||Hitachi, Ltd.||Resolution conversion system and method|
|US6037925||Apr 17, 1997||Mar 14, 2000||Samsung Electronics Co., Ltd.||Video signal converting apparatus and a display device having the same|
|US6046737||Jul 31, 1996||Apr 4, 2000||Fujitsu Limited||Display device with a display mode identification function and a display mode identification method|
|US6067071||Jun 27, 1996||May 23, 2000||Cirrus Logic, Inc.||Method and apparatus for expanding graphics images for LCD panels|
|US6078317||Oct 6, 1995||Jun 20, 2000||Canon Kabushiki Kaisha||Display device, and display control method and apparatus therefor|
|US6078361||Oct 10, 1997||Jun 20, 2000||Sage, Inc||Video adapter circuit for conversion of an analog video signal to a digital display image|
|US6115020||Oct 4, 1996||Sep 5, 2000||Fujitsu Limited||Liquid crystal display device and display method of the same|
|US6121947||Apr 20, 1999||Sep 19, 2000||Hitachi, Ltd.||Liquid crystal display Control device|
|US6144355||Oct 16, 1996||Nov 7, 2000||Kabushiki Kaisha Toshiba||Display device including a phase adjuster|
|US6195079||Oct 10, 1997||Feb 27, 2001||Sage, Inc.||On-screen user interface for a video adapter circuit|
|US6215467||Apr 26, 1996||Apr 10, 2001||Canon Kabushiki Kaisha||Display control apparatus and method and display apparatus|
|US6219023||Jul 7, 1997||Apr 17, 2001||Samsung Electronics Co., Ltd.||Video signal converting apparatus with display mode conversion and a display device having the same|
|US6310602||Jul 12, 2000||Oct 30, 2001||Hitachi, Ltd.||Liquid crystal display system capable of reducing and enlarging resolution of input display data|
|US6310618||Nov 13, 1998||Oct 30, 2001||Smartasic, Inc.||Clock generation for sampling analong video|
|US6320574||May 20, 1998||Nov 20, 2001||Genesis Microchip, Corp.||Circuit and method for generating pixel data elements from analog image data and associated synchronization signals|
|USRE40859 *||Jul 21, 2009||Genesis Microchip (Delaware) Inc.||Method and system for displaying an analog image by a digital display device|
|USRE41192 *||Apr 21, 2006||Apr 6, 2010||Genesis Microchip Inc.||Method and system for displaying an analog image by a digital display device|
|EP0299724A2||Jul 13, 1988||Jan 18, 1989||RCA Thomson Licensing Corporation||Digitally controlled phase locked loop system|
|EP0405523A2||Jun 27, 1990||Jan 2, 1991||Sony Corporation||Charge pump circuit|
|EP0479508A2||Sep 27, 1991||Apr 8, 1992||Sharp Kabushiki Kaisha||Video display apparatus including display device having fixed two-dimensional pixel arrangement|
|EP0502600A2||Jan 15, 1992||Sep 9, 1992||nVIEW CORPORATION||Method and apparatus for displaying RGB and sync video without auxiliary frame storage memory|
|EP0609843A1||Feb 1, 1994||Aug 10, 1994||Nec Corporation||Apparatus for driving liquid crystal display panel for different size images|
|EP615222A1||Title not available|
|JPS6314522A||Title not available|
|JPS56137736A||Title not available|
|JPS61103369A||Title not available|
|1||"Combined Digital Zooming and Digital Effects System Utilizing CCD Signal Characteristics", IEEE Transactions on Consumer Electronics, vol. 39, No. 3, Aug. 1993, pp. 398-406, Palk et al.|
|2||"Fast Prototyping of Video Interface Controller for AML CD System", Proceedings of the 4th Asian Symposium on Information Display, pp. 195-198, Cheng et al. Feb. 13, 1997.|
|3||"Hardware Accelerators for Bitonal Image Processing" Digital Technical Journal, vol. 3 No. 4, Fall 1991, pp. 1-36, Payson et al., Fall 1991.|
|4||"High Speed Image Scaling for Integrated Document Management", Second ACM-SIGOA Conference on Office Information Systems, vol. 5, Nos. 1-2, pp. 36-45, Tabata et al., Jun. 25, 1984.|
|5||"High-Speed Rotation of Digital Images by Raster Scanning and Table-Lookup Operations", Systems and Computers in Japan, vol. 17, No. 11, pp. 76-87, Tabata et al., 1986.|
|6||"Initial Determination Concerning Violation of Section 337 and Recommended Determination on Issues Concerning Permanent Relief", Publication Versions, United States International Trade Commission, Washington, D.C., Apr. 14, 2004.|
|7||"Initial Determination on Remand Concerning Violation of Section 337", Public Version, United States International Trade Commission, Washington, D.C., May 20, 2004.|
|8||"Low Cost Video Scaler and Gray Scale Integrator", IEEE Transactions on Biomedical Engineering, vol. 41, No. 7, pp. 698-703, Pietras & Bolanowski Jul. 1, 1994.|
|9||D'Alto et al. publication: A Highly Integrated Scanning Rate Converter for IQTV, 1994 IEEE-Jun. 27, 1994.|
|10||D'Alto et al. publication: A Highly Integrated Scanning Rate Converter for IQTV, 1994 IEEE—Jun. 27, 1994.|
|11||Development of 13.3 In. Super TFT-LCD Monitor, SID International Symposium, Digest of Technical Papers, pp. 414-417, Kasai et al., May 1996.|
|12||Ferraro: Programmer's Guide to the EGA and VGA Cards, 1988 p. 32, D'Alto V., et al.|
|13||Final Office Action dated Oct. 7, 2009 from U.S. Appl. No. 11/408,528.|
|14||Katsumata Article: "Development of Picture Converting System Applying an NTSC Signal to a Wide Aspect Display" K. Katsumata, et al., IEEE Trans. on CE; vol. 38 No. 3, pp. 303-312, Aug. 1992.|
|15||Notice of Allowance dated Mar. 16, 2009 from U.S. Appl. No. 10/720,011.|
|16||Notice of Allowance dated Sep. 24, 2009 from U.S. Appl. No. 11/408,669.|
|17||Office Action dated Aug. 3, 2007 from U.S. Appl. No. 10/720,001.|
|18||Office Action dated Feb. 5, 2008 from U.S. Appl. No. 11/408,528.|
|19||Office Action dated Jan. 9, 2009 from U.S. Appl. No. 11/408,669.|
|20||Office Action dated Oct. 13, 2006 from U.S. Appl. No. 10/720,001.|
|U.S. Classification||345/213, 345/211, 348/537, 345/204, 348/512, 345/501, 345/212|
|International Classification||G09G5/00, H03L7/093, H03L7/07, H03L7/085, G09G3/20, H03L7/06|
|Cooperative Classification||H03L7/085, H03L7/093, H03L7/07, G09G5/008|
|European Classification||H03L7/093, H03L7/07, G09G5/00T4C, H03L7/085|
|Aug 30, 2011||RF||Reissue application filed|
Effective date: 20110624
|Sep 18, 2012||CC||Certificate of correction|