|Publication number||USRE42653 E1|
|Application number||US 12/722,009|
|Publication date||Aug 30, 2011|
|Filing date||Mar 11, 2010|
|Priority date||Dec 7, 2001|
|Also published as||US6720649, US7342304, US20030107124, US20040164404|
|Publication number||12722009, 722009, US RE42653 E1, US RE42653E1, US-E1-RE42653, USRE42653 E1, USRE42653E1|
|Original Assignee||Siliconware Precision Industries Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (1), Classifications (28), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of application U.S. Ser. No. 10/211,430, filed on Aug. 2, 2002 now U.S. Pat. No. 6,720,649.
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package with a heat dissipating structure.
Ball grid array (BGA) semiconductor packages are mainstream package products in the light of providing a sufficient amount of I/O (input/output) connections for use with semiconductor chips that incorporate high density of electronic elements and electronic circuits. As such a highly-integrated chip operates to consequently produce relatively more heat, it is thereby important to promptly remove the heat from the chip; otherwise, heat accumulation in the chip would undesirably damage electrical performances and reliability of package products. Moreover, for protecting internal components of the semiconductor package against external contamination, it usually forms an encapsulant that encapsulates the chip and other conductive elements such as bonding wires. The encapsulant is made of a resin material with poor thermal conductivity (coefficient of thermal conductivity around 0.8w/m°K); therefore, the chip-generated heat would not be efficiently dissipated to the atmosphere through the encapsulant; this would thereby adversely affect performances and lifetime of the chip by virtue of heat accumulation.
In response to the above heat-dissipation, problem, there is adopted a heat dissipating structure in the BGA semiconductor package for facilitating dissipation of heat generated from the chip. However, this heat dissipating structure is embedded in the encapsulant, such that the chip-generated heat still needs to pass through the encapsulant for dissipation. Therefore, this structural arrangement cannot achieve satisfactory improvement in heat dissipating efficiency for the semiconductor package.
Accordingly, U.S. Pat. No. 5,977,626 discloses a semiconductor package with a heat dissipating structure being partly exposed to the atmosphere and also directly contacting with a chip. As shown in
However, the above semiconductor package 3 has significant drawbacks. In compliance with low profile packaging technology and high integration of chip development, substrates are preferred to be down-sized nearly to chip scale, and incorporated with sufficient conductive elements such as bonding wires required for accommodating highly-integrated chips with densely-arranged electronic elements or circuits. As a result, the above heat dissipating structure 33 is considered to occupy too much space on the substrate 30 in a manner that, the receiving space 35 embraced by the flat portion 330 and the single encircled support portion 331 with integrally-formed contact portion 332, makes all internal components of the semiconductor package 3 position-restrictedly enclosed in the receiving space 35. Thereby, the bonding wires 32, passive components or other electronic components (not shown) can only be disposed on the substrate 30 at area within coverage of the heat dissipating structure 33 in the receiving space 35. This drawback makes the semiconductor package 3 with the heat dissipating structure 33 hardly applied for accommodating highly-integrated chips that require a large amount of active and passive components as well as conductive elements to be comfortable situated on the substrate 30 for achieving desirable operational and electrical performances.
Further due to the heat dissipating structure 33 being located outside area for incorporating electronic components on the substrate 30, in another aspect, the substrate 30 may need to be increasingly sized in order to dispose a sufficient number of active and passive components as well as conductive elements on the substrate 30; this would make the substrate 30 considerably larger in size than the chip 31, thereby unfavorable to profile miniaturization.
An objective of the present invention is to provide a semiconductor package with a heat dissipating structure, wherein the heat dissipating structure is arranged in a manner not to interfere with layout of a chip, bonding wires or passive components mounted on the substrate, thereby improving flexibility in component arrangement in the semiconductor package.
Another objective of the invention is to provide a semiconductor package with a heat dissipating structure, so as to reduce surface area of a substrate occupied by the heat dissipating structure, and thus to increase layout area on the substrate for accommodating bonding wires and passive components.
A further objective of the invention is to provide a semiconductor package with a heat dissipating structure, so as to improve heat dissipating efficiency of the semiconductor package.
To achieve the above and other objectives, the present invention proposes a semiconductor package with a heat dissipating structure, comprising: a substrate; at least a chip mounted on the substrate and electrically connected to the substrate via a plurality of bonding wires; a heat dissipating structure comprising a flat portion, and a plurality of support portions formed at edges of the flat portion for supporting the flat portion in position above the chip, wherein the support portions are mounted at predetermined area on the substrate to be free of interference with arrangement of the chip and the bonding wires, and the support portions are arranged to form a space embraced by adjacent support portions and the flat portion, which space is dimensioned to accommodate the bonding wires and to allow the bonding wires to pass through the space to reach area on the substrate outside coverage of the heat dissipating structure; an encapsulant formed on the substrate for encapsulating the chip and the bonding wires; and a plurality of solder balls implanted on the substrate and exposed to outside of the encapsulant.
In the above package structure, the flat portion of the heat dissipating structure is elevated above the chip by the support portions and forms a predetermined height difference with respect to the substrate, wherein the height difference is at least corresponding to height of wire loops of the bonding wires. Therefore, part of bond fingers where the bonding wires are bonded can be formed on the substrate at area outside the coverage of the heat dissipating structure, allowing the corresponding bonding wires to pass through the space embraced by adjacent support portions and the flat portion and to reach the outside-coverage bond fingers. Besides, passive components or other electronic components may also be desirably mounted on the substrate at area within or outside the coverage of the heat dissipating structure, thereby improving flexibility in component arrangement in the semiconductor package. Moreover, by the above structural arrangement, more flexibly-sized heat dissipating structures or chips can be adopted in the semiconductor package as long as the support portions of the heat dissipating structure are mounted on the substrate at area without affecting the arrangement of the chip and the bonding wires. Furthermore, the heat dissipating structure with multiple individual support portions, instead of a conventional single encircled support portion (as shown in
In another embodiment, the flat portion of the heat dissipating structure, having a top surface exposed to outside of the encapsulant and a bottom surface connected to the support portions, is formed with at least a peripherally-situated recess on the top surface and at least a protrusion on the bottom surface. During a molding process for forming the encapsulant by an encapsulating resin, when flowing to the peripherally-situated recess, the encapsulating resin would quickly absorb heat from an encapsulating mold and slow down its flowing speed without flashing over the exposed top surface of the flat portion, thereby helping assure reliability of fabricated package products. Moreover, the protrusion formed on the flat portion extends toward the chip mounted on the substrate and shortens the distance between the flat portion and the chip, by which heat generated from the chip can be efficiently transmitted to the heat dissipating structure for dissipation, such that heat dissipating efficiency of the semiconductor package is desirably improved.
The substrate 10 has a top surface 100 and a bottom surface 101 opposed to the top surface 100, each surface being formed with predetermined conductive traces (not shown) thereon. A plurality of conventional vias (not shown) are formed through the substrate 10 for electrically interconnecting the conductive traces on the top and bottom surfaces 100, 101. The substrate 10 may be made of epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, ceramic material, glass material, etc., and preferably BT resin.
A plurality of bond fingers 102 are formed and associated with corresponding conductive traces on the top surface 100 of the substrate 10, so as to allow the bonding wires 12 to be bonded to the bond fingers 102 respectively. The passive components 17, such as inductor, capacitor, resister, etc., are mounted on the top surface 100 of the substrate for modulating electrical performances in operation of the semiconductor package 1. The solder balls 15 are implanted on the bottom surface 101 of the substrate 10 at positions associated with corresponding conductive traces, and used to electrically connect the chip 11 to an external device such as a printed circuit board (PCB, not shown).
The chip 11 has an active surface 110 formed with a plurality of electric elements and electric circuits thereon, and a non-active surface 111 opposed to the active surface 110, wherein the non-active surface 111 is mounted on the top surface 100 of the substrate 10 by an adhesive 16 such as silver paste or a polyimide tape.
In accompany with reference to
Each of the support portions 131 may be formed with a contact portion 132 at a position in contact with the substrate 10, wherein the contact portion 132 substantially extends laterally with respect to the substrate 10. The contact portion 132 may be flexibly shaped as, but not limited to, a rectangle, triangle, semicircle, etc. Each of the support portions 131 may be further formed with at least a hole 134 (as shown in
Moreover, by the above structural arrangement, more flexibly-sized heat sinks 13 or chips 11 can be adopted in the semiconductor package 1 as long as the support portions 131 of the heat sink 13 are mounted on the substrate 10 at area without affecting the arrangement of the chip 11 and the bonding wires 12. Furthermore, the heat sink 13 with multiple individual support portions 131, instead of a conventional single encircled support portion (as shown in
The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8759956 *||Jul 5, 2012||Jun 24, 2014||Infineon Technologies Ag||Chip package and method of manufacturing the same|
|U.S. Classification||257/706, 257/707, 257/675|
|International Classification||H01L23/433, H01L23/34, H01L23/10, H01L23/31|
|Cooperative Classification||H01L2224/73265, H01L2224/85399, H01L2224/05599, H01L2924/00014, H01L2224/45099, H01L2924/181, H01L2924/01019, H01L24/48, H01L24/49, H01L23/4334, H01L2224/48091, H01L23/3128, H01L2924/19041, H01L2224/49171, H01L2224/49175, H01L2924/09701, H01L2924/15311, H01L2924/19105, H01L2224/48227|
|European Classification||H01L23/433E, H01L23/31H2B|
|Sep 23, 2011||SULP||Surcharge for late payment|
|Sep 23, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Mar 11, 2015||FPAY||Fee payment|
Year of fee payment: 8