|Publication number||USRE42864 E1|
|Application number||US 11/334,817|
|Publication date||Oct 25, 2011|
|Priority date||Sep 7, 2001|
|Also published as||US6683344, US20030067034|
|Publication number||11334817, 334817, US RE42864 E1, US RE42864E1, US-E1-RE42864, USRE42864 E1, USRE42864E1|
|Inventors||Vladimir Tsukanov, Nathan Zommer|
|Original Assignee||Ixys Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Classifications (10), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to U.S. Provisional Patent Application No. 60/317,823, filed on Sep. 7, 2001, which is incorporated by reference herein for all purposes.
The present invention relates to power semiconductor devices.
Power metal oxide semiconductor (MOS) transistors and insulated gate bipolar transistors (IGBTs) can be grouped as either enhancement-mode or depletion-mode devices. Depletion-mode devices inherently include a pair of P/N junctions that form a parasitic bipolar transistor. Generally, it is preferable to prevent the parasitic transistor from being turned on during operation of the power devices, so that the switching speed of the device is not degraded. Also, if the parasitic transistor does turn on, the primary bipolar device may become latched in the on state that may result in destruction of the device.
As used herein, the term “power device” or “power semiconductor device” refers to the power MOS transistor, an IGBT, or other power switching devices.
Attempts have been made to minimize the likelihood of turning on the parasitic transistor. One method has been to short the source electrode of the MOS device to the body region of the device. This effectively shorts the base and emitter of the parasitic transistor together at the surface of the device. However, because of series resistance in the device body, other portions of the base and emitter are not shorted but have a relatively high impedance bridging the two elements. A highly doped region can be added to reduce the effective resistance of the bridging impedance. Another method has been to provide a resistive path between a source contact area and a channel section to provide a ballast voltage, e.g., U.S. Pat. No. 4,860,072, which is incorporated by reference herein for all purposes.
In one embodiment, a power semiconductor device includes a substrate having an upper surface and a lower surface. A source region of first conductivity is formed within a well region of second conductivity. The source region is provided proximate to the upper surface of the substrate. The well region has a non-polygon design. A gate electrode overlies the upper surface of the substrate. A drain electrode is provided proximate to the lower surface of the substrate.
In another embodiment, a power device includes a substrate having an upper surface and a lower surface. A plurality of cells are provided proximate to the upper surface of the substrate. The cells have non-polygon shapes and include source regions defining narrow electrical path within the cells. A drain electrode is provided proximate to the lower surface of the surface.
In yet another embodiment, a power semiconductor device includes a substrate having an upper surface and a lower surface. A source region of N conductivity is formed within a well region of P conductivity. The source region is provided proximate to the upper surface of the substrate and has a first circular path, a second circular path, and a connecting portion connecting the first and second circular paths. A gate electrode overlies the upper surface of the substrate. A drain electrode is provided proximate to the lower surface of the substrate. The connecting portion is configured to provided an increase resistance in the source region. The well region has substantially no linear dimension.
MOSFET 20 is fabricated from a silicon wafer which is heavily doped N+. A lightly doped N− expitaxial layer 24 is formed on the N+ substrate 22. A thin oxide layer is formed on which a silicon nitride layer is deposited and patterned to define the active area. Then, the gate oxide is formed on which polysilicon 34 is deposited and patterned to define the P well area. Then, using the polysilicon as a mask, a shallow and light P doping is performed by ion implantation, followed by a heavier and deeper P+ implant step. A single diffusion step is then performed to form regions 28 and 26, respectively. An oxide layer 32, having a central opening associated with each cell, functions as a diffusion mask for P diffusion 28. As shown in
Diffusion 28 is followed by an N+ diffusion 30 utilizing an oxide mask. Diffusion 30 also extends laterally under the oxide and polysilicon layer, but to a lesser extent than diffusion 28. Channel region 28a is formed under oxide layer 32, intermediate N+ region 30 and epitaxial N− layer 24. N+ region 30, which abuts the top surface of the wafer, forms the source region of the cell. A segment of P+ region 26 extends up through N+ region 30 to form a contact area for the body section of the cell. A source metallization 36 is formed over the exposed portion of the N+ source region 30 and P+ body region of each cell so as to provide a common source electrode. The highly doped silicon in combination with a metallization layer forms an ohmic (substantially non-rectifying) contact.
The polysilicon functions as a gate 34 and is positioned over channel region 28a and is insulated from the channel region by oxide layer 32. Gate electrode 34 extends over the surface of the device so as to form a common gate electrode for all cells 46 of the device. A metallization layer 38 is formed on the back of the die to form a drain electrode common to each cell 46 of the device.
When a positive potential is applied to the gate electrode 34, with respect to source electrode 36, electrons in body region 28 are attracted to the gate electrode. The excess electrons cause the channel region 28a immediately below the gate electrode to invert from P to N type conductivity, thereby forming an electrical path between the source and drain. When the gate potential is removed, the inversion layer disappears and section 28a is no longer conductive.
If current through resistor R1 is sufficiently large to forward bias the emitter/base junction of transistor 60 (about 0.7 volts), transistor 60 will turn on. This may occur because of current coupled to resistor R1 by way of the effective drain region 24 to body region 26/28 junction capacitance. If parasitic transistor 60 is permitted to turn on while MOS transistor 56 is conducting, the relatively slow turn-off time of the bipolar device would degrade the operation of the MOS device. In some instances, the MOS device may even be destroyed.
Power MOS device 100 is formed on an N+ substrate 102 on which an N− layer 104 is provided, e.g., by epitaxial growth. Alternatively, a MOS device may be formed on an N+ substrate that does not have an N− layer thereon. Referring back to MOS device 100, a P well region 106 is formed within N− layer 104. The P well region includes a P+ region 108 formed at a relatively deeper region and a P− region 110 formed at a relatively shallower region. An N+ well region or source region 112 (denoted as a left portion 112a, a center portion 112b, and right portion 112c) is formed within the P well region. Although the source region appears as three discrete regions in
A source electrode 114 is formed over an upper surface of the substrate and contacts center portion 112b of the source region and a portion of P well region 106. A gate electrode 116, generally of polysilicon, is provided at the periphery of P well region 106 overlying the upper surface of the substrate. The gate electrode is electrically isolated from the substrate and P well region by a lower oxide layer 118 and from the source electrode by an upper oxide layer 120. A channel region 122 is provided in the P well region below the gate electrode, so that an electrical path may be formed therein when a sufficient voltage is applied to the gate electrode. A drain electrode 124 is provided at a lower surface of the substrate.
The substrate is annealed to drive or diffuse the dopants in the P− and P+ regions. The dopants are driven vertically and horizontally in the N− layer; i.e., P well region 222 expands outwardly. As a result, a portion of the P well region extends underneath the gate electrode 212 to form a channel region, e.g., channel region 122 in
In the present embodiment, P+ regions 220 are provided to reduce the effective base resistance of the parasitic transistor to prevent it from being turned on during the operation of the MOS device. In one embodiment, the dopants from the P+ regions penetrate the MOS channel region to increase the threshold voltage of the device. A MOS device having a higher threshold voltage has higher noise immunity in power electronic circuits since it would require noise having higher energy to trigger the device on.
In one embodiment, the portion of P well region 222 that has not been converted to the N type is positioned substantially at the center of each circular lobe 226. A blocking mask, e.g., a patterned oxide layer 230, is used to block the N dopants from being implanted at the central areas of the circular lobes 226 and 228. The N+ well region, accordingly, is provided with two circular electrical path that is coupled at a connecting region 232 corresponding to center portion 112b of the source region 112 in
A source electrode (not shown) makes a contact 234 with the source region or N+ well region at the connecting region 232 and portions of the P well region (
In addition, a significant series resistance RN+ is provided between nodes 304 and 306. This resistance is formed in the N+ source region 112. The narrow current paths 236 and 238 and the narrow connecting region 240 contributes to the increased resistance of RN+. The current path from the contact 234 and the channel regions at the tips of the source regions are extended by the P well region provided at the central area of the circular lobes of the source region. Current flow through resistance RN+ is in the form of negative (electron) carriers and is represented accordingly by I−.
The electron flow I− through resistance RN+ creates a voltage drop which opposes the drop across resistance R2 and thus tends to reverse bias diode D1 thereby causing the parasitic transistor to remain turned off. Without resistance RN+, the diode D1 is more likely to be forward biased and then turn on the parasitic transistor, thereby degrading the operation of the MOS device.
As a result, the depth of the N+ or source region varies as one moves from the center of P+ region 402 to a channel region 406. The N+ region at a first end 408 and a second end 410 have different depth. The first end 408 proximate to the center of P+ region 402 is shallower than the second end remote from the center of P+ region 402. The shallower, first end has relatively higher sheet resistance then the deeper, second end 410, thereby creating an added degree of ballasting effect for increased device ruggedness. In other words, the varying depths of the source region provides selectively higher resistance in a portion of the source region that are removed from the channel region. This configuration may be used to control the resistance in the N+ layer (or RN+ of
While the invention has been particularly illustrated and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in the form and details may be made therein without departing from the spirit or scope of the invention. Therefore, the scope of this invention should not be limited to the embodiments described above, and should instead be defined by the following claims.
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|U.S. Classification||257/341, 257/328, 257/329, 257/401|
|International Classification||H01L29/78, H01L29/06|
|Cooperative Classification||H01L29/7802, H01L29/0696|
|European Classification||H01L29/06D3B, H01L29/78B2|