|Publication number||USRE43001 E1|
|Application number||US 12/368,589|
|Publication date||Dec 6, 2011|
|Filing date||Feb 10, 2009|
|Priority date||Oct 11, 2002|
|Also published as||US7177621, US20040072552, USRE44415|
|Publication number||12368589, 368589, US RE43001 E1, US RE43001E1, US-E1-RE43001, USRE43001 E1, USRE43001E1|
|Inventors||Ji Man PARK, Yong-Sung Jeon, Hong-il Ju, Young-soo Park, Sung-Ik Jun, Kyo-ill Chung|
|Original Assignee||Electronics And Telecommunications Research Institute|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (1), Classifications (9)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the priority of Korean Patent Application No. 2002-62075 filed on Oct. 11, 2002 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a wireless communication medium which can sense and generate a radio frequency (RF) signal necessary for communicating with a card reader or a contactless communication system, processes an analog signal to generate power necessary for driving a radio frequency identification (RFID) system, and processes a digital signal between an analog signal processor and a central processing unit (CPU) based on a communication protocol specified in ISO 14443, and a method for operating the same.
2. Description of the Related Art
In a method of processing an analog signal of a conventional RFID system, a RF hardware signal processor is broken down by a high voltage from an antenna, and thus the conventional RFID system loses its functions. Thus, the conventional RFID system cannot be used as a contactless RFID system. Also, a circuit is complicated and a large device value is required in order to prevent the contactless RFID from losing its functions.
In the conventional RFID, only a circuit, which processes an analog signal, is constituted and connected to a CPU. In other words, the CPU carries out functions of a digital signal processor without the digital signal processor or a digital signal processor carries out limited functions. Thus, it takes much time for the CPU to process such a digital signal and the whole performance of the conventional RFID deteriorates.
In addition, the conventional RFID uses a circuit which modulates a signal being transmitted to generate a BPSK-modulated signal by applying a carrier frequency of 874 KHz to a flip-flop circuit. Here, glitch necessarily occurs in the BPSK-modulated signal.
Accordingly, the present invention provides a RFID system which generates signals for controlling the operation of the RFID system by an additional logic circuit so that the additional logic circuit along with a CPU reliably and rapidly performs a process of converting an analog signal to a digital signal, and a method for operating the RFID system.
According to an aspect of the invention, there is provided a wireless communication medium including an antenna, an analog signal processor, a digital signal processor, and a central processing unit & logic module. The antenna transmits and receives a signal to and from an external apparatus. The analog signal processor converts an analog signal received via the antenna to a digital signal, and converts a digital signal to be transmitted to the external apparatus to an analog signal and transmits the analog signal to the antenna. The digital signal processor receives the digital signal from the analog signal processor, demodulates the digital signal, detects data and signals informing the start and end of data, and generates a control signal for determining whether data is transmitted to the external apparatus and a control signal for perceiving the end of data, blocking the reception of data from the external apparatus after a predetermined period of time, modulating data, and determining whether modulated data is transmitted to the external apparatus. The central processing unit & logic module includes a storage device and logic circuits that process data received from and transmitted to the external apparatus.
According to another aspect of the present invention, there is provided a method of operating a wireless communication medium. An analog signal received from an external apparatus is converted to a digital signal and a digital signal to be transmitted to the external apparatus is converted to an analog signal. Modulation and demodulation is performed for the transmission and reception of data to and from the external apparatus and signals for controlling the operation of the wireless communication medium are generated based on transmitted and received data. Transmitted and received data is processed.
The above features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
Hereinafter, preferred embodiments of the present invention will now be described in detail with reference to the attached drawings.
The functions of basic components of a RFID according to the present invention will be described. First, an antenna 100 serves to transmit and receive data to and from an external apparatus (e.g., a card reader), which communicates with the RFID, using an RF signal. The antenna 100 receives the RF signal from the external apparatus and transmits the RF signal to an analog signal processor 110, which is connected to two nodes Ant+ and Ant− of the antenna 100. Detailed blocks and functions of the analog signal processor 110 will be described with reference to
Next, the power supply 210 will be described. The power supply 210 serves to output power necessary for the RFID from an alternating signal induced via the antenna 100. The power supply 210 includes a source circuit & overvoltage clamp 211, a regulator 213, and a reset 215. The source circuit & overvoltage clamp 211 is a smoothing circuit which is basically composed of PMOS or NMOS transistors. The source circuit & overvoltage clamp 211 extracts a direct signal from the alternating signal and prevents an overvoltage exceeding a predetermined reference value from being output. The regulator 213 regulates an irregular direct voltage generated by the source circuit & overvoltage clamp 211. The regulator 213 is composed of a dual reference voltage block and a differential unit.
The load modulator 220 will be described.
The clock generator 230 will be described.
The capacitor 240 does not affect the physical shape of the RFID in the manufacture of the RFID. The capacitor 240 can be used to supply a stable direct current to the CPU and logic elements which require a large amount of power. The capacitor 240 is connected between a power supply and ground when manufacturing cards or Capacitor Over Bitlines (COBs) of chips.
The digital signal processor 120 will be described.
The clock divider 720 receives clock signals of 13.56 MHz from the analog signal processor 110 and generates a 2-divided clock signal of 6.78 MHz, a 4-divided clock signal of 3.39 MHz, or an 8-divided clock signal of 1.695 MHz. Next, the clock divider 720 selects one of the divided clock signals by software and outputs the selected clock signal to the transmission and reception reference clock generator 710. The clock divider 720 inputs the 8-divided clock signal of 1.695 MHz to the modulator 730 so that a signal is BPSK-modulated using the 8-divided clock signal and is transmitted to an external apparatus.
The receiver 740 samples received signals from the analog signal processor 110 whenever a reception reference clock signal generated by the transmission reception reference clock generator 710 is logic “high”. The receiver 740 stores one of eight time samplings as a data value. Next, the receiver 740 perceives a start of frame (SOF) signal informing the start of a frame in a received signal, generates a SOF detection signal (shown in
The transmitter 750 receives the SOF signal and the EOF signal from the receiver 740 and generates a transmitter ready after TR0 and TR1 specified in ISO 14443 elapse to inform a CPU & logic module 130 of the ready of transmission. When the CPU & logic module 130 receives the transmitter ready, the CPU & logic module 130 gives an instruction for the transmitter 750 to transmit the SOF signal, the EOF signal, or data. The CPU & logic module 130 includes addresses defined for the SOF signal and the EOF signal. Thus, when the CPU & logic module 130 transmits the defined addresses of the SOF signal and the EOF signal to the transmitter 750, the transmitter 750 transmits one of the SOF signal and the EOF signal corresponding to the address defined by the CPU & logic module 130. When the CPU & logic module 130 transmits an address defined for data with a desired data value to the transmitter 750, the transmitter 750 converts data to a serial signal and transmits the serial signal to the modulator 730. Whenever the transmission reference clock signal generated by the transmission reception reference clock generator 710 is logic “high”, the transmitter 750 converts the SOF signal, the EOF signal, or data to a serial transmission signal and transmits the serial transmission signal by each 1 ctu to the modulator 730 according to the instruction from the CPU & logic module 130. The transmitter 750 generates a SOF transmission signal (shown in
The modulator 730 will be described.
The transmission reception reference clock generator 710 will be described with reference to
Accordingly, by operating or stopping four modules under specific conditions, power consumption of the RFID can be lowered. Also, although an unnecessary signal is transmitted to the receiver 740 due to changes in power during the operation of the transmitter 750, since the receiver 740 is reset, the RFID can stably operate.
As described above, in a wireless communication medium and a method for operating the wireless communication medium according to the present invention, circuits are simple and a small amount of power is consumed. Thus, an efficiency of processing a RF signal can be improved. In addition, an analog signal processing hardware module and a digital signal processing hardware module are used in semiconductor IP models, respectively. A RF signal processor of the present invention can be directly applied to an existing information communication terminal (a portable phone, a personal digital assistant (PDA), or the like) by simply changing hardware and programs in the existing information communication terminal. Furthermore, a large amount of power can be stably supplied to a CPU and logic elements block using an external capacitor.
The RFID can include an additional digital signal processor which perceives a serial signal received from the analog signal processor 100, converts the serial signal to data, transmits data to the CPU & logic module 130, converts data transmitted from the CPU & logic module 130 to a serial signal, BPSK-modulates the serial signal, transmits BPSK-modulated signal to the ananlog signal processor 100, and automatically generates a CRC value of data received and transmitted. Thus, the performance of the RFID can be improved and an error occurring when transmitting and receiving data can be reduced.
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|USRE44415 *||Oct 27, 2011||Aug 6, 2013||Electronics And Telecommunications Research Institute||Wireless communication medium and method for operating the same|
|U.S. Classification||455/337, 455/115.4, 375/329, 455/151.2|
|International Classification||G06K19/07, H04B1/16, H04B1/40|