|Publication number||USRE43081 E1|
|Application number||US 12/136,712|
|Publication date||Jan 10, 2012|
|Filing date||Jun 10, 2008|
|Priority date||Oct 1, 2003|
|Also published as||EP1521187A1, US7157935, US20050127943|
|Publication number||12136712, 136712, US RE43081 E1, US RE43081E1, US-E1-RE43081, USRE43081 E1, USRE43081E1|
|Inventors||Ashish Kumar Goel, Davinder Aggarwal|
|Original Assignee||Sicronic Remote Kg, Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Classifications (11), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application claims priority from Indian Application for Patent No. 1230/Del/2003 filed Oct. 1, 2003, the disclosure of which is hereby incorporated by reference.
1. Technical Field of the Invention
The present invention relates to Programmable Logic Devices (PLDs) and more particularly to a device and method for configuration of PLDs.
2. Description of Related Art
A typical field programmable gate array (FPGA) comprises an array of configuration memory cells, configuration control elements and a matrix of logic and I/O blocks. Different digital circuits can be realized on an FPGA by configuring its memory cell array and control elements.
An FPGA is typically configured as follows: a frame of data is loaded into the VSR 1.2. For a complete frame of data that is loaded in the VSR 1.2, the configuration state machine 1.5 and the selection register 1.3 enable a selection line for shifting the data column from VSR 1.2 to a particular column of the configuration memory latch array 1.1 and on completion of the shift operation the selection lines are disabled. The next frame of data is then loaded in the VSR 1.2 and the process of selecting and shifting is repeated until the entire latch array 1.1 is configured.
The configuration state machine 1.5 supports two types of configuration schemes. One is a normal configuration, in which the entire configuration latch array 1.1 matrix is loaded. The other scheme is the partial configuration scheme, in which only a part of configuration latch array 1.1 matrix needs to be reloaded. In order to support both schemes, the configuration state machine includes two registers namely count register 1.5.1 and the index register 1.5.2 as shown in
After the data has been written onto the latches 1.1, the value of counter register 1.3 1.5.1 is incremented and the value in the index register 1.4 1.5.2 is decremented. This process continues until the value stored in the index is zero. After completion of the configuration process the startup sequence is initiated.
As described above, the index register 1.5.1 1.5.2 stores the value of the columns of onfiguration latches 1.1 to be enabled. Thus in case of partial configuration the value stored in this register determines the number of columns to be reprogrammed.
Decoder 1.4 and a select register 1.3 are used for enabling the column of latches. The line to be enabled is the decoded output of count register 1.5.1. Since the number of column lines of configuration latches 1.1 is very high (of the order of 1000) the complexity of decoder 1.4 is very high, and the placement and routing of the decoder 1.4 is also complex. The area consumed in making such a large decoder 1.4 is also high.
A further problem associated with this technique is the difficulty in scalability. Any modification in the size of the array requires a change in the size of the decoder.
Thus, there is a need to develop a technique that provides a simple method of enabling the column of configuration latches and also reduces area, complexity and routing requirements of the decoder.
Embodiments of the present invention address the foregoing and other drawbacks of the prior art.
In accordance with an embodiment of the present invention, a simplified method and device are provided for configuring FPGAs. In accordance with this method and device, the decoder of configuration memories used in FPGAs is replaced with a horizontal shift register. This reduces the complexities associated with the decoder hence simplifying configuration process.
Accordingly, an embodiment of the present invention provides a Programmable Logic Device providing efficient scalability for configuration memory programming while requiring reduced area for implementation. The device comprises an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.
The Configuration State Machine comprises an index register that specifies the number of columns of the configuration array that are to be enabled, an increment register that contains the number of shifts required in the HSR prior to enabling the column, and a count address register that provides a count of the number of programmed columns.
The Horizontal Shift Register comprises a plurality of flip-flops connected in series to form a serial shift register with a common clock signal and initialization signal that sets the first flip-flop and clears the remaining flip-flops at the start of the configuration process.
An embodiment of the present invention also provides a method for providing efficient scalability with minimum area overhead in configuring the configuration memory of a Programmable Logic Device (PLD). The method comprises shifting in the configuration data of a particular column of the configuration memory, selecting said particular column by shifting a selection bit to its enable signal bus, enabling the selected column to load the configuration data, and repeating the foregoing process steps for each desired column of the configuration memory.
In accordance with an embodiment of the invention, a device includes a configurable memory latch array and a vertical shift register supplying configuration data to rows of the array. The device further includes a circuit for moving the configuration data from the vertical shift register to one selected column of the array for storage, the circuit operating without the use of a horizontal decoding circuit. More specifically, in an embodiment of the present invention, the circuit uses a horizontal shift register in place of a horizontal decoding circuit to make column selections.
A more complete understanding of the method and apparatus of the present invention may be acquired by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:
The function of the registers VSR 3.2, select register 3.3, index register 3.5.2 and the count address register 3.5.1 are similar to the corresponding registers 1.2, 1.3, 1.5.2, and 1.5.1 of
The index 3.5.2 and increment 3.5.2 registers are loaded before the configuration starts. In case of partial configuration, the registers are loaded for each set of regular frames that are to be configured.
There are two sets of registers which control the enabling of the select line of the configuration latches—namely the HSR (Horizontal Shift Register) and the select register. The HSR has one set bit corresponding to the column of configuration latch matrix which has to be enabled. The column is finally enabled by the enabling of the select register, by the configuration state machine.
This arrangement provides a simple and flexible design of the HSR that is easily scalable since the size of the memory array can be easily enhanced by adding or removing a register from the HSR.
In the first step 5.1 the configuration is started and then the configuration mode is checked. For the case of normal configuration 5.2 the entire memory is cleared 5.3 and the index and increment registers are loaded 5.4 whereas for the partial mode configuration directly the index and increment registers are loaded. In the next step 5.5 it is checked if the increment register is zero, for the case when the increment register is not zero the HSR is shifted by the increment register count and address register is incremented by the increment register count 5.6. Once the VSR is full 5.7, if increment generated was zero then the select enable signal pulse is generated 5.7 and clock signal clock_HSR is initiated 5.8 and index and increment count address register are decremented 5.9. If index register is not zero 5.10 at this stage then steps 5.7 to 5.10 are repeated otherwise, if the count address register is maximum then steps 5.4 to 5.10 are repeated or the configuration is signaled as complete.
Normal configuration: for normal configuration mode the index register value is always equal to the column count in the configuration matrix and the value for increment register is always zero. Thus the configuration starts from the first column and proceeds until the last Column where both conditions of “index and count address register” become true.
Partial configuration: in the case of partial configuration the values of index and increment register will vary the column sets are defined by “start value” (increment) and columns to be enabled from “start value (index)”. After each set of configuration columns is loaded, the value in count address register is checked for maximum value. If the maximum value has not been reached another set of configuration data may require to be loaded. Once the count address register reaches maximum value the start up is initiated.
This invention is not to be considered limited to the specific examples chosen for purposes of disclosure, but rather to cover all changes and modifications, which do not constitute departures from the permissible scope of the present invention. The invention is therefore not limited by the description contained herein or by the drawings, but only by the claims.
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|U.S. Classification||326/39, 326/40, 326/46|
|International Classification||G06F17/50, H03K19/177|
|Cooperative Classification||G06F17/5054, H03K19/1776, H03K19/17748|
|European Classification||G06F17/50D4, H03K19/177H, H03K19/177H3|
|Apr 12, 2011||AS||Assignment|
Owner name: SICRONIC REMOTE KG, LLC, DELAWARE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS, N.V.;REEL/FRAME:026111/0774
Effective date: 20071228
|Jul 3, 2012||CC||Certificate of correction|
|Jun 24, 2014||FPAY||Fee payment|
Year of fee payment: 8
|Nov 2, 2015||AS||Assignment|
Owner name: MINERAL LASSEN LLC, NEVADA
Free format text: MERGER;ASSIGNOR:SICRONIC REMOTE KG, LLC;REEL/FRAME:036940/0693
Effective date: 20150811