|Publication number||USRE43201 E1|
|Application number||US 12/056,927|
|Publication date||Feb 21, 2012|
|Filing date||Mar 27, 2008|
|Priority date||Mar 30, 2003|
|Also published as||US7019573, US20040239389, USRE44029|
|Publication number||056927, 12056927, US RE43201 E1, US RE43201E1, US-E1-RE43201, USRE43201 E1, USRE43201E1|
|Original Assignee||Canon Kabushiki Kaisha|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Classifications (15)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 7,019,573 B2. The reissue applications are application Ser. Nos. 12/056,927 (the present application) and 12/814,680 (which is a divisional reissue of U.S. Pat. No. 7,019,573 B2).
1. Field of the Invention
The present invention relates to a DLL (Delay-Locked Loop) circuit used for a polyphase clock generating circuit, a multiply circuit, and the like, particularly to a technique preventing a pseudo lock state which is not normally locked.
2. Related Background Art
The pseudo lock state may be one of the most serious malfunctions of the DLL circuit.
In the conventional technique, as described in U.S. Pat. No. 6,259,290, there is a method in which the pseudo lock state is detected in such a manner that a plurality of pulses are generated within the 1 period of a reference clock by the multiply circuit to count the number of pulses.
However, in the method described in U.S. Pat. No. 6,259,290, such a circuit as the multiply circuit, the counter, and the like is required, and there is a drawback which results in a cost increase and an electrical power consumption increase because the circuit is enlarged.
It is an object of the invention to provide the low-cost DLL circuit which detects the pseudo lock state with a small-scale circuit and has high accuracy and high reliability.
The DLL circuit of the invention includes a delay stage to which a reference clock is input and in which delay elements being able to change an amount of delay are connected in a plurality of stages, phase-comparison means for comparing a phase of said reference clock to the phase of one of delay signals extracted from said delay stage, controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase comparing means, and state transition means for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state and for controlling said controlling means to transit the state to the normal lock state.
Since, in the normal lock state, an output signal of the delay element on a subsequent state side is always delayed in a delay relationship in the delay stage in which the plurality of variable delay elements are connected, according to the present invention, based on detection of a phase relationship between the output signals of the delay elements, it is prevented to fall into the pseudo lock state.
Depending on a type of the DLL circuit, the pseudo lock state never occurs in the case where the amount of delay is small, so that the controlling means is controlled so that the delay element becomes the minimum delay state in starting up the DLL circuit and the abnormal state can be detected in the transition state in which the normal lock state is disengaged to fall into the pseudo lock state.
Preferred embodiments of the invention will be described referring to the accompanying drawings.
A +1 period pseudo lock state of a 1 period phase-comparison type DLL circuit will be described referring to
The startup clear circuit (SUC) 18 is one which detects the state, such as power-up or a power saving mode of the DLL circuit, in which circuit operation transits from an OFF state to an ON state, and this operation allows the variable delay element D to be set to the minimum delay state in starting the DLL circuit.
Accordingly, in the DLL circuit of the embodiment, since a delay control loop is operated from the minimum state of the delay, it is difficult to transit to the pseudo lock state having the large delay. However, even in the case where the normal lock state is disengaged, the pseudo lock state can be detected by detecting the phase relationship within the delay stage with DFF.
Similarly to the example of the first embodiment shown in
In the above-described pseudo lock state, the delay stage formed by the 50-stage delay element was described as the example. However, in the actual operation, since a reverse state of the phase relationship is certainly generated in the delay stage until the normal lock state transits to the pseudo lock state, the optimum two points in the delay stage may be selected by the number of delay stages and loop gain.
The reversal of the phase relationship of the delay signal can be also generated between the delay signals of the delay elements adjacent to each other. For example, in the case where the delay stage is formed by the 4-stage delay element, the phase relationship is reversed within the 1 period between delay signals T1 and T2 output from the delay elements adjacent to each other as shown in
Further, in the above embodiments, although the reversal of the phase relationship is decided by the relationship between the outputs of the 25th stage and the 9th stage, the reversal of the phase relationship can be also decided by the relationship between the outputs of the 25th stage and the stage after the 9th stage.
Therefore, even if the reference clock CLK input to the DLL circuit or the duty of the variable delay element D is not in the ideal state, the transition to the pseudo lock state can be prevented. The control is not limited to the startup clear circuit, and the circuit having the same effect as the startup clear circuit may be used.
Thus, it will be appreciated that at least one more pseudo lock detection circuit may be provided in order to improve a detection rate.
An example of an indicator concerning selection of the delay output used for the detection of the pseudo lock will be described below.
As described above, in the DLL circuit, the pseudo lock state for the desired period exists in +1 period unit. When the unlock state is in the +½ period state compared to the normal lock state, it is not clear whether the unlocked state transits to the normal lock state or to the pseudo lock state. Therefore, for the delay output for detecting the pseudo lock state, in the ½ period phase-comparison type, when the amount of delay becomes larger than the ½ period, i.e., double the desired amount of delay, the two outputs of the delay stage in which the phase relationship is reversed are selected. For example, in the case where the delay stage is formed in 50 stages, the selection of the two delay outputs before the 50/2 step is preferable for the detection on the pseudo lock side.
Further, in the state in which the amount of delay triples the desired amount of delay, the outputs in which the delay relationship is reversed are selected so that the pseudo lock is securely detected in +1 period. In the delay output of the subsequent, stage, because the absolute change in the amount of delay is larger, the output stage having the amount of delay which does not exceed the 1 period of the reference clock even in the +1 period pseudo lock is used as a guide in one of the outputs of the delay stage. If feasible, in the +2 period pseudo lock, the amount of delay may be also within the 1 period of the reference clock. For example, in the case of the DLL circuit having the 50 stages, the output before the 50/2 stage is used for one of the delay outputs and the output before the 50/3 stage is used for the other delay output, or the output before the 50/5 stage is used for the other delay output in order to satisfy the secure detection in the +2 period pseudo lock. In the case of the 1 period phase-comparison type, the output before the 50/1.5 stage is used for one of the delay outputs in order not to securely decide the pseudo lock state before the 1.5 periods, and the amount of delay becomes larger than double the desired amount of delay, i.e., the output before the 50/2 stage may be selected for the other delay output in order to detect the +1 period pseudo lock, or the output before the 50/3 stage may be selected for the other delay output in order to detect the +2 period pseudo lock.
In the examples of the 50-stage DLL circuit shown in the first and second embodiments, the outputs of the 25th stage and the 9th stage are used as the delay output and the delay signal completely satisfying the above-described conditions is used.
In the case where the detection is performed on the basis of the above conditions in the ½ period phase-comparison DLL circuit having 40-stage configuration,
Even if these conditions are completely satisfied, since the delay relationship is always reversed in the process of the transition to the pseudo lock, the detection can be performed by selecting the delay outputs on the assumption that the amount of delay becomes larger than the ½ period to the desired amount of delay. Alternatively, the plurality of detection circuits such as the combination detecting the +1 period pseudo lock state, the combination detecting the +2 period pseudo lock state, and the combination detecting the +3 period pseudo lock state can be provided to improve the detection rate.
Although the output of the delay element input to the data input terminal of the DFF corresponds to the output of the delay element input to the phase comparator in the above embodiment, it is not always necessary that the output of the delay element input to the data input terminal of the DFF corresponds to the output of the delay element input to the phase comparator, and it will be appreciated that the output of the delay element input to the data input terminal of the DFF and the output of the delay element input to the phase comparator are output from the individual variable delay element.
As described above, in the second and third embodiments, the transition to the pseudo lock can be prevented in such a manner that the flip-flop circuit DFF and the startup clear circuit SUC are added to the DLL basic circuit, the delay is started from the minimum state, and the before-and after before-and-after phase relationship in the delay stage is detected. When the power saving mode signal exists, the power saving can be achieved only by the flip-flop circuit with setting function, so that a low-cost, high-reliability DLL circuit can be provided. Further, in the first to third embodiments, since it is not necessary to change the delay stage and the input reference clock, excessive delay is never generated and the DLL circuit can be implemented with high accuracy.
One example of the cases in which the DLL circuit of the invention is applied to a camcorder will be described in detail below referring to
The numeral 22 designates an iris, the numeral 23 designates a solid-state image sensing device which photoelectrically converts a subject image imaged on an imaging area into an electric imaging signal, and the numeral 24 designates a sample hold circuit (S/H circuit). The S/H circuit 24 performs sample hold of the imaging signal output from the solid-state image sensing device, amplifies the level of the imaging signal, and outputs a video signal.
The numeral 25 designates a process circuit which performs predetermined processing such as gamma correction, color separation, and blanking to the video signal output from the sample hold circuit 24 and outputs a luminance signal Y and a chroma signal C. In a color signal correction circuit 31, the corrections of white balance and color balance are performed to the chroma signal C output from the process circuit 25, and the chroma signal C after the corrections is output as color difference signals R-Y and B-Y. The luminance signal Y output from the process circuit 25 and the color difference signals R-Y and B-Y output from the color signal correction circuit 31 are modulated by an encoder circuit (ENC circuit) 34 and output as a standard television signal. Then, the standard television signal is supplied to a video recorder (not shown) or a monitor EVF such as an electronic view finder (not shown).
The numeral 26 designates an iris control circuit which controls an iris drive circuit 27 on the basis of the video signal supplied from the S/H circuit 24 and automatically controls an ig meter in order to control a numerical aperture of the iris 22 so that the level of the video signal becomes a predetermined value having a certain level. The numerals 33 and 34 designate a band-pass filter (BPF) which extracts a high-frequency component required to detect a focal point in the video signal output from the sample hold circuit 24, and the band-pass filters 33 and 34 restrict a different band. The signals output from the first band-pass filter (BPF1) 33 and the second band-pass filter (BPF2) 34 are gated by a focus gate frame signal in a gate circuit 35, respectively, peak values of the signals are detected and held by a peak detecting circuit 36, and the signals are input to a logical control circuit 37.
The signals are referred to as focal voltage, and the focusing is performed by the focal voltage.
The numeral 38 designates a focus encoder which detects a moved position of the focus lens 21A, the numeral 39 designates a zoom encoder which detects a focal distance of the zoom lens 21B, and the numeral 40 designates an iris encoder which detects the numerical aperture of the iris 22. The detection values of these encoders are supplied to the logical control circuit 37.
The logical control circuit 37 detects and adjusts the focal point to the subject on the basis of the video signal corresponding to an area set to detection of the focal point. Namely, the logical control circuit 37 takes in information on the peak values of the high-frequency components supplied from the band-pass filters 33 and 34, and supplies control signals such as a rotational direction, rotational speed, rotation and stop of a focus motor 30 to the focus drive circuit 29 and controls the control signals in order to drive the focus lens 21A to the position where the peak value of the high-frequency component becomes the maximum.
The DLL circuit of the invention is provided in a timing generator (TG) 50 and used so as to drive the photoelectric conversion device 23 and to finely adjust drive timing of the S/H circuit 24 and the like.
As described above, according to the invention, the transition to the pseudo lock can be prevented. Further, since the delay can be started from the minimum state by providing the means for controlling the amount of delay so as to minimize the amount of delay during the startup of the DLL circuit in power-up and the power saving mode, the transition to the pseudo lock state becomes more difficult.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6119242 *||May 25, 1999||Sep 12, 2000||Micron Technology, Inc.||Synchronous clock generator including a false lock detector|
|US6239634 *||Jan 10, 2000||May 29, 2001||Parthus Technologies||Apparatus and method for ensuring the correct start-up and locking of a delay locked loop|
|US6259290||Jun 15, 1999||Jul 10, 2001||Kabushiki Kaisha Toshiba||Delay locked loop having a mis-lock detecting circuit|
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|JP2004350116A||Title not available|
|U.S. Classification||327/161, 327/158|
|International Classification||H04N5/225, H03L7/00, H03L7/095, H03L7/081, H03L7/06, H04N5/232|
|Cooperative Classification||H03L2207/14, H03L7/0812, H04N5/23212, H04N5/335|
|European Classification||H04N5/232F, H03L7/081A, H04N5/335|