|Publication number||USRE43215 E1|
|Application number||US 11/598,154|
|Publication date||Feb 28, 2012|
|Filing date||Nov 9, 2006|
|Priority date||Feb 2, 2001|
|Also published as||US6815775, US20020149059|
|Publication number||11598154, 598154, US RE43215 E1, US RE43215E1, US-E1-RE43215, USRE43215 E1, USRE43215E1|
|Inventors||Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang|
|Original Assignee||Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (51), Referenced by (3), Classifications (12), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention is directed generally to electrostatic discharge (ESD) protection circuits for input/output (I/O) devices, and more particularly, to improving ESD robustness in I/O cell libraries using novel layout techniques to implement a turn-on retraining arrangement that reduces the turn-on speed or increases the breakdown voltage of a MOS transistor.
2. Description of the Related Art
The ESD robustness of CMOS integrated circuits (IC) has been found to be seriously degraded due to deep-submicron CMOS technologies. To improve the ESD robustness of the output transistors, the ESD-implant process and the silicide-blocking process have been widely implemented in the deep-submicron CMOS technologies. In addition to the process modification to improve the ESD robustness of the output buffers, the symmetrical layout structure had been emphasized to realize the large-dimension output transistors by ensuring the uniform turn-on phenomenon along the multiple fingers of the output transistor. To further enhance the uniform turn-on phenomenon among the multiple fingers of the output transistors, a gate-coupling design had been reported to achieve uniform ESD power distribution on large-dimension output transistors.
General circuit diagrams of the output cell, input cell, and I/O bidirectional cell in a cell library are shown in FIGS. 1(a)-(c), respectively. In a general application, the output buffers in a cell library have different driving specifications. For instance, the output buffers in a typical library may have the different driving capabilities of e.g., 2 mA, 4 mA, 8 mA, or 24 mA. To meet these different types of current specification, different numbers of fingers in the MOS device of the cell are provided to drive current to, or sink current from, the pad. An example of the finger numbers of the different I/O cells in a 0.35-μm cell library used to provide the driving/sinking current are shown in TABLE 1.
Wherein W/L=35 μm/0.5 μm for each finger, and the xp (xn) is the number of fingers in the output PMOS (NMOS) layout, which are used to generate the output current to the pad.
However, the cell layouts of the output buffers with different driving capabilities are all drawn in the same layout style and area for programmable application. To adjust different output sinking (driving) currents of the output buffer, different number of fingers of the poly gates in the output NMOS (PMOS) are connected to the ground (VDD). The general layout of the NMOS device in the output cell with the used and unused fingers is shown in
Due to the asymmetrical connection on the poly-gate fingers of the output NMOS in the layout, the ESD turn-on phenomenon among the fingers becomes quite different even if the layout is still symmetrical. When such an I/O cell with a small output current driving ability is stressed by ESD, the used NMOS Mn1 is often turned on first due to the transient coupled voltage on its gate. As seen in
The human body model (HBM) ESD level of an I/O cell library with different driving current specification but the same layout area and layout style is shown in TABLE 2.
The test data for two worst cases of ESD-testing pin combinations under the PS-mode ESD test and ND-mode ESD test are listed in Table 2 for the I/O cells with different output current specifications. According to the data of Table 2, it is concluded that when the output cell has a higher output current driving ability, the ESD level is also higher. However, the I/O cell with an output current of 2 mA only has an ESD level of 1 kV, even if the total (Mn1+Mn2) device dimension in every cell is the same. To verify the location of ESD damage on the I/O cell with a smaller output current, the ESD-stressed IC was de-layered to find the failure location.
The failure locations were found to locate at the Mn1 device of the I/O cell. However, the Mn2 in the same I/O cell was not damaged by the ESD stress. The detailed analysis on this failure issue is described in the paper by H. -H. Chang, M. -D. Ker and J. -C. Wu, “Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology,” Solid-State Electronics, vol. 43, pp. 375-393, February 1999. This creates a challenge to provide one set of I/O cells with better ESD level. Typically, the HBM ESD level of every I/O cell should be greater than 2 kV under any ESD-testing pin combination.
To improve ESD level of the I/O cells with different output current driving abilities, the descriptions of the gate-coupled technologies had been reported in publications by, e.g., C. Duvvury and R. N. Rountree, “Output buffer with improved ESD protection,” U.S. Pat. No. 4,855,620 (August, 1989); C.-D. Lien, “Electrostatic discharge protection circuit,” U.S. Pat. No. 5,086,365 (February, 1992) M.-D. Ker, C.-Y Wu, T. Cheng, C.-N. Wu, and T.-L. Yu, “Capacitor-couple ESD protection circuit for submicron CMOS IC,” U.S. Pat. No. 5,631,793 (May, 1997); and H.-H. Chang, M.-D. Ker, K. T. Lee, and W.-H. Huang, “Output ESD protection using dynamic-floating-gate arrangement,” U.S. Pat. No. 6,034,552 (March, 2000).
One of such gate-coupled designs is shown in
Another gate-coupled design to enhance the turn-on of Mn2 and Mp2 is shown in FIG. 4 (U.S. Pat. No. 5,086,365). In
A more complex design, called as the dynamic-floating-gate technique, was also disclosed to improve ESD level of the I/O cells, which is shown in
The manufacturing process solutions had been also invented for improving the ESD level of such I/O cells. To enhance the turn-on of Mn2, the process method with the additional ESD implantation is also provided to reduce the junction breakdown voltage of the Mn2 device, such as those disclosed in publications by, e.g., C.-C. Hsue and J. Ko, “Method for ESD protection improvement,” U.S. Pat. No. 5,374,565, December 1994; T. A. Lowrey and R. W Chance, “Static discharge circuit having low breakdown voltage bipolar clamp,” U.S. Pat. No. 5,581,104, December 1996; and K.-Z. Chang and C.-Y Lin, “Method of making ESD protection device structure for low supply voltage applications,” U.S. Pat. No. 5,674,761, October 1997.
The NMOS device structure, equivalent circuit, and layout with the additional ESD-implantation method for I/O cells are shown in FIGS. 6(a)-(c), respectively. In
When the CMOS technology scaled down to sub-half-micron, the voltage level of VDD in the chip is also reduced to a lower voltage level. Because the I/O signals come from external circuits of chips in a system may have different voltage levels, the high-voltage-tolerant I/O circuits are designed and used in such an interface condition. A typical 3V/5V-tolerant I/O circuit was described in M. Pelgrom and E. Dijkmans, “A 3/5V compatible I/O buffer,” in IEEE Journal of Solid-State Circuits, vol. 30, no.7, pp. 823-825, July 1995; and W. Anderson and D. Krakaauer, “ESD protection for mixed-voltage I/O using NMOS transistors staked in a cascade configuration,” in Proc. Of EOS/ESD Symp., 1998, pp. 54-62.
The design methodology as taught from the above-discussed prior art is focused exclusively on the unused Mn2 in the I/O cell. Although such design methodology can improve the ESD level of the I/O library, it is costly and requires additional elements to realize the gate-coupled circuit or modifications to lower the junction breakdown voltage.
It is an object of the present invention to provide a semiconductor structure for ESD protection of an integrated circuit in order to improve ESD level of the I/O cells with different driving specifications.
Another object of the present invention is to provide a semiconductor structure for improving ESD robustness of the output ESD protection NMOS/PMOS through an additional pick-up diffusion region and/or modification of channel length.
A further object of the present invention is to provide a semiconductor structure for improving ESD robustness of the input ESD protection NMOS/PMOS.
A still further object of the present invention is to provide a semiconductor structure to improve ESD robustness of the I/O cells by using different channel lengths in the I/O devices.
In accordance with the present invention, a semiconductor structure for electrostatic discharge (ESD) protection of a metal-oxide semiconductor (MOS) integrated circuit consists of a p-type substrate forming a base for the semiconductor structure, a first n-type channel formed between first N+ regions within the substrate for an Mn1 transistor, and a second n-type channel formed between second N+ regions within the substrate for an Mn2 transistor. In particular, an additional P+ pick-up diffusion region is disposed adjacent to the first N+ regions to reduce the turn-on speed of the first MOS transistor. Alternatively or in addition to the P+ pick-up diffusion region, the channel lengths of the first and second n-typ channels can be varied such that the channel length of the first n-type channel is larger than the channel length of the second n-type channel to increase the drain breakdown voltage of the first MOS transistor.
In accordance with another aspect of the present invention, the semiconductor structure is used to protect an internal circuit, output buffer, I/O buffer, input cell, or 3V/5V-tolerant I/O cell library of the MOS integrated circuit by slowing down the turn-on speed or increasing the break-down voltage of the output device with small driving current ability, such that the ESD-protection device with a large device dimension can be triggered on to bypass ESD current during an ESD stress event. Related aspects and advantages of the invention will become apparent and more readily appreciated from the following detailed description of the invention, taken in conjunction with the accompanying drawings.
FIGS. 1(a)-(c) are schematic circuit block diagrams showing conventional circuit function and device dimension of I/O cells;
The present invention will now be described by way of preferred embodiments with references to the accompanying drawings. Like numerals refer to corresponding parts of various drawings.
Referring now to
The operation of the present invention as shown in FIGS. 7(a)-(c) is more fully discussed hereinafter. The drain of Mn1 finger is filly surrounded by the P+ pick-up diffusion 70 (base guard ring). Therefore, the parasitic BJT in the Mn1 device 72 has a smaller equivalent base resistance (Rsub1) in the P-well/P-substrate, because the distance from the base region (under the Mn1 channel region) to the grounded P+ pick-up diffusion 70 is shortest in the layout structure. The drain of Mn2 fingers are drawn without such additional pick-up diffusion region 70, and therefore the parasitic BJT in the Mn2 device 74 has a larger base resistance (Rsub2). When a positive ESD voltage is attached to the output pad as shown in
To achieve this effect, the layout structure of the present invention incorporates the additional pick-up diffusion 70 (base guard ring) around the used Mn1 device 72, but not around the unused Mn2 device 74. The triggering on the Mn1 device 72 into a snapback region is restrained or delayed by the additional pick-up diffusion 70, and this allows enough time for the Mn2 device 74 with a relatively larger device dimension to be triggered on to discharge ESD current. If the PMOS has a small Mp1 driving device and a larger unused Mp2 device in the I/O cell layout, the output PMOS device of the present invention can also carried out by means of pulling up device between VDD and the output pad 78.
As shown in FIGS. 8(a)-(c), another way to limit the turn-on speed of the Mn1 device 72 is to change the channel length of Mn1 device 72 and Mn2 device 74 in the I/O cell. For instance, the 0.25-μm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) with a fixed channel width of 300 μm and afixed drain-contact-to-polygate spacing (DGS) of 1.5 μm can produce a NMOS device with a channel length (L) of 0.3 μm or 1.0 μm. The breakdown I-V curves of NMOS devices with different channel lengths have been measured in that the NMOS device with 0.3 μm channel length has a breakdown voltage (Vt1) of 9V and a snapback holding voltage (Vh) of 5V, while the NMOS device with 1.0 μm channel length has a breakdown voltage (Vt1) of 9.7V and a snapback holding voltage (Vh) of 6.1V. The NMOS devices with different channel lengths have different breakdown voltages and snapback holding voltages. The dependence of the breakdown voltages and snapback holding voltages on the NMOS channel length are such that an NMOS device with a shorter channel length has a lower breakdown voltage (Vt1) and a lower snapback holding voltage (Vh), which means that it can be turned on faster than the NMOS device having a longer channel length. From this perspective, the Mn1 72 and Mn2 74 devices in the I/O cell layout with different channel lengths can be drawn to restrain the turn-on of the Mn1 device 72. The unused Mn2 device 74 with larger device dimension (channel width) is therefore drawn with a shorter channel length in the layout.
As shown in
Additionally, in the semiconductor structure as shown in FIG. 8(a)-(c), the Mn2 device 74 with L2<L1 is triggered to enter its snapback region and discharge ESD current before the Mn1 device 72 is triggered on. As a result, the turn-on speed of the Mn1 device 72 is restrained according to different channel lengths in the layout structure.
One of the preferred embodiments with different channel lengths on the Mn1 device has been used in an in-house 0.5 μm bi-directional I/O cell B001H which has a smaller output current driving ability of only 1 mA. The layout view of NMOS part in the I/O cell of this 1-mA cell is shown in
The present invention can be also applied to improve the ESD level of the pure input cell, which has multiple fingers placed in parallel in the layout. The typical input cell used in the I/O cell library is shown in
Although the fingers in the NMOS layout of
The non-uniform turn-on behavior in
To compensate for the base resistance effect, the additional pick-up diffusion regions 122 in
When the CMOS technology scaled down to sub-half-micron regime, the voltage level of VDD in the chip is also reduced to a lower voltage level, such as 3.3V, 2.5V, or 1.8V for core circuits. However, the I/O signal come from external circuits of chips in a system may have different voltage levels, which may be greater than VDD of the chip. Therefore, the high-voltage-tolerant I/O circuits are designed and used in such an interface condition. A typical 3V/5V-tolerant I/O circuit is shown in
Although a specific form of the present invention has been described above and illustrated in the accompanying drawings in order to be more clearly understood, the above description is made by way of example and not as a limitation to the scope of the present invention. It is believed that various modifications apparent to one of ordinary skill in the art could be made without departing from the scope of the present invention which is to be determined by the following claims.
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|U.S. Classification||257/355, 257/357, 257/362, 257/356, 257/360, 257/E23.111, 257/E23.105|
|International Classification||H01L27/02, H01L23/62|
|Cooperative Classification||H01L27/0277, H01L2924/0002|
|Mar 4, 2007||AS||Assignment|
Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TAIWAN
Effective date: 20010105
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KER, MING-DOU;PENG, JENG-JIE;JIANG, HSIN-CHIN;REEL/FRAME:018955/0717
|Mar 27, 2007||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE;REEL/FRAME:019073/0121
Owner name: TRANSPACIFIC IP LTD., TAIWAN
Effective date: 20060610
|Mar 23, 2012||FPAY||Fee payment|
Year of fee payment: 8
|Sep 18, 2012||CC||Certificate of correction|