US RE43231 E1 Abstract Disclosed is aA system and method for joint source-channel encoding, symbol decoding and error correction, preferably utilizing an arithmetic encoder with operational error detection space; and a combination sequential, and arithmetic, encoded symbol decoder structure.
Claims(58) 1. A variable length symbol, joint source-channel encoding, symbol decoding and error correction system comprising:
encoder system;
modulation-transmission means; and
combination sequential, and encoded symbol, decoding systems;
said encoder system comprising input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto;
said encoder system being functionally interconnected to said modulation-transmission means such that entry of a symbol to said encoder system results in said encoder means outputting an encoded sequence of bits therefore into said modulation-transmission means;
said modulation-transmission means and combination sequential, and encoded symbol, decoding systems being functionally interconnected such that an encoded symbol sequence of bits entered to said modulation-transmission means enters said combination sequential, and encoded symbol, decoding systems;
said sequential decoding system comprising a plurality of bistable elements;
said encoded symbol decoding system comprising means for initiating an error correction routine to the end that, upon the detecting of the presence of an unexpected encoded reserved symbol a selection from the group consisting of:
at least one bistable element in said sequential decoding means is changed; and
selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means;
is performed;
wherein said reserved symbol is not allowed as an input symbol to said symbol encoder system input means, and wherein the detection of the presence of an encoded allowed symbol by said encoded symbol decoding system does not initiate said error correction routine.
2. A variable length symbol joint source-channel encoding, symbol decoding and error correction system comprising:
encoder means;
modulation-transmission means; and
combination sequential, and encoded symbol, decoding means;
said encoder means comprising input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto;
said encoder means further having means for generating, and in a sequence expected by said encoded symbol decoding means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said encoder means input means;
said encoder means being functionally interconnected to said modulation-transmission means such that entry of a symbol to said encoder means results in said encoder means outputting an encoded sequence of bits therefore into said modulation-transmission means;
said modulation-transmission means and combination sequential, and encoded symbol, decoding means being functionally interconnected such that an encoded symbol sequence of bits entered to said modulation-transmission means enters said encoded symbol decoding means;
said sequential decoding means comprising a plurality of bistable elements;
said encoded symbol decoding means comprising means for initiating an error correction routine to the end that, upon the detecting of the presence of an unexpected encoded reserved symbol, or the absence of an expected encoded sequence of bits for a reserved symbol, a selection from the group consisting of:
at least one bistable element in said sequential decoding
means is changed; and
selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means;
is performed;
and wherein the detection of the presence of an encoded allowed symbol, other than by its coincidental presence in the place of an absent expected reserved symbol, by said encoded symbol decoding means, does not initiate said error correction routine.
3. A joint source-channel encoding, symbol decoding and error correction system comprising:
encoder means;
modulation-transmission means; and
decoding means;
wherein said encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto;
wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an encoded symbol decoder means;
said encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means;
such that in use said encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof, said sequence of bits being caused to arrive at said decoding means;
and said encoded symbol decoder means having error detection means such that in use said encoded symbol decoder means, upon detecting the presence of an unexpected encoded sequence of bits for reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
at least one bistable element in said sequential encodingdecoder means is changed; and
selection is made of a series of sequential bits, said selection being made from a group consisting of aplurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means;
is performed;
wherein said reserved symbol is not allowed as an input symbol to said encoder means input means, and wherein the detecting of the presence of an encoded allowed symbol by said decoding means does not initiate said error correction routine.
4. A joint source-channel encoding, symbol decoding and error correction system as in
5. A joint source-channel encoding, symbol decoding and error correction system comprising:
encoder means;
modulation-transmission means; and
decoding means;
wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an encoded symbol decoder means;
wherein said encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said encoder means further having means for generating and, in a sequence expected by said encoded symbol decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said encoder means input means;
said encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means;
such that in use said encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with a sequence of bits which represent at least one encoded reserved symbol in a pattern expected by said decoder means, said sequence of bits being caused to arrive at said decoding means;
and said encoded symbol decoder means having error detection means such that in use said encoded symbol decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
at least one bistable element in said sequential decoding means is changed; and
selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means;
is performed;
and wherein the detection of the presence of an encoded allowed symbol, other than by its coincidental presence in the place of an absent expected reserved symbol, by said decoding means, does not initiate said error correction routine.
6. A joint source-channel encoding, symbol decoding and error correction system as in
7. A joint source-channel encoding, symbol decoding and error correction system comprising:
arithmetic encoder system;
modulation-transmission means; and
decoding system;
wherein said arithmetic encoder system comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input therein to;
wherein said decoding system comprises a functional combination of a sequential decoder system which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder system;
said arithmetic encoder system being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding system;
such that in use said arithmetic encoder system receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof, said sequence of bits being caused to arrive at said decoding system;
and said arithmetic decoder system having error detection means such that in use said arithmetic decoder system, upon detecting the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group, consisting of:
at least one bistable element in said sequential encoding meansdecoder system is changed; and
selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder meansdecoder system;
is performed;
wherein said reserved symbol is not allowed as an input symbol to said arithmetic encoder system input means, and wherein the detecting of the presence of an encoded allowed symbol by said decoding system does not initiate said error correction routine.
8. A joint source-channel encoding, symbol decoding and error correction system comprising:
arithmetic encoder means;
modulation-transmission means; an
decoding means;
wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means;
wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said arithmetic encoder means further having means for generating and, in a sequence expected by said arithmetic decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means;
said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means;
such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with at least one encoded reserved symbol in a pattern expected by said arithmetic decoder means, said sequence of bits being caused to arrive at said decoding means;
and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
at least one bistable element in said sequential decoding means is changed; and
selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means;
is performed;
and wherein the detection of the presence of an encoded allowed symbol, other than by its coincidental presence in the place of an absent expected reserved symbol, by said decoding means, does not initiate said error correction routine.
9. A method of correcting errors in decoded symbols which are encoded by an encoder means in a joint source-channel coding system, comprising the steps of:
a. providing a joint source-channel encoding, symbol decoding and error correction system comprising:
encoder means;
modulation-transmission means; and
decoding means;
wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an encoded symbol decoder means;
wherein said encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said encoder means further having means for generating and, in a sequence expected by said encoded symbol decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said encoder means input means;
said encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means;
such that in use said encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof, in optional combination with at least one encoded reserved symbol in a pattern expected by said decoder means, said sequence of bits being caused to arrive at said decoding means;
and said encoded symbol decoder means having error detection means such that in use said encoded symbol decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
at least one bistable element in said sequential decoding means is changed; and
selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means;
is performed;
wherein the detection of the presence of an encoded allowed symbol, other than by its coincidental presence in th place of an absent expected reserved symbol, by said decoding means, does not initiate said error correction routine;
b. inputting a plurality of symbols to the input means of said encoder means;
c. causing said encoder means to encode at least some of said plurality of symbols and output bits corresponding thereto into said modulation-transmission means;
d. causing said modulation-transmission means to enter said at least some of said plurality of encoded symbols into said functional combination of said sequential decoder means and encoded symbol decoder means;
e. causing said encoded symbol decoder means to, if detecting a present unexpected or absent expected, encoded reserved symbol, perform a selection from the group consisting of:
change at least one bistable element in said sequential decoder means; and
select a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means.
10. A method as in
11. A method of correcting errors in decoded symbols which are encoded by an arithmetic encoder in a joint source-channel coding system, comprising the steps of:
a. providing a joint source-channel encoding, symbol decoding and error correction system comprising:
arithmetic encoder means;
modulation-transmission means; and
decoding means;
wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto;
wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means;
said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means;
such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof, said sequence of bits being caused to arrive at said decoding means;
and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
at least one bistable element in said sequential decoding means is changed; and
selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means;
is performed;
wherein said reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means, and wherein the detection of the presence of an allowed encoded symbol by said decoding means does not initiate said error correction routine;
b. inputting a plurality of symbols to the input means of said arithmetic encoder means;
c. causing said arithmetic encoder means to encode at least some of said plurality of symbols and output bits corresponding thereto into said modulation-transmission means;
d. causing said modulation-transmission means to enter said at least some of said plurality of encoded symbols into said functional combination of said sequential decoder means and arithmetic decoder means;
e. causing said arithmetic decoder means to, if detecting a present unexpected encoded reserved symbol perform a selection from the group consisting of:
change at least one bistable element in said sequential decoder means; and
select a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means.
12. A method as in
13. A method of correcting errors in decoded symbols which are encoded by an arithmetic encoder in a joint source-channel coding system, comprising the steps of:
a. providing a joint source-channel encoding, symbol decoding and error correction system comprising:
arithmetic encoder means;
modulation-transmission means; and
decoding means;
wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means;
wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said arithmetic encoder means further having means for generating and, in a sequence expected by said arithmetic decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an allowed input symbol, which reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means;
said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means;
such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with at least one encoded reserved symbol in a pattern expected by said arithmetic decoder means, said sequence of bits being caused to arrive at said decoding means;
and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
at least one bistable element in said sequential decoding means is changed; and
selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means;
is performed;
wherein said reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means and wherein the detection of the presence of an allowed symbol, other than by its coincidental presence in the place of an absent expected encoded reserved symbol, by said decoding means, does not initiate said error correction routine;
b. inputting a plurality of symbols to the input means of said arithmetic encoder means;
c. causing said arithmetic encoder means to encode at least some of said plurality of symbols and output bits corresponding thereto, optionally intermingled with arithmetic at least one encoder means generated reserved symbol, into said modulation-transmission means;
d. causing said modulation-transmission means to enter said at least some of said plurality of encoded symbols, optionally along with at least one encoded reserved symbol entered into said modulation-transmission means, into said functional combination of said sequential decoder means and arithmetic decoder means;
e. causing said arithmetic decoder means to, if detecting a non-present expected or present unexpected encoded reserved symbol, perform a selection from the group consisting of:
change at least one bistable element in said sequential decoder means; and
select a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means.
14. A method as in
15. A method of correcting errors in decoded symbols which are encoded by an arithmetic encoder in a joint source-channel coding system, comprises the steps of:
a. providing a joint source-channel encoding, symbol decoding and error correction, system comprising:
arithmetic encoder means;
modulation-transmission means; and
decoding means;
wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means;
wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said arithmetic encoder means further having means for generating and, in a sequence expected by said arithmetic decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means;
said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means;
such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with at least one encoded reserved symbol in a pattern expected by said arithmetic decoder means, said sequence of bits being caused to arrive at said decoding means;
and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that at least one bistable element in said sequential decoder means is changed;
b. entering a sequence of symbols into said arithmetic encoder such that said sequence of symbols are encoded and exited therefrom as a binary bit stream sequence of +x √{square root over (E_{8})} and −x √{square root over (E_{8})} signals, corresponding to a string of “1”/(“0”)'s and “0”/(“1”)'s which pass through said transmission channel and enter said sequential decoder means, where x is a fraction;
c. making hard logic circuitry decisions as to the presence of “1”/(“0”)'s and “0”/(“1”)'s based on said binary bit stream sequence of +x√{square root over (E_{s})} and −x√{square root over (E_{s})} signals while identify decisions based upon signals wherein x is of a value so as to cause the values of +x√{square root over (E_{s})} or −x√{square root over (E_{s})} to be within a null zone of +Δ to −Δ around 0,0, and identifying said decisions as “branch point”, decisions in said sequential decoder means;
d. monitoring output from said arithmetic decoder for errors and whenif an error is indicated thereby, identifying a “branch point” in said sequential decoder means and correcting the “1”/(“0”) or “0”/(“1”) based binary bit thereat by inverting it to “0”/(“1”) or “1”/(“0”).
16. A method of correcting errors in decoded symbols as in
17. A method of correcting errors in decoded symbols as in
e. defining a tolerable Hamming distance threshold Tc, and keeping count of the number Kc of “branch points” in said sequential decoder means at which correction of the “1”/(“0”) or “0”/(“1”) based binary bit thereat by inverting to “0”/(“1”) or “1”/(“0”) has been performed; and
if Kc exceeds Tc, expanding the null zone by increasing the magnitude of Δ, thereby making available additional “branch points”.
18. A method of correcting errors in decoded symbols as in
f. determining in a second or greater practice of step e. if the identified “branch point” is sequentially prior to the “branch point” identified in the immediately previous practice of step e. and if so decreasing the value of Kc by 1, otherwise increasing the value of Kc by 1.
19. A method of correcting errors in decoded symbols as in
e. defining a means for calculating a Euclidean distance between received and decoded symbols, and a tolerable rate of increase of Euclidean distance between sequential practice of step d., and
if said Euclidean distance increases faster than at said tolerable rate, expanding the null zone by increasing he magnitude of Δ, thereby making available additional “branch points”.
20. A method of correcting errors in decoded symbols which are encoded by an arithmetic encoder in a joint source-channel coding system, comprises the step of:
a. providing a joint source-channel encoding, symbol decoding and error correction system comprising:
arithmetic encoder means;
modulation-transmission means; and
deocding means;
wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means;
specific bistable elements in said sequential decoder means being identified as fixed branch points;
wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said arithmetic encoder means further having means for generating and, in a sequence expected by said arithmetic decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means;
said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means;
such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with at least one encoded reserved symbol in a pattern expected by said arithmetic decoder means, said sequence of bits being caused to arrive at said decoding means;
and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that:
selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means at said specified branch points;
is performed;
b. entering a sequence of symbols into said arithmetic encoder means such that said sequence of symbols are encoded and exited therefrom as a binary bit stream sequence;
c. monitoring output from said arithmetic decoder means for errors;
d. upon detection of an error by said arithmetic decoder means, producing a plurality of series of sequential bits which result from the changing of bistable elements in said sequential decoder means at said branch points by using fixed branch point bistable elements in said sequential decoder means;
e. determining which series of sequential bits in said produced plurality of series of sequential bits is most likely correct utilizing at least one selection from the group consisting of:
1. eliminating any series of sequential bits which contains an encoded reserved symbol;
2. applying a metric to at least two series of sequential bits which do not contain an encoded reserved symbol, to determine which of said at least two series of sequential bits is most likely correct;
3. applying an Euclidean metric to at least two series of sequential bits which do not contain an encoded reserved symbol, to determine which of said at least two series of sequential bits is most likely correct.
21. A system, comprising:
a decoder, comprising an arithmetic decoder and a sequential decoder, configured to receive data from an arithmetic encoder via a channel, wherein the arithmetic decoder, upon detecting an absence of an expected encoded reserved symbol or a presence of an unexpected encoded reserved symbol, is configured to initiate an error correction routine, wherein the arithmetic decoder is configured to not initiate the error correction routine upon detection of an allowed symbol in the received data, and wherein the sequential decoder is configured to, upon initiation of the error correction routine by the arithmetic decoder, change at least one bistable element in the sequential decoder or select a series of sequential bits from a plurality of series of sequential bits which result from the changing of bistable elements in the sequential decoder. 22. The system of claim 21, further comprising:
the arithmetic encoder configured to receive input data; and a modulator located between the arithmetic encoder and the channel. 23. The system of claim 21, wherein the decoder is configured for use in a communication system.
24. The system of claim 23, wherein the communication system is configured to use Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), or Trellis Coded Modulation (TCM).
25. A method, comprising:
receiving data from an encoder via a channel at a decoder, the decoder comprising an arithmetic decoder and a sequential decoder; and producing output data using the decoder, wherein the arithmetic decoder, upon detecting an absence of an expected encoded reserved symbol or a presence of an unexpected encoded reserved symbol, initiates an error correction routine, wherein the arithmetic decoder does not initiate the error correction routine upon detection of an allowed symbol in the received data, and wherein the sequential decoder, upon initiation of the error correction routine by the arithmetic decoder, changes at least one bistable element in the sequential decoder or selects a series of sequential bits from a plurality of series of sequential bits which result from the changing of bistable elements in the sequential decoder. 26. The method of claim 25, further comprising:
receiving coded data from the encoder at a modulator, which outputs modulated data to the channel. 27. The method of claim 25, wherein the received data is a signal corresponding to a binary bit stream sequence of “1”/(“0”)'s and “0”/(“1”)'s.
28. The method of claim 27, wherein the producing output data further comprises making hard logic circuitry decisions as to a presence of the “1”/(“0”)'s and “0”/(“1”)'s based on the signal.
29. The method of claim 28, wherein the producing output data further comprises using the sequential decoder to monitor output from the arithmetic decoder for errors.
30. The method of claim 29, wherein the producing output data further comprises:
identifying a branch point if the signal has a value located within a null zone; and correcting the “1”/(“0”) or “0”/(“1”) binary bit by inverting it to “0”/(“1”) or “1”/(“0”) respectively, at the sequential decoder if an output from the arithmetic decoder indicates an error. 31. The method of claim 30, wherein the identifying a branch point and the correcting the “1”/(“0”) or “0”/(“1”) binary bit is performed more than once.
32. The method of claim 31, wherein the producing output data further comprises determining a number of branch points at which correction of the “1”/(“0”) or “0”/(“1”) binary bit has been performed (Kc).
33. The method of claim 32, wherein the producing output data further comprises:
decreasing a value of Kc by 1 if a subsequent branch point is sequentially prior to a first branch point; and increasing the value of Kc by 1 if the subsequent branch point is not sequentially prior to the first branch point. 34. The method of claim 32, further comprising:
determining a Hamming distance threshold (Tc); and expanding the null zone to increase a number of branch points, if the number of branch points at which correction has been performed (Kc) exceeds the Hamming distance threshold (Tc). 35. The method of claim 31, wherein the producing the output data further comprises:
determining a Euclidean distance between the received data and the output data; and expanding the null zone to increase a number of branch points, if the Euclidean distance for subsequent calculations increases faster than a defined rate. 36. The method of claim 25, wherein the producing the output data further comprises:
selecting a series of sequential bits in the sequential decoder by,
eliminating any series of sequential bits which contains an encoded reserved symbol;
applying a metric to at least two series of sequential bits which do not contain an encoded reserved symbol and determining which series is most likely correct; or
applying an Euclidean metric to at least two series of sequential bits which do not contain an encoded reserved symbol and determining which series is most likely correct.
37. The method of claim 25, further comprising using the decoder in a communication system.
38. The method of claim 37, further comprising using Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), or Trellis Coded Modulation (TCM) in the communication system.
39. A system, comprising:
a decoder, comprising an encoded symbol decoder and a sequential decoder, configured to receive data from an arithmetic encoder via a channel, wherein the encoded symbol decoder, upon detecting an absence of an expected encoded reserved symbol or a presence of an unexpected encoded reserved symbol, is configured to initiate an error correction routine, wherein the encoded symbol decoder is configured to not initiate the error correction routine upon detection of an allowed symbol in the received data, and wherein the sequential decoder is configured to, upon initiation of the error correction routine by the encoded symbol decoder, change at least one bistable element in the sequential decoder or select a series of sequential bits from a plurality of series of sequential bits which result from the changing of bistable elements in the sequential decoder. 40. The system of claim 39, wherein the encoded symbol decoder is an arithmetic decoder.
41. The system of claim 39, further comprising:
the arithmetic encoder configured to receive input data; and a modulator located between the encoder and the channel. 42. The system of claim 39, wherein the decoder is configured for use in a communication system.
43. The system of claim 39, wherein the communication system is configured to use Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), or Trellis Coded Modulation (TCM).
44. A method, comprising:
receiving data from an encoder via a channel at a decoder, comprising an encoded symbol decoder and a sequential decoder; and producing output data using the decoder, wherein the encoded symbol decoder, upon detecting an absence of an expected encoded reserved symbol or a presence of an unexpected encoded reserved symbol, initiates an error correction routine, wherein the encoded symbol decoder does not initiate the error correction routine upon detection of an allowed symbol in the received data, and wherein the sequential decoder, upon initiation of the error correction routine by the encoded symbol decoder, changes at least one bistable element in the sequential decoder or selects a series of sequential bits from a plurality of series of sequential bits which result from the changing of bistable elements in the sequential decoder. 45. The method of claim 44, further comprising:
receiving the data from the encoder via a modulator, which outputs data to the channel. 46. The method of claim 44, further comprising using an arithmetic encoder as the encoder and an arithmetic decoder as the encoded symbol decoder.
47. The method of claim 44, further comprising using a signal corresponding to a binary bit stream sequence of “1”/(“0”)'s and “0”/(“1”)'s as the received data.
48. The method of claim 47, wherein the producing output data further comprises making hard logic circuitry decisions as to a presence of the “1”/(“0”)'s and “0”/(“1”)'s based on the signal.
49. The method of claim 48, wherein the producing output data further comprises using the sequential decoder to monitor output from the encoded symbol decoder for errors.
50. The method of claim 49, wherein the producing output data further comprises:
identifying a branch point if the signal has a value located within a null zone; and correcting the “1”/(“0”) or “0”/(“1”) binary bit by inverting it to “0”/(“1”) or “1”/(“0”) respectively, in the sequential decoder if an output from the encoded symbol decoder indicates an error. 51. The method of claim 50, wherein the identifying a branch point and the correcting the “1”/(“0”) or “0”/(“1”) binary bit is performed more than once.
52. The method of claim 51, wherein the producing output data further comprises determining a number of branch points at which correction of the “1”/(“0”) or “0”/(“1”) binary bit has been performed (Kc).
53. The method of claim 52, wherein the producing output data further comprises:
decreasing a value of Kc by 1 if a subsequent branch point is sequentially prior to a first branch point; and increasing the value of Kc by 1 if the subsequent branch point is not sequentially prior to the first branch point. 54. The method of claim 52, further comprising:
determining a Hamming distance threshold (Tc); and expanding the null zone to increase a number of branch points, if the number of branch points at which correction has been performed (Kc) exceeds the Hamming distance threshold (Tc). 55. The method of claim 51, wherein the producing output data further comprises:
determining a Euclidean distance between the received data and the output data; and expanding the null zone to increase a number of branch points, if the Euclidean distance for subsequent calculations increases faster than a defined rate. 56. The method of claim 51, wherein the producing the output data further comprises:
selecting a series of sequential bits in the sequential decoder by,
eliminating any series of sequential bits which contains an encoded reserved symbol;
applying a metric to at least two series of sequential bits which do not contain an encoded reserved symbol and determining which series is most likely correct; or
applying an Euclidean metric to at least two series of sequential bits which do not contain an encoded reserved symbol and determining which series is most likely correct.
57. The method of claim 44, further comprising using the decoder in a communication system.
58. The method of claim 57, further comprising using Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), or Trellis Coded Modulation (TCM) in the communication system.
Description This Application is a CIPThis is a reissue application of U.S. Pat. No. 6,892,343 B2 issued May 10, 2005, U.S. Pat. No. 6,892,343 B2 issued from U.S. application Ser. No. 09/816,398 filed Mar. 24, 2001, which claims the benefit under 35 U.SC. §119(e) of provisional application Ser. No. 60/192,215 filed on Mar. 27, 2000. The present invention relates to source symbol encoding, decoding and error correction capability in the context of noisy channels in electronic communication systems. More particularly the prefered present invention is a system and method for joint source-channel encoding and variable length symbol decoding with error correction, comprising arithmetic encoder and combination sequential and arithmetic encoded symbol, decoder means. BACKGROUND With the increasing popularity of mobile communications there has come renewed interest in joint source-channel coding. The reason is that shared mobile communications channels are restrictive in terms of bandwidth and suffer from such as fading and interference etc., thus making some form of error protection essential, particularly where variable length codes are used. Further, it is well known that standard approaches to error correction are expensive, in terms of required bandwidth, hence there exists a need for systems and methodology which can provide efficient source and channel encoding and symbol decoding with error correction. Viable candidates include a joint source-channel encoding system and methodology which utilizes characteristics of a source, or source encoder, to provide error protection. As background, it is noted that one of the earliest works that examined the effect of errors on variable length codes was that of Maxted and Robinson in an article titled “Error Recovery for Variable Length Codes”, IEEE Trans. on Information Theory, IT-31, p. 794-801, (November 1985). Corrections and additions to said work were provided by Monaco and Lawlor in “Error Recovery for Variable Length Codes”, IEEE Trans. on Information Theory, IT-33, p. 454-456, (May 1987). And said work was later extended by Soualhi et al. in “Simplified Expression for the Expected Error Span Recovery for Variable Length Codes”, Intl. J. of Electronics, 75, p. 811-816, (November 1989), and by Rahman et al. in “Effects of a Binary Symetric Channel on the Synchronization Recovery of Variable length Codes”, Computer J., 32, p. 246-251, (January 1989); as well as by Takishima et al. in “Error States and Synchronization Recovery for Variable Length Codes”, IEEE Trans. on Communications, 42, p. 783-792; as well as by Swaszek et al. in “More on the Error Recovery for Variable Length Codes”, IEEE Trans. on Information Theory, IT-41, p. 2064-2071, (November 1995)., all of which focused mainly on the resynchronization ability of Huffman Codes. In terms of joint source channel coding where the source and source encoder characteristics are used to provide error protection, one of the earliest works which incorporated variable length codes was that of Sayood, Liu and Gibson in “Implementation Issues in MAP Joint Source/Channel Coding”, Proc. 22nd Annular Asilomar Conf. on Circuits, Systems, and Computers, p. 102-106, IEEE, (November 1988). Assuming a Markov model for the source encoder output they used packetization to prevent error propagation and the residual redundancy at the source encoder output to provide error protection. This approach is used by Park and Miller who have developed a bit constrained decoder specifically for use with variable codes, (see “Decoding Entropy-Coded Symbols Over Noisy Channels by MAP Sequency Estimation for Asynchronous HMMs”, Proc. Conference on Information Sciences and Systems, IEEE, (March 1999). Murad and Fuja, in “Robust Transmissions of Variable-Length Encoded Sources”, Proc. IEEE Wireless and Networking Conf. 1999, (September 1999); and Sayood, Otu and Demir in “Joint Source/Channel Coding for Variable Length Codes”, IEEE Transactions on Communications, 48:787-794, (May 2000), describe designs which make use of the redundancy at the source coder output for error correction. The problem of low bandwidth hostile channels can also be addressed using error resilent source codes which incorporate the possibility of errors in the channel and provide mechanisms for error concealment. Work in the area includes that of Yang. et al. as reported in “Robust Image Compression Based on Self-Synchronizing Huffman Code and Inter-Subband Dependency”, Proc. thirty-second Asilomar Conference on Signals, Systems and Computers, p. 986-972 (November 1997), who use the self-synchronizing property of suffix rich Huffman codes to limit error propagation, and correlation between subbands to provide error correction/concealment. In addition, there exist a number of concatenated schemes in which the source and channel encoders are concatenated in the traditional manner with channel resources allocated between them based on the characteristics of the channel. If the channel is very noisy, more bits are allocated to the channel and fewer to source encoding, and the situation is reversed when the channel conditions are more favorable. Examples of this approach include the work of Regunathan et al. as presented in an article titled “Robust Image Compression for Time Varying Channels”, Proc. Thirty-first Asilomar Conf. on Signals, Systems and Computers, p. 968-972, (November 1997) and in an article titled “Progressive Image Coding for Noisy Channels”, by Sherwood et al., IEEE Signal Processing Lett., 4 p. 189-191, (July 1997). Most of the schemes referenced above use Huffman coding or variants thereof as the variable length coding scheme, however, with the increasing popularity of arithmetic coding, there has developed interest in joint source channel coding schemes which use said arithmetic coding. One such approach is described in “Arithmetic Coding Algorithm with Embedded Channel Coding”, ElMasry, Electronics Lett., 33 p. 1687-1688, (September 1997); and another is described in “Integrating Error Detection into Arithmetic Coding”, Boyd et al., IEEE Transactions on Communications, 45(1), p. 1-3, (January 1997). The ElMasry approach involves generation of parity bits which are embedded into arithmetic coding procedure for error correction. The Boyd approach showed that by reserving probability space for a symbol which is not in the source alphabet the arithmetic code can be used for detecting errors. Reserving probability space for a symbol that will never be generated means that less space remains for the source alphabet and this translates into a higher coding rate. Said overhead, however, is small considering the capability of error detection enabled, as described by Kozintsev et al. in “Image Transmission Using Arithmetic Coding Based on Continuous Error Detection”, Proc. of Data Compression Conf. p. 339-348, IEEE Computer Society Press, (1998) regarding two scenarios, (eg. Automatic Repeat Request (ARQ) based communications and serially concatenated coding schemes with an inner error correction code and an outer error detection code), which use error detecting capability of the arithmetic code with an error detection space. With an eye to the present invention a Key-word Search for relevant Patents which involve inner and outer coding, trellis coding, data compression, error detection, error correction, variable length coding, arithmetic coding, and data transmission over noisy channels, has provided:
No known reference or combination of references, however, discloses use of a joint source-channel encoding, symbol decoding and error correction system comprising encoder means, modulation-transmission means, and combination sequential, and encoded symbol, decoding means; wherein errors detected by the encoded symbol decoding means are corrected by methodlogy involving the changing of bistable elements in said sequential decoder means, or selection of a series of sequential bits from a plurality of said serieses of sequential bits which result from changing bistable elements in said sequential decoder means, particularly where said encoder means is an arithmetic encoder and encoded symbol decoding means comprises arithmetic decoder, and encoded symbols are of variable length. The present invention can be characterized as a system and method involving a concatenated scheme in which the functional roles of both:
The present invention system can be described as a variable symbol length, joint source-channel encoding, symbol decoding and error correction system comprising:
Said encoder means can optionally further comprise means for generating, and in a sequence expected by said encoded symbol decoding means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded
Continuing, where the encoder means and encoded symbol decoder means are arithmetic, the present invention joint source-channel encoding, decoding and error correction system can be described as comprising:
Where the encoder means and encoded symbol decoder means are arithmetic, the present invention joint source-channel encoding, decoding and error correction system can be more precisely described as comprising:
A method of practicing the present invention, assuming the presence of an arithmetic encoder and arithmetic encoded symbol decoding system, can be recited as:
It is noted that the arithmetic encoder means and decoding means, which comprises a sequential decoder means and an arithmetic decoder means, can be any electronic systems which perform the indicated function. It is felt beneficial to provide insight to a specific error correction procedure which can be performed by the present invention. Again, a present invention joint source-channel encoding system can be considered to be sequentially comprised of:
A method of correcting errors in decoded symbols which are encoded by an arithmetic encoder in joint source-channel coding system, comprises the steps of:
Said method of error correction can involve step d. being practiced more than once, with said error correcting method further comprising the step of:
Further, said error correction method can further comprise the step of:
Alternatively, said error correcting method can involve practice of step d. more than once, with said error correcting method further comprising the step of:
Again, the error detection method, in step d., involves the determination of the presence or absence of non-alphabet, (ie. reserved), symbols other than as expected, said non-alphabet symbols being not-allowed as arithmetic encoder input symbols. The just described approach to correcting errors requires that “branch-points” in the sequential decoder means be determined based upon a “null-zone” criteria, and involves retracking the contents of the sequential decoder means, and selectively changing an identified “1”/(“0”) to “0”/(“1”), when an error is identified. It is possible, however, to identify bistable elements in said sequential decoder means and define them as fixed branch points, based upon the modulation technique utilized. For instance, if a trellis coded modulation scheme is utilized, a well known 8-PSK Constellation Codeword Assignment approach can be practiced. When such an approach to correcting errors in decoded symbols which are encoded by an arithmetic encoder in joint source-channel coding system is utilized, the method thereof can be described as comprising the steps of:
Said method of correcting errors in decoded symbols can, in step e., involve determining which series of sequential bits in said produced plurality of series of sequential bits is most likely correct based on applying at least on selection from the group consisting of:
Finally, it is specifically noted that, while not limiting, it is believed that Patentability is definitely established where the present invention system is comprised of an arithmetic encoder means, in combination with a decoding means which is comprised of a functional combination of a sequential decoder means and an arithmetic decoder means, wherein in use, error correction methodology is initiated upon the detecting, by the arithmetic decoder means, of a non-expected encoded reserved symbol, or the absence of an expected encoded reserved symbol sequentially inserted with encoded allowed symbols by the arithmetic encoder means. It is also noted that no arithmetic encoder means is known which provides operational error detection space. Computer simulation thereof, and of sequential and arithmetic decoder means then serve as example systems. The present invention will be better understood by reference to the Detailed Description Section in combination with the Drawings. It is therefore a primary purpose and/or objective of the present invention to provide a system comprising an outer symbol encoder means which comprises operational error detection space, and a combination sequential, and encoded symbol, decoding means, wherein said outer encoder means is preferably an arithmetic encoder, and the encoded symbol, decoding means is preferably an arithmetic decoder. It is another purpose of the present invention to disclose use of reserved symbols as means to enable encoded symbol, decoding means, (arithmetic decoder), to identify errors, said identified errors being corrected by the changing of at least one bit is an associated sequential decoder means. It is another purpose yet of the present invention to teach that error detection by an arithmetic decoder means can be based on detecting the presence of an unexpected encoded symbol or on detecting the absence of an expected encoded symbol. It is yet another purpose of the present invention to disclose methods of enhancing the operation of the sequential decoder means in correcting of errors involving distance calculations, (eg. Hamming and Euclidean distances). It is a further purpose of the present invention to identify use of “null-zones”, or use of modulation technique determined specific “branch points” in a sequence of bistable elements in a sequential detector means. Other purposes and/or objectives will become obvious from a reading of the Specification and Claims. Turning now to the Drawings, there is shown in In use then the Arithmetic Encoder sends a binary stream of bits (x_{k}) into the Modulation-Transmission means (2), in some mapped form, (eg. mapped to +/−√{square root over (Es)} for BPSK signaling). (Note: BPSK stands for Binary Phase Shift Keying). In the traditional sequential decoding scenario the structure of the convolution code imposes a restriction on possible decoded sequences and, hence, on possible branch points along a path. By discarding branches in which an error has been detected, the decoding tree can be pruned such that what is left is the decoded sequence with the lowest Hamming Distance from the received sequence. The structure of the convolution code then defines the valid paths in the tree. The job of the Decoder is then primarily to find the valid path that results in a decoded sequence with the minimum distance from the received sequence. Where Arithmetic Encoders are utilized, the situation is not as simple. To apply sequential decoding procedures to the case wherein an Arithmetic Encoder is utilized, two considerations become important:
The first requirement is easily satisfied if use is made of error detection space in the Arithmetic Encoder, and in fact, it is noted that it is satisfied in a stronger manner than where convolution encoding is utilized. That is, in the Arithmetic Encoding case in which use is made of error detection space, the appearance of a symbol corresponding to the error detection space is a definite indication of error. The second requirement is not as easily satisfied. This is because unlike in the convolution encoder case, the output of the arithmetic encoder is not restricted in terms of bit patterns which it can output, hence, an associated tree would have each bit as a branch point and the tree grows exponentially with the number of bits in a sequence. Thus it becomes necessary to identify specific branch points which are most-likely to be the location of error, and to arrive at a more rational code tree. Present invention methodology makes use of information available at the output of the Modulation-Transmission means (2), (ie. a Channel), to obtain what are the most likely error branch points. Assuming binary BSPK signalling and an additive white Gaussian noise channel, the signal space can be represented as shown in The number of possible paths can be represented as a fully connected binary Trellis, such as shown in 3. The heavy lines in the To aide with understanding, suppose that at point “X” in As a specific example, consider that the output of an Arithmetic Encoder is transmitted using a binary signalling scheme with √{square root over (E_{s=1})}. Further consider that said output is transmitted over a Modulation-Transmission means (2), (ie. a Channel), which corrupts it with additive noise such that the output of a signal receiver would provide:
where denotes the explored branch point and the * denotes unexplored branch points. In order to capture an error it is sufficient that Δ be greater than the magnitude of the error. It would seem then that selecting a large value for Δ is desirable, however, as already mentioned, such an approach leads to proliferation of branches in a resulting Tree. Further, it is known that small magnitude errors are more likely than are large magnitude errors, and as a result large values of Δ typically do not provide significant benefit. Also, it is noted that the probability of an error being within the last “n” symbols is:
It is noted that in an arithmetic decoder an error will almost always propagate. However, the use of detection space essentially guarantees that any error will eventually be detected. The “Depth First” algorithm allows correction of the errors by exploring branches of a code tree, but said approach can become computationally expensive. It is, however, possible to prune a code tree in order to reduce the number of computations. Several constraints can be used to accomplish said pruning the code tree, and the inventors herein have made use of the fact that making incorrect “corrections” causes increased deviation from a correct path. Detection of proceeding along an incorrect path can be accomplished by, for instance, keeping track of Hamming distance, and/or keeping track of a Squared distance in the Euclidean sense. Regarding the Hamming distance approach, keeping continuous track of the number of corrections still extant is key, with said count being compared against a threshold (T_{h}). The value of (T_{h}) is the maximum Hamming Distance between a received and decoded sequence which it is decided can be tolerated. The reasoning is that the probability of more errors is less than the probability of fewer errors, and that if an additional correction make the number of corrections extant greater than (T_{h}), then the null zone should be expanded by increasing the value of Δ. Expanding the null zone increases the number of possible branch points and this increases the possibilities for decoding sequences at a distance (T_{h}) or less from the received sequence. Regarding the approach based on Euclidean distance, a squared distance between received and decoded symbols is monitored. A running sum of the distance between the sequential decoder output (x_{k}) and the received sequence is computed and compared to the distance between the output of the hard decision decoder (x_{k}) and the received sequence. At a time “n” this is accomplished by comparing the Euclidean distance for the sequential decoder means: The value of (T_{h}) can be initialized to 1.0 if it is desired to explore all single error events, with increases in (T_{h}) being implemented only when a maximum value of Δ is applied. It is noted, however, that single errors with large Δ may actually be less a problem than double errors with a small Δ. Thus, it can be advantageous to increase the value of (T_{h}) before increasing Δ. In view of the foregoing, it should be appreciated that there are three parameters which can be varied in controlling the discard criteria, namely:
In the following two present invention application scenarios are discussed, namely Breadth First and Depth First. In the Depth First approach the complexity depends almost completely on the number of symbol decodings that take place during a packet decoding. For a Breadth First approach, two major factors affect the complexity. The first is the average number of decodings that take place during the decoding of a packet, which remains less than M times the number of symbols in a given packet. The second factor is the sorting that takes place before an expansion at a branch point. With the foregoing in mind, additional comments are appropriate regarding two distinguished approaches to Decoding, (ie. Breadth First and Depth First). Applying the Breadth First approach, involves fixing the size of the null zone prior to decoding. It is desirable to keep the null zone small to reduce the number of branch points, and hence the amount of computation, small. At the same time it is necessary to utilize a null zone sufficiently large that the probability of missing an error is below what it is determined can be tolerated. Assuming an AWGN channel with a known SNR, Δ can be selected as: It is further noted, in the context of a Breadth First approach, that knowing the Modulation Technique applied can allow determination of Specifc Bistable Elements in a Sequential Decoder means which serve as fixed “Branch Points”.
Of course the selected series of sequential bits will be determined by at least one criteria being met, said criteria being for instance:
To implement the Depth First approach the parameters required are:
It has been found useful to define two thresholds T_{h,t }and T_{h,w }for Hamming distance and two thresholds α_{t }and α_{w }for the Euclidean distance. The total Hamming distance between the decoded sequence and the sequence obtained by hard decision decoding to the threshold T_{h,t }as previously described. The Hamming distance between the decoded sequence on the code Tree and the sequence obtained by hard decision decoding in a sliding window of size L_{w }to the threshold T_{h,w}. The end point of the sliding window is the current bit. A similar procedure is used for the Euclidean distance. It is noted that the values of T_{h, t }and T_{h,w }are obtained using two estimates of channel noise variance, one for the entire received sequence σ_{t} ^{2}, and one for the sliding window of size L_{w}. The variance σ_{t} ^{2 }is translated into a channel probability error “p”, and the two thresholds are obtained as:
Computational effort was determined by computing the ratio of the total number of decode operations performed by the decoder to the number of symbols transmitted. In the case where no errors occurred this ratio is one. When an error is detected, because of backtracks, the decoding scheme requires more decode operations than the number of symbols transmitted resulting in a value greater than one. When said ratio exceeded 10^{3 }a decoding failure was declared. Table 1 presents the results of using the depth first decoding approach in terms of packet recovery rates for the four different values of the error detection space:
For comparison, also included is the case where the standard arithmetic encoder is used, albeit with packetization. The results show a more than 99% recovery rate for ε=0.16, 0.29, and 0.5; at a channel error rate of 10^{−3 }Similarly high results hold for ε=0.29 and 0.5 for p_{c}=10^{−2.5}; where p_{e }is the probability of error for a symbol being transmitted over the channel. However, for higher error rates the recovery rates drop significantly. Note that for a given channel error probability the amount of error space that is used is inversely proportional to the probability of packet loss. To implement the Breadth First approach various parameter values were selected as follows: M=200, M_{inc}=1800, and M_{max}=2000. Δ was chosen to be {1.20, 1.00, 0.91, 0.82} for channel error probabilities of {10^{−15}, 10^{−2}, 10^{−2.5}, 10^{−3}}, respectively. The parameters used give the lower bounds on packet loss rates of {10^{−1.5}10^{−3}, 10^{−4}, 10^{−5}}, respectively. It should be recalled that he algorithm functions by first listing all possible paths at a branch point, then pruning all but the M which are closest in Euclidean distance, to the received sequence. Between the branch point paths get pruned because progressing along them results in the decoding of the error of the detection space. Table 2 presents recovery rates for the case where Breadth First decoding was applied.
The recovers rate is greater than 99% for all values of c for channel probabilities of error of 10^{−2.5 }and 10^{−3.0}. For p_{e}=10^{−2 }the recovery rate is still greater than 99% for ε=0.29 and 0.5. For p_{c}=10^{−1.5 }a recovery rate of 73% of the packets for ε=0.50 may still be useful for some applications. Notice that at higher error rates the Breadth first approach substantially out-performs the Depth First approach. A penalty is paid for this performance at lower error rates, however, where the computational cost of the Breadth First approach is higher than the Depth First approach. Finally, performance of the present invention Joint Source Channel Coding Strategy is compared to that of three conventional schemes:
The performances of the identified schemes is plotted in {2.368, 4.323, 5.714, 6.790} decibels. Continuing, the amount of redundancy indicated in Table 3 shows that the convolutional codes have the highest amount thereof, followed by the present invention scheme with ε=0/5. The present invention scheme with ε=0.29 has the lowest amount of added redundancy of the schemes compared. It should be specifically appreciated that the present invention algorithm is only slightly more complex than a standard Arithmetic encoding scheme, with the added complexity being present primarily at the decoder. In the Depth First approach the complexity depends almost completely on the number of symbol decodings that take place during a packet decoding, hence the complexity is slightly more than the average number of symbol decodings for a given SNR. As alluded to earlier, for a Breadth First approach, two major factors affect the complexity. The first is the average number of decodings that take place during the decoding of a packet, which remains less than M times the number of symbols in a given packet. The averages can be seen in Present invention schemes provide substantial packet recovery rates at channel rates as low as 10^{−1.5 }with low coding overhead. Such schemes are useful in hostile communication environments where minimal coding overhead is advantageous. The approach may be especially useful for mobile and wireless applications. The present invention can be applied in communication systems which operate based on Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK) and Trellis Coded Modulation (TCM) etc. It is noted that the terminology “variable length” refers to the length of code words assigned to input symbols, and the “joint source-channel symbol encoding” refers the use of the same encoding means to encode “allowed alphabetic symbols” and “non-alphabet symbols” for use in error correction. Finally, it is noted that the present invention is primarily useful when applied with variable length symbol coding methods. For example Huffman coding provides coding more probably symbols with shorter bit sequences. Arithmetic encoders code strings of symbols in a sequence of bits, and Claim language structure is focused to apply thereto. Having hereby disclosed the subject matter of the present invention, it should be obvious that many modifications, substitutions, and variations of the present invention are possible in view of the teachings. It is therefore to be understood that the invention may be practiced other than as specifically described, and should be limited in its breadth and scope only by the Claims. Patent Citations
Non-Patent Citations
Classifications
Legal Events
Rotate |