|Publication number||USRE43236 E1|
|Application number||US 12/779,885|
|Publication date||Mar 13, 2012|
|Filing date||May 13, 2010|
|Priority date||Nov 16, 2006|
|Also published as||US7371005, US20080117722|
|Publication number||12779885, 779885, US RE43236 E1, US RE43236E1, US-E1-RE43236, USRE43236 E1, USRE43236E1|
|Inventors||Hoa Vu, Teck-Boon Serm, Bhupendra K. Ahuja|
|Original Assignee||Intersil Americas Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Classifications (12), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit of Provisional Application No. 60/859,396 filed on Nov. 16, 2006 and Provisional Application No. 60/869,683 filed on Dec. 12, 2006, both entitled “AUTOMATIC CIRCUIT AND METHOD FOR TEMPERATURE COMPENSATION OF OSCILLATOR FREQUENCY VARIATION OVER TEMPERATURE FOR A REAL TIME CLOCK CHIP”, both being incorporated by reference in their entireties into the present application.
The invention relates to electronic devices, and, more particularly, to timekeeping devices useful in personal computers and other consumer electronics, as well as networking devices.
Personal computers typically include a clock/calendar that tracks the time of day, day, month, and year. Such a clock/calendar has various uses such as time stamping files and inserting dates into documents, such as letters and e-mails both sent and received. The clock/calendar must be programmable for setting or changing the date or time of day. A clock/calendar is typically implemented in specific hardware with a dedicated crystal oscillator to insure accuracy and a battery backup power supply to insure preservation of timekeeping data during an interruption of the primary power supply. This is especially important with personal computers which are frequently powered down.
Crystals generally show frequency variation with temperature resulting into several hundred ppm shift in their nominal frequency. Most applications, in particular, a Real Time Clock (RTC), requires accuracy of the input clock to be within +/−5 ppm over a temperature range of −40 to 85° C. in order to provide accurate time information to the user.
An RTC with a 32.768 kHz quartz tuning-fork crystal oscillator is currently the standard timekeeping reference for most electronic applications. The RTC maintains the time and date by counting seconds, which requires an oscillator divider chain to derive a 1 Hz clock signal provided by the 32.768 kHz crystal oscillator. The current time and date information is stored in a set of registers, which is generally accessed through a communication interface.
Tuning fork type crystal oscillators are known to have both a frequency offset at room temperature and frequency variation over temperature, typically resulting into several hundred ppm frequency shift from their nominal frequency of 32.768 kHz. These frequency offsets can be broken into two portions, one being the initial frequency inaccuracy, with the other being the frequency fluctuation over temperature. The typical frequency stability of a crystal can be described by equation (1) below:
Where Δf is in the total frequency variation in ppm; Δfi is the initial frequency tolerance at 25° C., which usually within the range of ±32 ppm; α is the parabolic curvature constant of the crystal, for the commonly used quartz watch crystal, α has a typical value of 0.034 ppm/C2 for quartz; T is temperature in Celsius and T25 is 25° C. This parabolic frequency versus temperature characteristic is depicted in
Δfi is the constant frequency offset due to the manufacturing quality issues and aging of the crystal. The value of the second term in equation 1, α(T−T25)2, is determined by a which is a characteristic of the particular crystalline material, and the operating temperature. Both terms combined could contribute to a frequency variation up to about 200 ppm. For an RTC, 100 ppm in the frequency variation implies that there is about 120 seconds (about 2 minutes) of error at the end of a month's time.
It is well known to use load capacitors to adjust the parallel resonance frequency, f0, of crystal oscillators. This frequency, f0, has an inverse square root relationship to load capacitor (CL) changes. For on-chip load capacitor designs, some known designs use switched capacitor arrays controlled digitally by input code vectors. Such capacitor arrays are known as capacitor digital-to-analog converters (referred to as capacitor DACs, capacitive DACs or CDACs). A conventional capacitor DAC comprises of an array of N capacitors hooked in parallel with binary weighted values plus generally one “dummy LSB” capacitor. During the acquisition phase, the array's common terminal (the terminal at which all the capacitors share a connection) is connected to ground and all free terminals are connected to the input signal (Analog In or VIN). After acquisition, the common terminal is disconnected from ground and the free terminals are disconnected from VIN, effectively trapping a charge proportional to the input voltage on the capacitor array. Due to the binary weighting and conventional digital code used, in response to the applied digital input codes, such DACs provide a linear analog output (capacitance).
Some RTCs provide a digital calibration register that can be used to periodically adjust the time of day in discrete amounts. This method does not attempt to alter the crystal behavior, but instead, periodically adjusts the time according to the expected frequency deviation at a specified temperature. The effect is to move the 32.768 kHz parabolic curve up or down in an attempt to approach 0.0 ppm accuracy at a desired temperature. This is accomplished by adding or subtracting clock cycles from the oscillator divider chain. The number of clock pulses removed (subtracted for negative calibration) or inserted (added for positive calibration) is set by the value in the calibration register. By adding clock pulses, time is sped up (the crystal curve moves up). In contrast, by subtracting clock pulses, time is slowed down (the crystal curve moves down).
Another method dynamically changes the load capacitance to “trim” the crystal frequency. One known RTC circuit of this type includes a 6-bit capacitor DAC that provides a delta of 0.5 pF for each code which is used to trim the frequency. In such an arrangement, due to the well known nonlinear frequency to CL relationship, changing CL linearly results in a nonlinear change in frequency. For precision applications requiring better than ±5 ppm precision over a normal operating temperature range, such a non-linear frequency trim arrangement generally cannot meet the requirement.
A linear frequency shift per input code would be desirable as it would provide improved precision. However, due to the nonlinear frequency to CL relationship, the input code vectors would need to be nonlinear and more specifically parabolic to provide a linear frequency shift. Using known methods, this would require nonlinear digital signal processing which can be complex, and also generally requires a large chip area and significant power consumption. Thus, what is needed is a compact, low power RTC circuit which does not require factory calibration and automatically provides a minimal frequency variation over the full RTC operating temperature range, such as within ±5 ppm from −40 to 85° C.
This Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal. A DSP engine receives the digital temperature signal and calculates frequency correction needed to correct for frequency inaccuracy and determines a bit sequence including the ATR bits appropriate to achieve the frequency correction.
The non-linear DAC can comprise a piecewise linear segmented DAC, comprising a plurality of piecewise linear segments connected in parallel. In this embodiment, the plurality of segments can be binary weighted segments. Some of the plurality of segments are controlled by a first number of ATR bits and other of the segments are controlled by a different number of ATR bits. The RTC can further comprise thermometer decoder logic for receiving the ATR bits and generating a plurality of control lines for controlling the switches.
The DSP calculation preferably splits the frequency correction into ATR bits and into coarser Digital Trimming (DTR) bits, wherein the digital trimming bits are operable to perform frequency correction by adding or skipping clock cycles. In this embodiment, the RTC can further comprise an RTC digital trimming module including a clock divider chain for generating a 1 Hz clock from fp, wherein the DTR bits are coupled to an input of the digital trimming module, the digital trimming module performing frequency adjustment on the 1 Hz clock.
The temperature sensor block can comprise a delta Vbe-based temperature sensor (delta Vbe-based temperature sensors are also known in the art as bandgap references). The temperature sensor block can further comprise a PTAT block coupled between the Vbe-based temperature sensor and the A/D converter, wherein process trim (PTR) bits coupled to the PTAT trim at least one of offset and gain for the A/D converter.
RTC and related circuits according to the invention provide low power operation. The RTC chip generally runs at an average current of <1 μA and an average power of <5 μW. In one embodiment, the RTC chip includes a buck voltage regulator for stepping down a supply voltage received by the chip to a lower level. The temperature sensor block can operate with a duty cycle of <1:1,000. The DSP module can be configured exclusive of hardware multipliers. The A/D converter can be a switched-capacitor based A/D converter.
A method for temperature compensating real time clocks comprises the steps of providing a real-time clock (RTC) having a crystal oscillator block comprising a crystal coupled to crystal compensation circuitry. The crystal compensation circuitry comprises a non-linear Capacitor DAC having a plurality of load capacitors having respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block, wherein the capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance resulting in a linear relationship between fp and the ATR bits. The temperature of the crystal is measured. An input code comprising the ATR bits is generated based on the temperature to correct fp. Frequency correction is implemented by applying input code vectors to the Capacitor DAC to provide a frequency shift to temperature correct an oscillator frequency of the crystal oscillator. The linear relationship between fp and the ATR bits can comprise a constant integer/bit, such as 1 ppm/bit. In one embodiment, the generating step comprises generating Digital Trimming (DTR) in addition to the ATR bits, wherein the DTR bits provide a coarser frequency adjustment as compared to the ATR bits and operate by adding or skipping clock cycles derived from the oscillation frequency. A trim frequency resolution of an LSB of the DTR bits can be more than a maximum trim frequency adjustment provided by the ATR bits. The chip can be operated at an average current of <1 μA and an average power of <5 μW. The frequency correcting can comprise continuous non-overlapping frequency adjustment over a range of at least 100 ppm, such as from −63 to 223 ppm.
A fuller understanding of the present invention and the features and benefits thereof will be accomplished upon review of the following detailed description together with the accompanying drawings, in which:
First, Applicants provide some notation used in the Figures and the detailed description: a capacitor array controlled digitally by input code vectors (DAC or Capacitor DAC); band gap circuit (BGAP), Proportional To Absolute Temperature circuit (PTAT); analog trimming register (ATR); digital trimming register (DTR), and temperature coefficient (TC).
Moreover, although specific numbers of bits are shown for registers shown in the drawings and described herein, the present invention is not limited to the number of bits shown and described for each register.
An automatic temperature compensated real time clock (RTC) chip comprises a clock portion including a crystal oscillator block comprising crystal compensation circuitry adapted to be coupled to a crystal, the crystal generally being external to the chip. The compensation circuitry comprises a non-linear capacitor DAC which includes a plurality of load capacitors. The load capacitors have respective switches which switch respective capacitors to change the parallel resonant frequency (fp) provided by the oscillator. The DAC is arranged so that Analog Trimming (ATR) bits received as inputs cause an arrangement of the switches to provide a non-linear change in overall load capacitance, the non-linear change being a parabolic change configured to result in a linear relationship between fp and the number of ATR bits.
An on-chip temperature sensor block is coupled to the crystal for measuring a temperature of the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital signal representative of the temperature of the crystal. A DSP engine receives the digital signal representative of the temperature and calculates the frequency correction needed determines a bit sequence of ATR bits, and optionally DTR bits as described below, to achieve frequency correction. Although the present invention is generally described relative to a quartz crystal which has provides a nominal oscillation frequency of about 32.768 kHz, the present invention can operate with other crystal types which operate at other nominal oscillation frequencies.
RTC chips according to the present invention are very low power, generally drawing a supply current of less than 1 μa. Preferably, the ADC used with the present invention is a low power ADC. For example, the switched-capacitor based ADC disclosed in a paper by Onodera et al. entitled “A Cyclic A/D Converter That does not Require Matched Components”, IEEE JNL of Solid-State Circuits, Vol. 23, No. 1, February 1988 can be used. However, other ADC designs may be used with the present invention, preferably being low power designs.
Several other aspects of the present invention significantly contribute to low power aspect of the present invention. The RTC logic described below is preferably run at a low frequency, such as 32.768 kHz. An on-chip voltage regulator is also preferably provided, for example, so that a higher supply voltage received by the chip, such as a VCC of 2.7 to 5.5 volts, is stepped down to a lower voltage, such as 2.4 volts, for use on the RTC chip. Channel lengths of RTC logic gates can also designed to have comparatively long channel lengths to decrease the magnitude of shoot through currents. The temperature sensor is also preferably designed to have a very low duty cycle. Specifically, in one embodiment, the temperature sensor initiates temperature sampling which lasts around 1 msec, or less, with the sampling occurring for example, only once every minute. The capacitor DAC is also configured to consume essentially no DC power because capacitors do not carry steady DC current. The DTR circuitry which in one embodiment implements the DSP algorithm together with ATR bits is also preferably configured without any hardware multipliers or other power hungry circuitry. The DSP is a lower power module because the DSP algorithm is implemented using hard-wired blocks (as opposed to programmable blocks) which results in much smaller gate count, intermediate signals are bussed, and its speed is optimized for low power application.
The invention obtains accurate crystal temperature data on the RTC chip, and uses the temperature data to automatically correct the oscillator frequency as the temperature changes. An on-chip temp sensor, an A/D to digitize the analog sensed temperature data and a DSP algorithm to provide crystal correction based on a stored frequency deflection relationship with temperature for the associated crystal, are preferably all implemented on the same chip, such as a Si chip. As noted above, crystal oscillators use load capacitors to adjust their parallel resonance frequency, fp, and the fp for a Pierce Oscillator has an inverse square root relationship to load capacitor (CL) changes.
The invention uses an on-chip load capacitor array which is controlled digitally by input code vectors. As noted above, such capacitor arrays are referred to herein as Capacitor DACs and inputs to the Capacitor DACs as ATR bits and optionally also DTR bits. Due to the well known nonlinear frequency (fp) to CL relationship provided by a Pierce Oscillator, to achieve a desired linear frequency shift per ATR bit requirement, a non-linear input code can be used. However, as noted in the Background, the generation of a non-linear input code generally requires nonlinear digital signal processing, which is fairly complex. By instead providing a non-linear capacitor DAC according to the invention, the desired linear frequency shift per ATR bit requirement is provided without the need for a non-linear input code. In a preferred embodiment, the nonlinear capacitor DAC is implemented using a plurality of piecewise linear segments. This frequency control is generally used for automatic crystal frequency compensation against temperature variation. A prototype device was found to provide frequency correction within ±5 ppm over the full temperature range from −50 to 95° C.
To achieve a linear step size of frequency shift, such as a constant integer number (e.g. 1) ppm of frequency shift for each ATR bit, CL is changed in non-linear parabolic manner. Accordingly, for capacitor DACs according to the present invention, the capacitor DACs are arranged so that ATR bits produce nonlinear parabolic changes in the value of CL, wherein the parabolic change results into linear frequency shifts (see
As shown in
In a preferred embodiment, a six bit ATR output by DSP 115, ATR<5:0>, changes the on-chip CL for the crystal to change its center frequency in a constant fine resolution of 1 ppm/code. Thus, the six bit ATR can change crystal frequency over +/−32 ppm range in 1 ppm steps. In one embodiment, the DTR is 3 bits, DTR<2:0> which change the crystal frequency digitally by adding or swallowing some clock pulses, such as every second. As described below, DTR is a relatively coarse control with an exemplary range of −32 ppm to +192 ppm, with 32 ppm step size.
The ATR bits are applied to a non-linear Capacitor DAC according to the invention 120. Capacitor DAC 120 is coupled to the crystal compensation circuitry 122 which is coupled to the crystal 123. The DTR bits are applied to digital trim logic 125 including a clock divider chain for generating a 1 Hz clock, wherein the DTR bits are coupled to an input the digital trimming module, the digital trimming module performing frequency adjustment on a 1 Hz clock derived from fp as described in more detail below.
PTR(7:0) bits are input to PTAT 415. ADC 420 has inputs Vptat and Vref. The 10 bit ADC 420 output is given by 1024*Vptat/Vref. The Vptat signal ideally should be proportional to Temperature with no DC offset, such that:
However, the actual (non-ideal) Vptat signal is as follows:
Thus, PTR(7:0) bits can be used in the present invention to add/subtract dc signals from Vptat (actual) to null out “Offset” voltage as well as correct the “Gain” coefficient to “Ideal_Gain_Constant” value. After Offset and Gain corrections, ADC 420 advances by 2 LSB for each 1 deg C. or:
ADC(Code in Decimal)=2*(Temperature+273)
PTR bits can be set by the test program thru a Serial Interface to the RTC chip. In one arrangement, the test program checks ADC codes at 2 different known temperatures and calculates Gain and Offset trim bit values. These PTR(7:0) bits can then be stored permanently inside the chip using a non volatile memory, such as an EE memory register.
A simplified flow chart for the present invention can be described as follows: The user measures Fout provided by a pin on the RTC chip at room temperature and inputs ATR0, DTR0 for initial accuracy, or to compensate for crystal aging. On the circuit, the following data sequence automatically occurs:
band gap (BGAP) Ref+PTAT→10 bit ADC→Junction Temp (e.g. in Kelvin)→crystal TC LOGIC→F_ATR and F_DTR→NonLinear DACs of crystal Oscillator→temperature compensated fp.
Another inventive aspect of the present invention relates to a new frequency trim algorithm and implementing circuitry. As noted in the background, a typical stability of a crystal can be described by equation (1), repeated below.
In order to compensate the initial frequency error Δfi, the present invention can use initial trim registers, such as an Initial Digital Trimming Register (DTR0) and the Initial Analog Trimming Register (ATR0). The user can measure Fout provided by a pin on the RTC chip at room temperature and input ATR0, DTR0 which corrects for initial accuracy, or sometime later to compensate for crystal aging. These two registers are used to program the initial frequency correction term IPPM.
As noted above, the trimming preferably splits the frequency correction into two portions, referred to herein as ATRs and DTRs, the coarser DTRs minimizing the chip area needed for phase adjustment on the crystal. Digital trimming which is based on adding or swallowing (omitting) some pulses from the crystal compensation circuitry is a technique that has been applied to previous generations of RTC chips. However, the combination of ATR and DTR according to the present invention which provides continuous, non-overlapping frequency adjustment was unknown prior to the present invention. For example,
As described above, the initial Digital Trimming Register (DTR0) and Initial Analog Trimming Register (ATR0) can be used to program the initial frequency correction term IPPM. The frequency correction (in ppm) corresponding to these registers are shown on Table 1 and Table 2 below.
Initial Exemplary Digital Trimming Register and corresponding
Initial Exemplary Analog Trimming Register and corresponding
Also as described above, referring again to
To convert the parabolic curvature constant α into binary code, a 7 bit register (ALPHA) can be used, where
The ALPHA register can be in the value of 33 hex.
The DSP will then compute the product term PROD and temperature/crystal dependent correction term CPPM, where
The final frequency correction needed, the Net PPM (NPPM), is then given by
The NPPM is an 11 bit register, and it is in the structure as shown below,
S=Sign Bit; Indicates the direction of correction
[X1,X0]=Extra Bits; If either one of them is at Logic High (1), it means that the Net PPM desired has been outside the correction limit, which in the embodiment described herein is within −63 ppm to +223 ppm.
Because of the above-described NPPM structure, the NPPM bits can be simply distributed into Final Digital Trimming Register (F_DTR) and Final Analog Trimming Register (F_ATR), respectively.
Regarding analog trimming and CURRENT_ATR 143, the F_ATR is the final input that is applied to the 6 bit capacitor DAC, which modulates the oscillating frequency of the crystal. For a 6 bit F_ATR trimming 1 ppm/bit, the F_ATR provides frequency trimming between the ranges of ±32 ppm, as shown in Table 2 above.
In order to minimize the disturbance on the crystal and crystal compensation circuit, in a preferred embodiment of the invention the CURRENT_ATR is directly connected to the DAC. Once the F_ATR has been computed, the CURRENT_ATR will move toward the F_ATR gradually, such as with one ppm per crystal clock, until CURRENT_ATR is equal to the F_ATR. In the extreme case, it takes 64 crystal clocks to complete such adjustment. This new technique provided smooth phase modulation for the crystal and avoids overshoot.
Regarding digital trimming for RTC, as described above, the crystal can suffer from frequency fluctuation of up to 200 ppm over the operating temperature range. However, it is extremely costly in terms of chip area to correct such a wide frequency variation by using conventional ATR trimming. In a preferred embodiment, ATR trimming is preferably limited among the frequency correction of ±32 ppm, while the rest of the correction, up to the range of 192 ppm, is implemented by utilizing the DTR function. The effect of exemplary F_DTR trimming is shown in Table 3 below.
Exemplary F_DTR and corresponding frequency correction
Since the RTC ticks on the 1 Hz frequency, the RTC includes a divider chain to generate the 1 Hz clock, with an exemplary frequency divider 800 being shown in
DTR correction is frequency correction that is applied to clock F1Hz circuitry. To speed up the F1Hz, the circuit should count faster in the divider chain by counting a single F32 kHz cycle twice. While to slow down the F1Hz, the circuit should skip a count of an F32 kHz cycle. This is implemented according to an embodiment of the invention as shown as DTR circuitry 840 in
Again, to achieve smooth frequency adjustment, and also to achieve a large correction range, such as up to 192 ppm, the frequency trimming adjustment is performed gradually by distributing the trim among the 1 million cycles of F32 kHz. This means that every 5208 (1 million/192) cycles of F32 kHz clock, a trimming will happen, depending on the input of F_DTR. This is depicted in
As an example,
Although the present invention is described herein applied to an RTC circuit, the invention can be used in a variety of other products, including clock synthesizers, phase lock loops, crystal oscillators, and other timing products. The low power aspect of the present invention, generally requiring no more than 1 μa at 2.4 volts for implementation as an RTC, for example, makes the present invention highly desirable for many applications because of the ability to limit the battery backup power supply required.
In the preceding description, certain details are set forth in conjunction with the described embodiment of the present invention to provide a sufficient understanding of the invention. One skilled in the art will appreciate, however, that the invention may be practiced without these particular details. Furthermore, one skilled in the art will appreciate that the example embodiments described above do not limit the scope of the present invention and will also understand that various modifications, equivalents, and combinations of the disclosed embodiments and components of such embodiments are within the scope of the present invention.
Moreover, embodiments including fewer than all the components of any of the respective described embodiments may also within the scope of the present invention although not expressly described in detail. Finally, the operation of well known components and/or processes has not been shown or described in detail below to avoid unnecessarily obscuring the present invention.
One skilled in the art will understood that even though various embodiments and advantages of the present Invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. For example, some of the components described above may be implemented using either digital or analog circuitry, or a combination of both, and also, where appropriate may be realized through software executing on suitable processing circuitry. The present invention is to be limited only by the appended claims.
It is to be understood that while the invention has been described in conjunction with the preferred specific embodiments thereof, that the foregoing description as well any examples provided are intended to illustrate and not limit the scope of the invention. Other aspects, advantages and modifications within the scope of the invention will be apparent to those skilled in the art to which the invention pertains.
The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
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|U.S. Classification||368/202, 331/176|
|International Classification||H03L1/00, G04B17/20|
|Cooperative Classification||H03L1/027, H03L1/022, H03L1/028, G04F5/06|
|European Classification||H03L1/02B, H03L1/02C, G04F5/06, H03L1/02B3|
|Jul 26, 2010||AS||Assignment|
Owner name: INTERSIL AMERICAS INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VU, HOA;SERM, TECK-BOOM;AHUJA, BHUPENDRA K.;SIGNING DATES FROM 20071015 TO 20071107;REEL/FRAME:024737/0572
|Jun 10, 2014||AS||Assignment|
Owner name: INTERSIL AMERICAS LLC, CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:INTERSIL AMERICAS INC.;REEL/FRAME:033119/0484
Effective date: 20111223
|Nov 13, 2015||FPAY||Fee payment|
Year of fee payment: 8