|Publication number||USRE43248 E1|
|Application number||US 10/066,475|
|Publication date||Mar 13, 2012|
|Filing date||Feb 1, 2002|
|Priority date||Jun 10, 1994|
|Also published as||US5758115, US6021265|
|Publication number||066475, 10066475, US RE43248 E1, US RE43248E1, US-E1-RE43248, USRE43248 E1, USRE43248E1|
|Inventors||Edward Colles Nevill|
|Original Assignee||Arm Limited|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (91), Non-Patent Citations (26), Classifications (15)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a divisional of application Ser. No. 08/477,781 filed on Jun. 7, 1995 now U.S. Pat. No. 5,758,115.
1. Field of the Invention
This invention relates to the field of data processing, and in particular to data processing using multiple sets of program instruction words.
2. Description of the Prior Art
Data processing systems operate with a processor core acting under control of program instruction words which when decoded serve to generate core control signals to control the different elements in the processor to perform the necessary operations to achieve the processing specified in the program instruction word.
It is known to provide systems that execute program instruction words from two or more instruction sets, with means being provided to switch between use of the different instruction sets. The VAX11 computers of Digital Equipment Corporation have a VAX instruction mode and a compatibility mode that enables them to decode the instructions for the earlier PDP11 computers.
In order to switch between the different instruction sets, an instruction set switch may be hard-wired into the processor core necessitating a physical rewiring of the processor to switch instruction sets. Alternatively, a processor register may be used to specify the current instruction set to be used. In this case, the current instruction set can be selected by the operating software, by writing an instruction set-specifying value to that processor register. However, as described below, this technique requires additional program instruction words, which in turn require extra time during preparation of the software and extra memory space to store the program instruction words.
In order to execute a piece of code, a processor capable of using two or more instruction sets must have two pieces of information:
1) The address of the code in memory; and
2) The instruction set to use (i.e. the instruction set in which the code is written)
Typically, in the previously proposed processors, a call to a routine in a different instruction must be performed as described below.
1) The subroutine call is diverted from its original destination to an automatically generated instruction set selection sequence or veneer.
2) The veneer must then accomplish the following
This process can be made relatively transparent to the programmer by use of a conventional software tool called a Linker. However, the process has a five instruction overhead per routine which is called from a different instruction set, and it also introduces a significant processing overhead.
It is an object of the invention to improve the capabilities of data processing apparatus to switch between multiple instruction sets.
This invention provides a data processing apparatus comprising:
With the invention, a control flag or flags to select a current instruction set is provided in the program counter register. This allows the current instruction set to be changed when a new value is written into the program counter register, for example as part of the execution of a branch instruction.
The invention recognises that if the required instruction set and the next instruction address are encoded in separate processor registers as in the previously proposed processors described above (an instruction set register and a program counter register), it becomes difficult to change between instruction sets as the two separate registers have to be updated to accomplish a call to a section of code written in a different instruction set.
As an example, consider a program which is to perform a sorting or collation function. Typically this will call a generic sort routine to perform the sort. As this sort routine is generic, it must be capable of sorting in any given sequence. For example, it may be called to sort items in numerical order, alphabetical order, case insensitive alphabetical order, or any other order specified by the programmer. The means by which the programmer specifies the sorting order is to pass the address of a routine (called a compare routine) to the sort routine. This compare routine will then be called by the sort routine and will return a value to indicate whether, given two items of data, the first should be placed before or after the second in the sorted sequence.
If just the address of the compare routine is passed to the sort routine then the sort routine has no way of knowing which instruction set should be selected when the routine is to be called. If the wrong instruction set is current when an attempt is made to execute the compare routine, the results can be dramatically unsuccessful. Extra information must be passed to the sort routine to tell it what instruction set should be in force when the compare routine is called. However, many existing programs written in high level languages such as C & C++ make assumptions that all the information necessary to uniquely identify a target routine (in this case the address and the instruction set information) can be represented in a single machine word.
The invention addresses these problems by defining a predetermined bit or bits of the program counter register (PC) to indicate the instruction set to be used. In the specific example given above, the address of the compare routine passed to the sort routine can have the required instruction set encoded in the predetermined bit or bits of that address. The address, including the indicator bit or bits, is then simply moved to the program counter register when the compare routine is called.
Although certain bits of the program counter register can be reserved for use as the indicator bits, an alternative approach is to store portions of code to be executed using the various instruction sets in corresponding memory areas, so that while those memory areas are being accessed the program counter will contain a particular range of values specifying the appropriate instruction set to be used.
In order to decode instructions from the different instruction sets, it is preferred that the apparatus comprises a first instruction decoder for decoding program instruction words of the first instruction set; and a second instruction decoder for decoding program instruction words of the second instruction set; and that the control means is operable to control either the first instruction decoder or the second instruction decoder to decode a current program instruction word.
Preferably, program instruction words of the first instruction set are X-bit program instruction words; and program instruction words of the second instruction set are Y-bit program instruction words; where Y is different to X. In this way, a common processor core can be programmed with either an instruction set having longer program instruction words and allowing potentially more powerful and involved instructions, or an instruction set having shorter program instruction words, thus saving memory space where a potentially more limited instruction set can be tolerated.
In one preferred embodiment, the one or more bits of the program counter register are one or more most significant bits of the program counter register. In a program counter register of say, 32 bits, the highest order bits are seldom required since the maximum memory space that can be addressed by such a large program counter register is much more than the memory space normally used.
Alternatively, in another preferred embodiment, the one or more bits of the program counter register are one or more least significant bits of the program counter register. In this case, these bits are often not used where the minimum length of program instruction words or data words is at least two bytes.
In order to avoid invalid addresses in the data memory being accessed, it is preferred that means are provided for accessing a program instruction word stored in the data memory, the accessing means not being responsive to the one or more bits of the program counter register.
The above and other objects, features and advantages of the invention will be apparent from the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawings, in which:
The processor core 10 includes a register bank 30, a Booths multiplier 40, a barrel shifter 50, a 32-bit arithmetic logic unit (ALU) 60 and a write data register 70. Between the processor core 10 and the memory system 20 are: an instruction pipeline 80, a multiplexer 90, a first instruction decoder 100, a second instruction decoder 110, and a read data register 120.
A program counter (PC) register 130, which is part of the processor core 10, is shown addressing the memory system 20. A program counter controller 140 serves to increment the program counter value within the program counter register 130 as each instruction is executed and a new instruction must be fetched for the instruction pipeline 80. Also, when a branch instruction is executed, the target address of the branch instruction is loaded into the program counter 130 by the program counter controller 140.
The processor core 10 incorporates 32-bit data pathways between the various functional units. In operation, instructions within the instruction pipeline 80 are decoded by either the first instruction decoder 100 or the second instruction decoder 110 (under the control of the multiplexer 90) to produce various core control signals that are passed to the different functional elements of the processor core 10. In response to these core control signals, the different portions of the processor core conduct 32-bit processing operations, such as 32-bit multiplication, 32-bit addition and 32-bit logical operations.
The register bank 30 includes a current programming status register (CPSR) 150 and a saved programming status register (SPSR) 160. The current programming status register 150 holds various condition and status flags for the processor core 10. These flags may include processing mode flags (e.g. system mode, user mode, memory abort mode, etc.) as well as flags indicating the occurrence of zero results in arithmetic operations, carries and the like. The saved programming status register 160 (which may be one of a banked plurality of such saved programming status registers) is used to store temporarily the contents of the current programming status register 150 if an exception occurs that triggers a processing mode switch.
The program counter register 130 includes an instruction set flag, T. This instruction set flag is used to control the operation of the multiplexer 90, and therefore to control whether the first instruction decoder 100 or the second instruction decoder 110 is used to decode a current data processing instruction. In the present embodiment, two instruction sets are used: a first instruction set comprises 32-bit program instruction words and is decoded by the first instruction decoder 100, and a second instruction set comprises 16-bit program instruction words and is decoded by the second instruction decoder 110. The core control signals generated by the first instruction decoder 100 and the second instruction decoder 110 are compatible with the various functional units of the core 10.
The use of two instruction sets of different program instruction word length allows a common processing core 10 to be programmed with either the first instruction set having longer words and allowing potentially more powerful and involved instructions, or the second instruction set having shorter program instruction words, thus saving memory space where a potentially more limited instruction set can be tolerated.
The provision of an instruction set flag T enables the second instruction set to be non-orthogonal to the first instruction set. This is particularly useful in circumstances where the first instruction set is an existing instruction set without any free bits that could be used to enable an orthogonal further instruction set to be detected and decoded.
The instruction set flag T is “hidden” in normally unused bits of the program counter register. This means that the T flag can be set or reset by the program counter controller 140, but the state of the T flag need have no direct effect on the operation of the memory system 20 and the instruction pipeline 80.
The program counter register is a 32-bit register, which allows 232 bytes to be addressed in the memory system 20. However, since this equates to 4 gigabytes of addressable memory space, it is extremely unlikely that the full address range made possible by the 21-bit program counter register will be required.
Accordingly, the T bit in
A problem which must be overcome is that when the T bit is set, the program counter register 130′ may well point to a memory address which is far in excess of the address range of the memory system 20. In other words, the memory address pointed to by the 32-bits of the program counter register 130 is an invalid address as far as the memory system 20 is concerned.
This problem can be overcome in two straightforward ways. In one technique, the highest order bit (the T bit) of the program counter register 130′ is simply not supplied as an address bit o the memory system 20. Alternatively, the address decoding within the memory system 20 may detect only a certain number of lowest order bits (e.g. the lowest order 24 bits to address a 16 megabyte address space), with the state of the remaining higher order bits being irrelevant to the decoded address. This is a standard technique in memory address decoding when it is known in advance that only a certain number of address bits will be required.
As described above, the T bit is passed from the program counter register 130′ to the multiplexer 90, and determines the routing of instructions to either the first instruction decoder 100 or the second instruction decoder 110.
The lowest order bit of the program counter register is normally unused in a processor in which the minimum instruction or data word size is at least two bytes (16 bits in this case). Accordingly, in the present embodiment the instruction program words may be either 32 bits long (4 bytes) or 16 bits long (2 bytes) so the addresses supplied from the program counter 130 to the memory system 20 will always be a multiple of two and will therefore have a zero as the least significant bit of the address.
The least significant bit of the program counter register 130″ is used to store the T bit, which is supplied to the multiplexer 90 as described above. Also as described above, the lowest order bit of the program counter register 130″ is not supplied to the memory system, in order that invalid addresses are not accessed by the memory system 20.
The fact that the program counter 130 is controlled by the program counter controller 140 means that the T bit can be set as part of a branch instruction carried out by the core 10. For example, if the T bit is currently set to indicate the use of the first (32-bit) instruction set and it is desired to branch to a portion of a code employing the second (16-bit) instruction set, then a branch instruction can be executed to jump to the address of the 16-bit code to be executed and simultaneously to change the T bit in the program counter register, in particular, in the arrangement shown in
This process is illustrated schematically in
When a switch is made between the two instruction sets by changing the T bit in the program counter 130, the actual switch-over by the multiplexer 90 may be delayed to allow for existing instructions currently stored in the pipeline 80.
In summary, the switch between different processing modes (in particular, the use of different instruction sets) can be made by writing a target address and a mode flag (T) to the program counter as part of the execution of a branch instruction.
In an alternative case where the first instruction set is pre-defined and used in existing processors, there may be logical restrictions within the existing first instruction set preventing the normally unused bits of the program counter register 130 from being changed by the instruction set. For backwards compatibility of processors incorporating the second alternative, instruction set, it may be necessary to employ a short instruction set selection sequence of code to switch in one direction from the first (existing) instruction set to the second instruction set. Since the second instruction set would generally be added at the same time that the switching mechanism is being added, the second instruction set can be defined without the restrictions on accessing normally unused bits of the program counter register 130. This means that the branching mechanism described above can be used to switch back from the second instruction set to the first instruction set.
An example of an instruction set selection sequence (known as a “veneer”) is as follows:
In this routine, the current contents of the program counter register 130″ of
In an alternative veneer routine, a subtract operation could be used instead of an exclusive-OR operation to change the T-bit of the program counter register 130″. This has the advantage that in some processors, the subtract operation also flushes or clears the instruction pipeline 80.
The following example assumes that the program counter 130″ points 8 bytes beyond the current instruction, and that the current instruction is a 32 bit (4 byte) instruction. Accordingly, to change the least significant bit of the program counter register 130″ to 1, it is necessary to add or subtract the following amounts to the current program counter register contents:
(to change the T bit to 1)
(to compensate for the program counter
pointing ahead of the current instruction)
(to compensate for the length of the current
The instruction sequence used is therefore:
(replace PC with PC-3)
In summary, the use of the program counter to store the instruction-set-specifying bit or bits has at least the following advantages:
1. It provides a single, uniform method of identifying a target routine by representing both the target address and the corresponding instruction set in a single machine word.
2. The code size is reduced as fewer veneers are required.
3. The processor performance can be improved as there is no longer a need to execute a veneer on each inter-instruction set routine call.
Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4217638||May 19, 1978||Aug 12, 1980||Tokyo Shibaura Electric Co., Ltd.||Data-processing apparatus and method|
|US4236204||Mar 13, 1978||Nov 25, 1980||Motorola, Inc.||Instruction set modifier register|
|US4274138||Feb 13, 1979||Jun 16, 1981||Tokyo Shibaura Denki Kabushiki Kaisha||Stored program control system with switching between instruction word systems|
|US4338663||Sep 18, 1980||Jul 6, 1982||Digital Equipment Corporation||Calling instructions for a data processing system|
|US4346437||Aug 31, 1979||Aug 24, 1982||Bell Telephone Laboratories, Incorporated||Microcomputer using a double opcode instruction|
|US4398243||Apr 25, 1980||Aug 9, 1983||Data General Corporation||Data processing system having a unique instruction processor system|
|US4434459||Apr 25, 1980||Feb 28, 1984||Data General Corporation||Data processing system having instruction responsive apparatus for both a basic and an extended instruction set|
|US4434461||Sep 15, 1980||Feb 28, 1984||Motorola, Inc.||Microprocessor with duplicate registers for processing interrupts|
|US4459657||Sep 22, 1981||Jul 10, 1984||Tokyo Shibaura Denki Kabushiki Kaisha||Data processing system having re-entrant function for subroutines|
|US4511966||Jan 28, 1983||Apr 16, 1985||Sony Corporation||Digital signal processing system|
|US4514803||Apr 26, 1982||Apr 30, 1985||International Business Machines Corporation||Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof|
|US4554627||Mar 9, 1983||Nov 19, 1985||Data General Corporation||Data processing system having a unique micro-sequencing system|
|US4685080||Feb 22, 1982||Aug 4, 1987||International Business Machines Corp.||Microword generation mechanism utilizing separate programmable logic arrays for first and second microwords|
|US4695943||Sep 27, 1984||Sep 22, 1987||Honeywell Information Systems Inc.||Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization|
|US4839797||Jul 25, 1985||Jun 13, 1989||Nec Corporation||Microprocessor compatible with any software represented by different types of instruction formats|
|US4849922||Dec 11, 1987||Jul 18, 1989||Cselt - Centro Studi E Laboratori Telecomunicazioni Spa||Circuit for computing the quantized coefficient discrete cosine transform of digital signal samples|
|US4870614||Dec 29, 1988||Sep 26, 1989||Quatse Jesse T||Programmable controller ("PC") with co-processing architecture|
|US4876639||Apr 6, 1988||Oct 24, 1989||Mensch Jr William D||Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit|
|US4905196||Oct 5, 1987||Feb 27, 1990||Bbc Brown, Boveri & Company Ltd.||Method and storage device for saving the computer status during interrupt|
|US4930068||Nov 9, 1987||May 29, 1990||Nec Corporation||Data processor having different interrupt processing modes|
|US4931989||Apr 15, 1987||Jun 5, 1990||International Business Machines Corporation||Microword generation mechanism utilizing a separate programmable logic array for first microwords|
|US5077659||Dec 20, 1990||Dec 31, 1991||Kabushiki Kaisha Toshiba||Data processor employing the same microprograms for data having different bit lengths|
|US5115500 *||Jan 11, 1988||May 19, 1992||International Business Machines Corporation||Plural incompatible instruction format decode method and apparatus|
|US5148536||Jul 25, 1988||Sep 15, 1992||Digital Equipment Corporation||Pipeline having an integral cache which processes cache misses and loads data in parallel|
|US5187791||Oct 29, 1991||Feb 16, 1993||Apple Computer, Inc.||Microprocessor with improved interrupt response with data saving dependent upon processor status using status flag|
|US5193158||Oct 18, 1991||Mar 9, 1993||Hewlett-Packard Company||Method and apparatus for exception handling in pipeline processors having mismatched instruction pipeline depths|
|US5276824||Jun 21, 1993||Jan 4, 1994||Motorola, Inc.||Data processor having a multi-stage instruction pipe and selection logic responsive to an instruction decoder for selecting one stage of the instruction pipe|
|US5303378||May 21, 1991||Apr 12, 1994||Compaq Computer Corporation||Reentrant protected mode kernel using virtual 8086 mode interrupt service routines|
|US5327566||Jul 12, 1991||Jul 5, 1994||Hewlett Packard Company||Stage saving and restoring hardware mechanism|
|US5335331||Jul 12, 1991||Aug 2, 1994||Kabushiki Kaisha Toshiba||Microcomputer using specific instruction bit and mode switch signal for distinguishing and executing different groups of instructions in plural operating modes|
|US5353420||Aug 10, 1992||Oct 4, 1994||Intel Corporation||Method and apparatus for decoding conditional jump instructions in a single clock in a computer processor|
|US5363322||Apr 2, 1991||Nov 8, 1994||Motorola, Inc.||Data processor with an integer multiplication function on a fractional multiplier|
|US5386563||Oct 13, 1992||Jan 31, 1995||Advanced Risc Machines Limited||Register substitution during exception processing|
|US5392408||Sep 20, 1993||Feb 21, 1995||Apple Computer, Inc.||Address selective emulation routine pointer address mapping system|
|US5404472||Nov 10, 1993||Apr 4, 1995||Hitachi, Ltd.||Parallel processing apparatus and method capable of switching parallel and successive processing modes|
|US5416739||Mar 17, 1994||May 16, 1995||Vtech Computers, Ltd.||Cache control apparatus and method with pipelined, burst read|
|US5420992||Apr 5, 1994||May 30, 1995||Silicon Graphics, Inc.||Backward-compatible computer architecture with extended word size and address space|
|US5475824||Feb 10, 1995||Dec 12, 1995||Intel Corporation||Microprocessor with apparatus for parallel execution of instructions|
|US5481684||Jul 20, 1994||Jan 2, 1996||Exponential Technology, Inc.||Emulating operating system calls in an alternate instruction set using a modified code segment descriptor|
|US5481693||Jul 20, 1994||Jan 2, 1996||Exponential Technology, Inc.||Shared register architecture for a dual-instruction-set CPU|
|US5524211||Mar 25, 1993||Jun 4, 1996||Hewlett Packard Company||System for employing select, pause, and identification registers to control communication among plural processors|
|US5542059||Dec 21, 1994||Jul 30, 1996||Exponential Technology, Inc.||Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order|
|US5561810||May 15, 1995||Oct 1, 1996||Nec Corporation||Accumulating multiplication circuit executing a double-precision multiplication at a high speed|
|US5568646||Sep 19, 1994||Oct 22, 1996||Advanced Risc Machines Limited||Multiple instruction set mapping|
|US5574928||Apr 26, 1994||Nov 12, 1996||Advanced Micro Devices, Inc.||Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments|
|US5583804||Jan 27, 1995||Dec 10, 1996||Advanced Risc Machines Limited||Data processing using multiply-accumulate instructions|
|US5598546||Aug 31, 1994||Jan 28, 1997||Exponential Technology, Inc.||Dual-architecture super-scalar pipeline|
|US5600845||Jul 27, 1994||Feb 4, 1997||Metalithic Systems Incorporated||Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor|
|US5606714||Dec 1, 1995||Feb 25, 1997||National Semiconductor Corporation||Integrated data processing system including CPU core and parallel, independently operating DSP module and having multiple operating modes|
|US5630083||Jul 3, 1996||May 13, 1997||Intel Corporation||Decoder for decoding multiple instructions in parallel|
|US5630153||Oct 4, 1994||May 13, 1997||National Semiconductor Corporation||Integrated digital signal processor/general purpose CPU with shared internal memory|
|US5638525||Feb 10, 1995||Jun 10, 1997||Intel Corporation||Processor capable of executing programs that contain RISC and CISC instructions|
|US5642516||Oct 14, 1994||Jun 24, 1997||Cirrus Logic, Inc.||Selective shadowing of registers for interrupt processing|
|US5664147||Aug 24, 1995||Sep 2, 1997||International Business Machines Corp.||System and method that progressively prefetches additional lines to a distributed stream buffer as the sequentiality of the memory accessing is demonstrated|
|US5666355||Mar 26, 1996||Sep 9, 1997||Interdigital Technology Corporation||Power consumption control method and apparatus for a communication system subscriber unit|
|US5671422||Mar 28, 1995||Sep 23, 1997||Intel Corporation||Method and apparatus for switching between the modes of a processor|
|US5689672||Oct 29, 1993||Nov 18, 1997||Advanced Micro Devices, Inc.||Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions|
|US5692152||May 14, 1996||Nov 25, 1997||Exponential Technology, Inc.||Master-slave cache system with de-coupled data and tag pipelines and loop-back|
|US5701493||Aug 3, 1995||Dec 23, 1997||Advanced Risc Machines Limited||Exception handling method and apparatus in data processing systems|
|US5740461||Oct 22, 1996||Apr 14, 1998||Advanced Risc Machines Limited||Data processing with multiple instruction sets|
|US5758115||Jun 7, 1995||May 26, 1998||Advanced Risc Machines Limited||Interoperability with multiple instruction sets|
|US5781750 *||Jan 11, 1994||Jul 14, 1998||Exponential Technology, Inc.||Dual-instruction-set architecture CPU with hidden software emulation mode|
|US5784585||Apr 5, 1995||Jul 21, 1998||Motorola, Inc.||Computer system for executing instruction stream containing mixed compressed and uncompressed instructions by automatically detecting and expanding compressed instructions|
|US5784636||May 28, 1996||Jul 21, 1998||National Semiconductor Corporation||Reconfigurable computer architecture for use in signal processing applications|
|US5796973||Aug 6, 1997||Aug 18, 1998||Advanced Micro Devices, Inc.||Method and apparatus for decoding one or more complex instructions into concurrently dispatched simple instructions|
|US5968161||Feb 7, 1997||Oct 19, 1999||Altera Corporation||FPGA based configurable CPU additionally including second programmable section for implementation of custom hardware support|
|US5970254||Jun 27, 1997||Oct 19, 1999||Cooke; Laurence H.||Integrated processor and programmable data path chip for reconfigurable computing|
|US6496922 *||Oct 31, 1994||Dec 17, 2002||Sun Microsystems, Inc.||Method and apparatus for multiplatform stateless instruction set architecture (ISA) using ISA tags on-the-fly instruction translation|
|EP0109567A2||Oct 21, 1983||May 30, 1984||International Business Machines Corporation||Accelerated instruction mapping external to source and target instruction streams for near realtime injection into the latter|
|EP0169565A2||Jul 25, 1985||Jan 29, 1986||Nec Corporation||Microprocessor compatible with any software represented by different types of instruction formats|
|EP0199173A2||Apr 8, 1986||Oct 29, 1986||Hitachi, Ltd.||Data processing system|
|EP0306920A2||Sep 7, 1988||Mar 15, 1989||Nec Corporation||Data processor having expanded operating functions|
|EP0324308A2||Nov 8, 1988||Jul 19, 1989||International Business Machines Corporation||Method and system for decoding plural incompatible format instructions|
|EP0758464A1||Feb 15, 1995||Feb 19, 1997||Advanced Risc Machines Ltd.||Data processing with multiple instruction sets|
|GB2016755A||Title not available|
|GB2284492A||Title not available|
|JPH0476626A||Title not available|
|JPH0683615A||Title not available|
|JPH03150633A||Title not available|
|JPH05265751A||Title not available|
|JPH07281890A||Title not available|
|JPS583040A||Title not available|
|JPS647129A||Title not available|
|JPS5240826A||Title not available|
|JPS5268340A||Title not available|
|JPS6225334A||Title not available|
|JPS58155457A||Title not available|
|JPS62151938A||Title not available|
|JPS62262146A||Title not available|
|JPS63111533A||Title not available|
|WO1997024660A1||Dec 20, 1996||Jul 10, 1997||Advanced Micro Devices Inc||A microprocessor configured to switch instruction sets upon detection of a plurality of consecutive instructions|
|1||"Instruction-Processing Optimization Techniques for VSLI Microprocessors", by John David Bunda, Ph.D. Dissertation, University of Texas at Austin, May 1993.|
|2||Clark et al., IEEE Transactions on Computers, vol. 30, (10) 1981, "Memory System of a High-Performance Personal Computer", 715-722.|
|3||Declaration of Dr. Earl E. Swartzlander, Jr., Nov. 1, 2001.|
|4||Declaration of Professor Alan Jay Smith, Oct. 17, 2001.|
|5||Defendant picoTurbo, Inc.'s Response to Plaintiff ARM's Second Set of Interrogatories, Aug. 18, 2000.|
|6||Defendant picoTurbo's Civil L.R. 16-9(b)(1)-(4) Response Chart Concerning U.S. Patent No. 6,021,265, ARM Limited v. picoTurbo, Inc., Case No. C-00-00957 (N.D. Calif., Dec. 22, 2000).|
|7||Defendant picoTurbo's Civil L.R. 16-9(b)(1)-(4) Supplemental Responses U.S. Patent Nos. 5,740,461, 5,568,646, 5,758,115, 6,021,265, and 5,583,804, May 17, 2001.|
|8||Defendant picoTurbo's Motion for Summary Judgment on Issues of Patent Invalidity, Oct. 23, 2001.|
|9||Defendant picoTurbo's Response Brief on Claim Construction, Mar. 15, 2001.|
|10||Expert Report: Professor Alan Jay Smith, Aug. 31, 2001.|
|11||IBM Technical Disclosure Bulletin by J.C. Kemp, entitled: "Instruction Translator" vol. 15, No. 3 published Aug. 1972, p. 920.|
|12||IBM Technical Disclosure Bulletin by P.F. Smith, entitled: "Extended Control for Microprocessors" vol. 17 No. 11 published Apr. 1975, pp. 3438-3441.|
|13||IBM Technical Disclosure Bulletin entitled: "Oncode Remap and Compression in Hard-Wired Risc Microprocessor" vol. 32 No. 10A published Mar. 1990, p. 349.|
|14||Initial Disclosure by Defendant picoTurbo, Inc. of Prior Art Under Local Rule 16-7, Case C00-00957CW, Aug. 14, 2000.|
|15||Joint Designation of Disputed Terms for Claim Construction, Feb. 5, 2001.|
|16||Memorandum of Points and Authorities in Support of Plaintiff ARM's Opposition and Cross Motion for Summary Judgment that the Patents-in-Suit are not Invalid, Nov. 2, 2001.|
|17||Order Construing Disputed Claims and Terms, ARM Limited v. picoTurbo, Inc., Case No. C-00-00957 (N.D. Calif., Jun. 15, 2001)(Wilken, J.).|
|18||picoTurbo's Reply in Support of Motion for Summary Judgment on Invalidity and Opposition to ARM's Cross-Motion, Nov. 9, 2001.|
|19||picoTurbo's Third Supplemental Response Charts, Aug. 31, 2001.|
|20||Plaintiff ARM's Opening Brief on Claim Construction, Mar. 1, 2001.|
|21||Plaintiff ARM's Reply Brief on Claim Construction, Mar. 22, 2001.|
|22||Plaintiff ARM's Reply in Support of its Opposition and Cross Motion for Summary Judgment that the Patents-in-Suit are not Invalid.|
|23||Plaintiff ARM's Response to picoTurbo, Inc.'s First Set of Interrogatories to ARM, Limited, Aug. 14, 2000 (Interrogatories 1 and 2 only).|
|24||Rebuttal Expert Report of Dr. Earl E. Swartzlander, Jr., Sep. 20, 2001.|
|25||Second Supplement to Defendant picoTurbo's Civil L.R. 16-9(b)(1) Response Charts, Jun. 6, 2001.|
|26||Supplemental Declaration of Professor Alan Jay Smith, Nov. 8, 2001.|
|U.S. Classification||712/209, 712/210|
|International Classification||G06F9/318, G06F9/30, G06F9/38, G06F9/32, G06F9/42|
|Cooperative Classification||G06F9/321, G06F9/30181, G06F9/30196, G06F9/3822|
|European Classification||G06F9/30X8, G06F9/38C4, G06F9/32A, G06F9/30X|