|Publication number||USRE43326 E1|
|Application number||US 11/802,763|
|Publication date||Apr 24, 2012|
|Filing date||May 24, 2007|
|Priority date||Dec 15, 1999|
|Also published as||US6368933, US6388315, US20020026261, US20020031894, USRE42776|
|Publication number||11802763, 802763, US RE43326 E1, US RE43326E1, US-E1-RE43326, USRE43326 E1, USRE43326E1|
|Inventors||Lawrence T. Clark, Vikas R. Amrelia, Raphael A. Soetan, Eric J. Hoffman, Tuan X. Do|
|Original Assignee||Marvell International Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Non-Patent Citations (2), Classifications (21), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to semiconductors and, more particularly, to semiconductor fabrication.
Semiconductors form the basis of most integrated circuits. Integrated circuits are typically built from standard cell circuits. A standard cell circuit may include an AND gate, a NAND gate, or an inverter, to name just a few.
Each standard cell circuit is typically made up of a number of transistors. An integrated circuit may therefore include hundreds, thousands, or even millions of transistors.
The processes used to manufacture semiconductors employ smaller and smaller line widths and features which are scaled down in order to increase the number of transistors per die. Furthermore, the power supply levels are collapsed to lower and lower voltages. For deep sub-micron processes, power supply levels may be decreased to keep electrical or electromagnetic fields from punching through the channel region of the transistors. These deep sub-micron processes may be employed, for example, in digital signal processing, or DSP, applications such as cellular technology, to minimize battery discharge levels.
Such deep sub-micron processes, however, leak current while the transistors are off because the threshold voltages for these devices are lowered. As the leakage current increases, the power consumed (or, more correctly, wasted) by the leaking transistor also increases.
To address the leakage problem, additional voltage supply rails may be added to the integrated circuit design. The supply rails may be used to reverse-bias the bulk-to-source junction of the transistor, for example. However, the additional power rails may present other challenges for the design of the integrated circuit.
Thus, there is a continuing need for an efficient design of an integrated circuit which includes additional power rails.
A bulk terminal 54 is a heavily doped p-type region which is formed in the p-type substrate 40. The bulk terminal 54 sets the potential of the p-type substrate 40, ostensibly to prevent leakage from the source region 36 and the drain region 32. The bulk terminal 54 is known as a tap cell 56 or a spacer cell 56.
The tap cell 56 is used to set the potential of the substrate 40, to prevent leakage from the source region 36 and the drain region 32 into the p-type substrate 40. The tap cell 56 of
A power rail 50, with a potential, Vss, is connected both to the source 32 and the bulk terminal 54. The voltage between the source 32 to the bulk terminal 54, or Vsb, for the transistor 30 is thus close to zero.
A bulk terminal 74 is a heavily doped n-type region formed into the n-type well 68. The bulk terminal 74 sets the potential of the n-type well 68, to minimize leakage from the source region 62 and the drain region 64 into the n-type well 68. Like the bulk terminal 56, the bulk terminal 74 is also a tap cell, known as a “well tap.”
A second power rail 70, with a potential, Vdd, is connected to both the source 62 and the bulk terminal 74. The voltage between the source 62 to the bulk terminal 74, or Vsb, for the transistor 60 is thus close to zero.
An integrated circuit may include many logic circuits which are built from both n-type MOSFETs 30 and p-type MOSFETs 60. For example, a logic complementary metal-oxide-semiconductor, or CMOS, inverter may be formed by connecting the gates of both an n-type MOSFET 30 and a p-type MOSFET 60. In operation, one transistor is biased on while the other transistor is biased off.
When the source-to-drain voltage (Vsd) across a deep sub-micron CMOS device is at the full rail value and the voltage between the source and the bulk (Vsb) of the device is zero volts, leakage from the CMOS device may be considerable.
To address this phenomenon, the source-to-bulk voltage, Vsb, may be adjusted such that Vsb is no longer zero. For an n-type device, if a positive Vsb is created, then a body effect is induced. Body effect is the variation in the threshold voltage, Vt, resulting from a change to the source-to-bulk voltage, Vsb. Thus, by increasing Vsb, an increase in the threshold voltage (Vt) of the device may result. Persons of ordinary skill in the art will recognize that sub-threshold leakage has a strong inverse exponential relationship to Vt. Therefore, this increase in the threshold voltage, Vt, causes the sub-threshold leakage to drop dramatically.
Likewise, for p-type devices, the source-to-bulk voltage, Vsb, may be made negative. Accordingly, a body effect for the p-type device is invoked, thus increasing the value of the threshold voltage, Vt, of the device. The sub-threshold leakage of the p-type device may thus be reduced.
In an integrated circuit which includes the power rails 50 and 70, for example, each cell circuit may be connected to both power rails. Such may be the case in a CMOS cell circuit, for example. The substrate tap 56 of
Likewise, a well tap 76 may be available to every p-type MOSFET 60 in a CMOS integrated circuit design, for example. A heavily doped n-type region 74 may be formed into the n-type well 68 which may traverse a number of p-type MOSFETs 60. Since the power rail 70 is connected to every cell circuit, a metal line 72 may be connected from the power rail 70 to the heavily doped n-type region 74. The heavily doped n-type region 74 is added without extending the cell circuit area and with minimal use of metal.
The two additional power rails 58 and 78, however, are not supplied to the standard cell circuits of the integrated circuit. Thus, in one embodiment of the invention, the tap cells 56 are removed from each cell circuit. Alternatively, the metal connected to the tap cells 56, either the metal line 72 connected to the heavily doped n-type region 72 for the well tap 76 or the metal line 52 connected to the heavily doped p-type region 52 for the substrate tap 56, may be removed from the design of each cell circuit.
Once removed from the design as part of the cell circuits, substrate tap cells 56a and well tap cells 76a may be included in the integrated circuit design. Because Vsssupp and Vddsupp are not supplied to the cell circuits, the new tap cells 56a and 76a may be placed outside the cell circuits. Substrate tap cells 56a may be connected to Vsssupp while well tap cells 76a may be connected to Vddsupp, as needed, throughout the integrated circuit.
A single substrate tap cell 56a may set the potential of the p-type substrate 40 for some distance, biasing the substrate 40 for a number of cell circuits. Likewise, a single well tap cell 76a may bias the n-type well 68 for many cell circuits. In one embodiment of the invention, tap cells placed approximately 55 microns apart are effective to bias the substrate 40 and the well 68.
Because the tap cells are no longer contained inside the cell circuits, they may no longer be “close” to the associated power rails. Thus, metal lines 52 and 72 connect the power rails 58 and 78 to the tap cells 56a and 76a, respectively. However, the amount of metal available for connection between the various components of the integrated circuit is finite and, in some cases, may be a constraint on the available size of the circuit.
Typically, in designing integrated circuits, it is desirable to minimize the track length, e.g., the amount of metal used to connect circuits. Short tracks are generally less susceptible to interference and cross-talk, have lower parasitic reactances, and radiate less energy.
In the integrated circuit 100a, each standard cell 90 is connected to both the power rails 50 and 70. These connections supply the voltages for operation of the transistors inside each standard cell circuit 90.
In order for connections between circuits to be made, regions are etched out of layers of the various semiconductor materials. Metal is then placed in the etched regions, such that components may be connected. The metal is typically fabricated in multiple layers, known as M1, for the first metal layer, M2, for the second metal layer, and so on. The metal layers may be connected by vertical connections, known as vias.
As described above, the well tap 56a biases the n-type well 68 (
Feed-throughs are pre-determined routes for the placement of designated signals, such as the power rails 58 and 78. Instead of leaving the placement of the tap cells 80 to be determined by the automatic placement tool, the feed-throughs 58a and 78a indicate where the power rails 58 and 78 will subsequently be placed. Because the automatic placement tool “knows” where the power rails 58 and 78 will be, the tool may place the tap cells 80 close to these power rails 58 and 78. The effect is to avoid excessive use of metal for connection between the tap cells 80 and the power rails 58 and 78.
The separate feed-throughs 58a for the voltage Vsssupp 58 are placed a distance 122 apart. The feed-throughs 78a for the voltage Vddsupp 78 may likewise be placed the distance 122 apart. In one embodiment of the invention, the distance 122 is approximately 55 microns. Recall that the tap cells 80 may be optimally placed about 55 microns apart to effectively bias the substrate 40 and the well 68. Thus, the placement of the feed-throughs 58a and 78a may result both in fewer tap cells 80 and in shorter metal lines for routing to the tap cells 80.
In one embodiment of the invention, the Vsssupp and the Vddsupp signals are routed in the metal 3 layer rather than in the metal 2 layer. The metal 2 layer may thus be reserved for the primary Vss and Vdd signals, which are wider and which provide power to each cell circuit 90.
A typical integrated circuit may include multiple metal layers. For example, a circuit may include a first metal layer, M1, a second metal layer, M2, a third metal layer, M3, a fourth metal layer, M4, a fifth metal layer, M5, and so on, as needed.
Each metal layer may be thought of as a sheet of metal, with all layers being parallel to one another. However, the metal lines for each layer may run orthogonally to the metal lines for adjacent layers. Thus, if the metal lines in M1 run in one direction, the metal lines in M2 run orthogonally to the metal lines in M1, and the metal lines in M3 run orthogonally to the metal lines in M2, which are thus parallel to the metal lines in M1. The different metal layers may be connected, as needed, by vias. Vias are vertical connections between the metal layers.
However, the tap cells 80 are connected to the power rails 58 and 78. The metal line 84 connecting to the tap cell 80 is formed in the M2 layer. The via 86, a vertical connector of two metal layers, connects the metal line 84 (in M2) to the power rail 58 (in M3). In the cross-sectional view of
Another fabrication issue arises from the addition of the power rails 58 and 78. Recall that, in conventional integrated circuit designs, the p-type substrate 40 is biased with the power rail 50 (
The likelihood of destroying the transistor 132 may be predicted by calculating the area of the line 130, the area of the gate 134, and taking a ratio of the two. In one process technology, if the ratio exceeds a predetermined value, the transistor 132 may be destroyed.
The electrostatic discharge problem, however, does not arise if the charge being built up on the line 130 has a path to the p-type substrate 40 (which is, in effect, ground). In
The power rails 58 and 78, however, bias the p-type substrate 40 differently. The p-type substrate 40 is no longer biased to Vss, but instead is biased to Vsssupp.
Conventionally, a node area check, or NAC, protection device, may be incorporated into a design to prevent electrostatic discharge from destroying one or more transistors during fabrication. However, conventional design tools such as automatic routing tools may not properly determine where NAC protection devices are appropriate, particularly where additional power rails 58 and 78 are used.
Accordingly, in one embodiment of the invention, NAC protection devices are incorporated into the tap cells 80. Looking back to
In addition to reducing leakage from the transistors, the tap cell 80 may be used for protection against electrostatic buildup during the fabrication of the integrated circuit 120. Turning to
The drain of a transistor 88a is connected to the power rail 78. The source of the transistor 88a is connected to the power rail 70, which runs orthogonally to the power rail 78, in one embodiment of the invention. Using the NAC protection device 88a during the fabrication process, a transistor to which connections are etched has a path from the power rail 70 to the power rail 78.
The tap cell 80 also includes a second NAC protection device 88b. The NAC protection device 88b is connected to the power rail 58 at the drain. The source is connected to the power rail 50. During fabrication, any standard cell connected to the power rail 50 has a path to the power rail 58, thus preventing a transistor from being destroyed due to electrostatic buildup.
The NAC protection device 88b, however, provides a path for the electrostatic discharge to follow. By making a connection between the power rail 50 and the power rail 58, the built-up current may discharge to the p-type substrate 40. The gates 142a and 144a are thus protected.
Thus, in accordance with some embodiments of the invention, in an integrated circuit design, tap cells are placed outside of cell circuits for connection to power rails which do not connect to the cell circuits. The tap cells may bias the substrate and the well. Feed-throughs for the power rails are provided for efficient automatic placement of the tap cells as well as efficient use of metal for connecting the tap cells to the new power rails. Additional transistors are placed inside the tap cells, where needed, such that electrostatic charge built up during fabrication does not destroy gate dielectrics.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5492856||Jun 2, 1995||Feb 20, 1996||Ikeda; Takeshi||Method of forming a semiconductor device having a LC element|
|US6157070||Feb 23, 1998||Dec 5, 2000||Winbond Electronics Corporation||Protection circuit against latch-up in a multiple-supply integrated circuit|
|1||Neil H. E. Weste Kamran Eshraghian, "Principles of CMOS VSLI Design, A Systems Perspective," 2nd Ed., pp. 51, 54-55, 1994.|
|2||Robert F. Pierret, "Semiconductor Device Fundamentals with Computer-Based Exercises Homework Problems," pp. 680-681, 1996.|
|U.S. Classification||438/395, 307/147, 307/58, 438/394, 361/637, 361/639, 438/393, 307/148, 361/638|
|International Classification||H01L23/528, H01L21/20, H01L27/118, H01L27/02|
|Cooperative Classification||Y10T307/582, H01L27/0203, H01L27/118, H01L2924/0002, H01L23/5286|
|European Classification||H01L27/118, H01L27/02B, H01L23/528P|