|Publication number||USRE43378 E1|
|Application number||US 12/288,359|
|Publication date||May 8, 2012|
|Priority date||Sep 27, 2002|
|Also published as||US7124392, US20040133869|
|Publication number||12288359, 288359, US RE43378 E1, US RE43378E1, US-E1-RE43378, USRE43378 E1, USRE43378E1|
|Inventors||Sunil Kumar Sharma|
|Original Assignee||Sicronic Remote Kg, Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Non-Patent Citations (10), Classifications (10), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority from Indian patent application No. 993/Del/2002, filed Sep. 27, 2002, which is incorporated herein by reference.
This invention relates to an improved method and system for mapping an electronic circuit to a programmable logic device (PLD). In particular, the invention relates to the utilization of cascade logic elements while mapping.
Programmable Logic Devices (PLDs) provide the capability of implementing a wide range of electronic circuits using the same physical device. This capability is exploited by configuring the device appropriately for each desired application. The configuring process involves the mapping of the target circuit onto the available resources of the PLD. Programmable Gate Arrays (PGAs) and Field Programmable Gate Arrays (FPGAS) are the most widely used PLDs. The architecture of these devices incorporates Look Up Tables (LUTS) that are configured for desired functionality. The efficiency of mapping algorithms is critical to the effective utilization of PGAs and FPGAs. In LUT-based FPGAs the mapping is implemented on the LUTs.
The conventional LUT-based FPGA mapping algorithms can be divided into two classes. The algorithms in the first class emphasize the minimization of the number of LUTs in the solution. This class includes “Chortle” and “Chortle-crf” algorithms by Francis, based on tree decomposition and bin packing techniques. The algorithms in the second class emphasize the minimization of the delay of the solution. This class includes “Flowmap” by Cong and Y. Ding, which use flow based techniques in mapping with node duplication to reduce the logical depth of the mapped netlist. See Jason Cong and Yuzheng Ding; An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs; IEEE Trans. On Computer Aided Design of Integrated Circuits and Systems CAD, Vol. 13, pp 1-12 Jan. 1994.
A DAG-map (Direct Analysis Graph) method for FPGA technology mapping for delay optimization has been proposed by J. Cong et.al. See Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew Kahng, Peter Trajmar; DAG-Map: Graph Based FPGA Technology Mapping For Delay Optimization; IEEE Design and test of computers, pp 7-20, September 1992. This method utilizes a graph based technology mapping algorithm “DAG-Map”, for delay optimization in lookup-table based FPGA designs. The algorithm carries out technology mapping and delay optimization on the entire Boolean network. As a preprocessing step in “DAG-Map”, a general algorithm transforms an arbitrary n-input network into a two-input network with a corresponding increase in the network depth; Finally, a graph matching based technique which performs area optimization without increasing the network delay is used as a post processing step for “DAG-Map”. This method does not however utilize the cascade elements available with each LUT in the FPGA.
Another optimal technology mapping algorithm for delay optimization in Lookup -Table based FPGA Designs has been proposed by Jason Cong et. al. See Jason Cong and Yuzheng Ding; An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs; IEEE Trans. On Computer Aided Design of Integrated Circuits and Systems CAD, Vol. 13, pp 1-12 January 1994. This method proposes a polynomial time technology-mapping algorithm, called “Flow-Map”, that optimally solves the LUT-based FPGA technology-mapping problem for depth minimization for general Boolean networks. A key step in “Flow-Map” is the computation of a minimum height K-feasible cut in a network, by network flow computation. This algorithm does effectively minimize the number of LUTs by maximizing the volume of each cut and by several post processing operations but it does not utilize the cascade elements with the LUT to further reduce the size of the logic.
A method for On Area/Depth Trade-off in LUT-Based FPGA Technology mapping has been disclosed in reference by Jason Cong and Yuzheng Ding. Jason Cong and Yuzheng Ding; On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping; 30th ACM/IEEE design Automation Conference (DAC), pp. 213-218, 1993. In this method the area and depth trade off in LUT based FPGA technology mapping is proposed by performing a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous for subsequent re-mapping for area minimization. The resulting network is then re-mapped to obtain an area-minimized mapping solution. By gradually increasing the depth bound for each design a set of mapping solutions with smooth area and depth trade-off is achieved. For the area minimization step, an optimal algorithm for computing an area-minimum mapping solution without node duplication is developed. However this method also does not talk about the area minimization by utilizing the cascade elements with each LUT.
Another method proposed by Jason Cong and Yuzheng Ding proposes an integrated approach to synthesis and mapping that extends the combinatorial limit set up by the depth-optimal “Flow Map” algorithm. See Jason Cong and Yuzheng Ding; Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs; IEEE/ACM International Conference on Computer Aided Design (IC-CAD), pp. 110-114, November 1993. The new algorithm, “FlowSYN”, uses global combinatorial optimization techniques to guide the Boolean synthesis process during depth minimization. The combinatorial optimization is achieved by computing a series of minimum cuts of fixed heights in a network based on fast network flow computation, and the Boolean optimization is achieved by efficient OBDD-based implementation of functional decomposition. This method also does not utilize cascade elements.
One aspect of this invention is to provide an algorithm for efficiently synthesizing electronic circuits by utilizing cascade elements in LUT-based FPGAs.
Another aspect of the invention is to provide a method and mechanism for maximum utilization of on-chip resources in LUT-based FPGAs hence reducing the area in logic device.
Yet another aspect of the invention is to provide a method for synthesizing a logic circuit with minimum depth in LUT-based FPGAs.
It is yet another aspect of the invention to provide a method for realizing faster LUT-based FPGA implementation.
The described embodiments of this invention provide an improved method for mapping an electronic digital circuit to a Look Up table (LUT) based Programmable Logic Device (PLD). The method operates by selecting an unmapped or partially mapped LUT, and identifying a group of circuit elements for mapping on the selected LUT based on the available capacity of the selected LUT and the mapping constraints. The identified circuit elements are then mapped onto the selected LUT. The identification of circuit elements and mapping is carried out while taking into consideration the Cascade Logic associated with the selected LUT. The process is continued until all the circuit elements have been mapped. The group of circuit elements is mapped to the cascade logic prior to mapping on the LUTs. Conversely, the cascade logic is incorporated only after either all circuit elements have initially been mapped onto LUTs or some circuit elements remain unmapped even after all LUTs have been utilized. The mapping constraints include timing constraints, placement constraints, and size constraints.
The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
The following description is based on the definition of technical terms given below:
Electronic design includes the logical structure of an electronic device such as an integrated circuit. This may be specified either as a behavioral description, as high-level Boolean equations, a circuit schematic or in any other form representing the logical arrangements of a device. It may include different constraints such as timing constraints, placement constraints, or mapping constraints, etc.
A Target hardware device includes the hardware device on which an electronic design is implemented. In context of this invention, a target hardware device typically includes the symmetric array of uncommitted logic elements. The uncommitted elements consist of the LUT, cascade gate, MUXes and flip-flops. These elements are grouped to form another hierarchy called programmable logic blocks, which are again grouped to form a programmable logic device.
A Compiler includes software and hardware on which the software operates for compiling the electronics design. The function of the compiler is to synthesize the netlist and map the netlist (design) to the target device.
Mapping refers to the process of grouping gates from a gate netlist or other hardware independent representation of logic into a logic block. In other words, the logic design may be divided into clusters representing the various logic functions within the design. These clusters are mapped onto the uncommitted logic elements in the programmable logic device during the compilation of the electronic design. The conditions for grouping (mapping) the gates into logic cells is that it should be possible to implement the grouped gates in the logic cell, For example, if a four input LUT is taken as a logic cell then the grouped gates must have less than or equal to four inputs for successful mapping.
Embodiments of the present invention utilize cascade elements during the hardware description language (HDL) compilation and maps the design for programmable integrated circuits during technology mapping.
In the accompanying diagrams (
Another method that can be applied for extracting the cascade chains is:
Since the cascade element is a single universal gate (NAND or NOR) certain constraints have to be observed while mapping gates onto the cascade element. These constraints can be divided into two groups.
The first group of conditions that need to be verified when starting a new cascade chain are:
The second set of conditions that are needed to be verified while the cascade chain is being formed are:
This process of utilizing the cascade elements while mapping a logic circuit onto target architecture is independent of the algorithm used for LUT synthesis. This method provides an optimal solution superior to existing methods without any extra traversal of the gate level netlist.
A programmable logic device programmed in accordance with the described embodiments of the present invention can be included in a variety of electronic systems, such as a computer system or an embedded system.
It will be apparent to those with ordinary skill in the art that the foregoing is merely illustrative and not intended to be exhaustive or limiting, having been presented by way of example only and that various modifications can be made within the scope of the present invention.
Accordingly, this invention is not to be considered limited to the specific examples chosen for purposes of disclosure, but rather to cover all changes and modifications, which do not constitute departures from the permissible scope of the present invention. The invention is therefore not limited by the description contained herein or by the drawings, but only by the claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5946219||Oct 30, 1996||Aug 31, 1999||Atmel Corporation||Method and system for configuring an array of logic devices|
|US6212670||Sep 1, 1998||Apr 3, 2001||Agilent Technologies, Inc.||Method for implementing a programmable logic device having look-up table and product-term circuitry|
|US6216257||Jun 26, 2000||Apr 10, 2001||Vantis Corporation||FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks|
|US6336208||Feb 4, 1999||Jan 1, 2002||Xilinx, Inc.||Delay optimized mapping for programmable gate arrays with multiple sized lookup tables|
|US6470485||Oct 18, 2000||Oct 22, 2002||Lattice Semiconductor Corporation||Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device|
|US6490717||Aug 15, 2000||Dec 3, 2002||Altera Corporation||Generation of sub-netlists for use in incremental compilation|
|US6725442||Sep 4, 2002||Apr 20, 2004||Lattice Semiconductor Corporation||Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device|
|US7124392||Sep 29, 2003||Oct 17, 2006||Stmicroelectronics, Pvt. Ltd.||Mapping of programmable logic devices|
|1||Chen, et al., "DAG Map: Graph Based FPGA Technology Mapping For Delay Optimization:", IEEE Design and test of computers, (Sep. 1992),pp. 7-20.|
|2||Cong, Jason at al., "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping", 30th ACM/IEEE design Automation Conference (DAC), (1993),pp. 213-218.|
|3||Cong, Jason et al., "An Optimal Tchnology Mapping Algorithm for delay optimization in lookup-table based FPGA Designs", IEEE Trans. on Computer aided design of Inergrated circuits and systems CAD, vol. 13, (Jan. 1994),pp. 1-7.|
|4||Cong, Jason et al., "Beyond the Combinatorial Limit Depth Minimization for LUT-Based FPGA Designs", IEEE/ ACM International Conference on Computer Aided Design (ICCAD), (Nov. 1993),pp. 110-114.|
|5||Jason Cong and Yuzheng Ding; An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs; IEEE Trans. On Computer Aided Design of Integrated Circuits and Systems CAD, vol. 13, pp. 1-12 Jan. 1994.|
|6||Jason Cong and Yuzheng Ding; Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs; IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 110-114, Nov. 1993.|
|7||Jason Cong and Yuzheng Ding; On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping, 30th ACM/IEEE design Automation Conference (DAC), pp. 213-218, 1993.|
|8||Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew Kahng, Peter Trajmar; DAG-Map: Graph Based FPGA Technology Mapping For Delay Optimization; IEEE Design and test of computers, pp. 7-20, Sep. 1992.|
|9||Non-final Office Action issued in U.S. Appl. No. 10/675,908 and mailed Oct. 18, 2005.|
|10||Notice of Allowance issued in U.S. Appl. No. 10/675,908 and mailed May 15, 2006.|
|U.S. Classification||716/116, 326/37, 326/38, 716/104, 716/117|
|International Classification||H03K19/173, G06F17/50, G06F7/38|
|Apr 12, 2011||AS||Assignment|
Owner name: SICRONIC REMOTE KG, LLC, DELAWARE
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|Nov 6, 2012||CC||Certificate of correction|
|Mar 26, 2014||FPAY||Fee payment|
Year of fee payment: 8
|Nov 2, 2015||AS||Assignment|
Owner name: MINERAL LASSEN LLC, NEVADA
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