|Publication number||USRE43404 E1|
|Application number||US 12/728,630|
|Publication date||May 22, 2012|
|Filing date||Mar 22, 2010|
|Priority date||Mar 7, 1996|
|Also published as||US5834339, US6107123, US6458681, US6653172, US6780747, US20020094671, US20030027373|
|Publication number||12728630, 728630, US RE43404 E1, US RE43404E1, US-E1-RE43404, USRE43404 E1, USRE43404E1|
|Inventors||Thomas H. DiStefano, Joseph Fjelstad|
|Original Assignee||Tessera, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (105), Non-Patent Citations (28), Classifications (41), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation application of application Ser. No. 09/188,599 filed Nov. 9, 1998, now U.S. Pat. No. 6,107,123, which is a divisional application of application Ser. No. 08/610,610 filed Mar. 7, 1996, now U.S. Pat. No. 5,834,339.
The present invention relates to the field of semiconductor chip packaging.
In the construction of semiconductor chip assemblies, it has been found desirable to interpose encapsulating material between and/or around elements of the semiconductor assemblies in an effort to reduce and/or redistribute the strain and strain on the connections between the semiconductor chip and a supporting circuitized substrate during operation of the chip, and to seal the elements against corrosion.
Ball grid array (“BGA”) packaged and chip scale packaged (“CSP”) semiconductor chips and flip chip attachment solutions are connected to external circuitry through contacts on a surface of the chip. To save area on a supporting substrate, such as a printed wiring board (“PWB”), these chips are directly connected/soldered to the substrates and from there connected to external circuitry on other parts of the substrate. The chip contacts are either disposed in regular grid array patterns, substantially covering the face surface of the chip (commonly referred to as an “area array”) or in elongated rows extending parallel to and adjacent each edge of the chip front surface. Many of the techniques for attachment run into problems because of the thermal expansion mismatch between the material the chip is composed of and the material the supporting circuitized substrate is made of, such as a PWB. In other words, when the chip is in operation, the chip heats up and also heats its supporting substrate thereby causing both the chip and the substrate to expand. When the heat is removed, the chip and substrate both contract. This heating and cooling process is referred to as “thermal cycling”. Since the heat is being generated in the chip, the chip will heat up more quickly and will typically get hotter than its supporting substrate. The materials comprising both the chip and the substrate have inherent expansion and contraction rates, referred to as their coefficients of thermal expansion (“CTE”), which causes them to expand and contract at different rates and in different degrees when subjected to the same thermal conditions. This thermal expansion mismatch between the chips and the substrate places considerable mechanical stress and strain on the connections between the chip contacts and corresponding bond pads on the substrate.
BGA and CSP technology refers to a large range of semiconductor packages which use interconnection processes such as wirebonding, beam lead, tape automated bonding (“TAB”) or the like as an intermediate connection step to interconnect the chip contacts to the exposed package terminals. This results in a device which can be tested prior to mechanical attachment to the bond pads on supporting substrate. The BGA or CSP packaged chips are then typically interconnected with their supporting substrates using standard tin-lead solder connections. In most such packaged devices, the mechanical stress/strain due to thermal cycling is almost completely placed on the solder connections between the chip and the substrate. However, solder was never intended to undergo such forces and commonly under-goes significant elastic solder deformation causing the solder to crack due to fatigue brought on by the thermal cycling. When the solder connections have smaller diameters, thermal cycling has an even more profound fatiguing affect on the solder. This has driven efforts in the packaging art to modify the solder and other elements of the packages so that they may better withstand the thermal cycling forces.
As the features of semiconductor chip packages continue to be reduced in size, as in the case of CSPs, the number of chips packed into a given area will be greater and thus the heat dissipated by each of these chips will have a greater effect on the thermal mismatch problem. Further, the solder cracking problem is exacerbated when more than one semiconductor chip is mounted in a package, such as in a multichip module. As more chips are packaged together, more heat will be dissipated by each package which, in turn, means the interconnections between a package and its supporting substrate will encounter greater mechanical stress due to thermal cycling. Further, as more chips are integrated into multichip modules, each package requires additional interconnections thereby increasing the overall rigidity of the connection between the module and its supporting substrate.
Certain designs have reduced solder connection fatigue by redistributing the thermal cycling stress into a portion of the chip package itself. An example of such a design is shown in U.S. Pat. Nos. 5,148,265 and 5,148,266, the disclosure of which is incorporated herein by reference. One disclosed embodiment of these patents shows the use of a chip carrier in combination with a compliant layer to reduce the CTE mismatch problems. Typically, the compliant layer includes an elastomeric layer which, in the finished package, is disposed between the chip carrier and the face surface of the chip. The compliant layer provides resiliency to the individual terminals, allowing each terminal to move in relation to its electrically connected chip contact to accommodate CTE mismatch as necessary during testing, final assembly and thermal cycling of the device.
In some arrangements used heretofore, the compliant layer was formed by stenciling a thermoset resin onto the chip carrier and then curing the resin. Next, additional resin was applied to the exposed surface of the cured layer, this additional resin was partially cured, and the resulting tacky adhesive surface was used to bond the elastomeric layer to the chip and chip carrier. Once attached, the entire structure was heated and fully cured. Although this process is effective, further improvement would be desirable. The ambient gas can be occasionally entrapped when the chip carrier and die are affixed to the compliant layer. The entrapped gas can create voids and gas bubbles in the encapsulation of the surface of the die by the encapsulation material. These voids/bubbles allow moisture and other contamination to come into direct contact with the surface of the die. Accordingly, care must be taken to prevent such entrapment. This adds to the expense of the process.
In the flip-chip mounting technique, the contact bearing face surface of the chip opposes a bond pad bearing supporting substrate. Each contact on the device is joined by a solder connection to a corresponding bond pad on the supporting substrate, as by positioning solder balls on the substrate or device, juxtaposing the device with the substrate in the front-face-down orientation and momentarily reflowing the solder. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. However, flip-chip assemblies suffer from significant problems when encountering thermal cycling stress because the sole thermal cycling stress bearing elements are the solder connections, as described above in relation to the BGA and CSP packages. In the case of flip chip devices, there is no package to redistribute the thermal cycling stress. Because of this, significant work has been done in the art to make the flip chip solder connections more reliable. However, to keep the chip's standoff from the substrate to a minimum, the solder connections have a typical diameter of between about five and eight thousandths of an inch (“mils”), too small to provide much real mechanical compliance. In an attempt to solve this problem, a curable liquid underfill is flowed between the chip and its attached substrate, enclosing the solder connections. The underfill is then cured into a rigid form which has a CTE that is closely matched to the solder material. The aim of the underfill is to reduce the stress caused by CTE mismatch by redistributing the stress more uniformly over the entire surface of the chip, supporting substrate and solder balls. Examples of the use of underfill materials may be found in U.S. Pat. Nos. 5,120,678, 5,194,930, 5,203,076 and 5,249,101. All of these prior art solutions are aimed at reducing the shear stress endured by the interconnections caused by thermal cycling. However, each of these solutions also encounters significant problems such as insufficient compliancy, voids and process cost. Most significant among these costs is reducing the voiding problem which occurs when the underfill flows between the chip and the substrate and traps gas therebetween. If this gas is not removed, it will typically quickly expand during a heating cycle of the chip. The force associated with the expanding gas can cause the solder connections to crack or otherwise become unreliable. Yet, presently, the underfill process involves a very costly and time-consuming process of allowing the underfill to flow very slowly between the chip and the substrate to try to avoid voids. After the underfill has flowed completely between the chip and the substrate, the assembly will then be subjected to one or more vacuuming steps in a further attempt to remove any voids in the underfill material.
Despite these and other efforts in the art, still further improvements in interconnection technology would be desirable.
The present invention provides a method of eliminating voids and gas bubbles within the encapsulation used in attaching and packaging microelectronic devices which solves the aforementioned problems in the art. The present invention further provides an effective method of filling cavities and channels during encapsulation of a plurality of semiconductor chips formed on a semiconductor wafer.
In one embodiment, the method includes providing a substantially void and bubble free underfill for a semiconductor wafer having a plurality of flip chip assemblies. Typically, a flip chip device is electrically and mechanically attached to a circuitized substrate, such as a PWB, by a plurality of conductive members, which are most typically a plurality of solder balls. These solder balls provide an electrical path from each chip contact to a respective bond pad on the substrate. The solder balls further provide a gap or stand-off between the wafer and hence each flip chip device and its substrate. This gap is then sealed on all sides of the flip chip device with a curable liquid encapsulant so that either a void (vacuum) or an area containing a first gas is thereby created. An isostatic or hydrostatic pressure is then applied to the semiconductor wafer assembly causing the encapsulant to flow into the gap and around the solder balls. An energy is applied to cure the encapsulant once the void/bubble has been completely removed thereby ensuring that new voids and/or bubbles do not re-occur between the flip chip device and the substrate. Typically, heat and/or ultra-violet radiation are used as the applied energy.
In another embodiment of the present invention, the method includes creating a substantially void/bubble free interposer layer between a semiconductor wafer having a plurality of microelectronic components and a sheet-like substrate. According to this method, an interposer layer is injected into a gap between each of the microelectronic components and the substrate such that any voids or gas bubbles are sealed within the gap. Isostatic or hydrostatic pressure is then applied to the entire semiconductor wafer assembly which causes the total volume for the voids/bubbles to be reduced to the point where they are substantially eliminated from the interposer layer. A further step of applying energy, such as heat, is employed to cure the interposer layer thereby ensuring that future voids/bubbles do not occur.
The injecting step may include providing a curable, liquid encapsulant at each edge of the gap between the microelectronic components and the substrate prior to the step of applying pressure, effectively sealing the space between the component and the substrate. When the pressure is then applied, it causes the sealed volume to be reduced thereby allowing the encapsulant to flow into the gap and form a substantially void/bubble free interposer layer.
A still further embodiment of the present invention includes a method of treating an interposer layer for a semiconductor wafer assembly to provide a substantially void/bubble free interposer layer. An interposer layer is first disposed between a semiconductor wafer having a plurality of semiconductor chips and a sheet-like substrate such that any voids within or at the boundaries of the interposer are sealed within the assembly. An isostatic or hydrostatic pressure is then applied to the assembly thereby reducing the volume of the voids/bubbles and substantially eliminating them from the interposer layer.
The foregoing and other objects and advantages of the present invention will be better understood from the following Detailed Description of a Preferred Embodiment, taken together with the attached Figures.
The present invention is directed toward the pressure injection of encapsulants into cavities and gaps in micro-electronic structures and the simultaneous removal of voids and gas bubbles within encapsulants and adhesive/chip attach layers. As described below, the present inventive methods may be used as a method for underfilling attached flip chip devices, for injecting encapsulant and for removing voids and gas bubbles within encapsulants. As will be appreciated by one skilled in the art, each of the embodiments described below could and preferably would be performed on more than one assembly at a time to facilitate the mass production of finished parts.
I. Flip Chip Underfill Encapsulation
As shown in
Isostatic pressure is then applied to the outside of the assembly. This step of applying more pressure on the assembly after the void 140 has been sealed will cause a pressure differential between the compressive, ambient gas applied to the outside of the assembly and any first gas trapped within the void 140. The average diameter of the void 140 will thus be reduced allowing the encapsulant to begin encapsulating the outermost solder connections 110 on all four sides of the chip 100. This pressure differential further causes the encapsulant 130 to flow between the chip and the substrate and around the connections. The amount of pressure required to collapse the void 140 depends on the type of encapsulant 130 used and on the desired time period to entirely collapse the void 140. Typically, if more pressure is used, less time is required to collapse the void 140. The amount of pressure applied may also depend on how the pressure is applied, i.e. all at once in a virtual pressure “step” or gradually in progressively increasing pressure steps. While either pressure application method may be used, using one virtual pressure step increases the rate of collapse of the void 140. By way of example, the applied ambient gas pressure may be approximately between 10 and 1000 pounds per square inch (“psi”) and will be applied for between thirty minutes to several hours; although typically no harm will come to the assembly if it is allowed to remain within the pressurized environment beyond this specified time frame. Such pressure may be supplied by an autoclave device such as has been used in the aerospace industry; although the required size of an autoclave for the removal of voids within encapsulation is typically much smaller than required for the aerospace industry. An example of a possible autoclave device is the Mini-bonder autoclave manufactured by United McGill of Westerville, Ohio.
Eventually, the trapped first gas in the void 140 will begin to reach an equilibrium state with the ambient pressure applied to the outside of the assembly, i.e. the pressure of the first gas (P1) will be approximately the same as the ambient pressure (P2). At this time, the added pressure due to the surface tension (Pt) of the void 140 begins to play a more dominant role. As the void 140 gets smaller, the surface tension induced pressure acting on any first gas within the void 140 gets larger. At some point, during a second time period, the sum of the pressures within the void 140 (P1) will become greater than the ambient pressure (P2) acting on the outside of the assembly. At or near this point, the first gas within the void 140 will slowly diffuse into the encapsulant 130. Since the gas within the void 140 is under higher pressure, during the second time period, than the ambient gas acting on the outside of the assembly, the rate of diffusion of the first gas into the encapsulant 130 will be greater than the rate of diffusion of the ambient gas into the encapsulant 130 causing the void 140 to get smaller still. As the diameter of the void 140 gets smaller and smaller, the pressure due to the surface tension (Pt) of the void 140 will progressively grow greater and greater, up until the point where the gas within the void is completely diffused within the encapsulant, as shown in
If the area around the flip chip device has been evacuated prior to the sealing step, there will of course be virtually no first gas within the void 140. This being the case, the combination of the ambient pressure (P2) and the surface tension pressure (Pt) push the encapsulant in to the void 140 while aided by a “pulling effect” created by the vacuum within the void 140 pulling the encapsulation into the void 140. Thus, an evacuation step prior to the sealing step will cause any voids 140 to collapse more quickly.
Typically, the next step includes applying energy to cure the encapsulant 130. The object of applying the curing energy is to fully cure (cross-link) the encapsulant 130 so that new voids will not reoccur such as may happen when the ambient gas pressure (P2) is released quickly. The type of applied energy will depend on what encapsulant is used and how that particular encapsulant cures. Examples of possible sources of energy include heat, ultra-violet radiation, catalysis and combinations thereof. When an epoxy, such as Hysol®, is used as the encapsulant, heat is typically applied as the curing energy. An appropriate temperature range will again depend on the type of encapsulant 130 used and the length of time desired to fully cure the encapsulant 130. A fully cured, thermoset encapsulant 130 will maintain its structural integrity without allowing new voids to occur. It has also been found that the step of applying energy may occur after the ambient gas pressure (P2) is removed from the assembly without the reoccurrence of voids 140 if the ambient gas pressure (P2) is released slowly enough so as to allow any dissolved gases within the encapsulant 130 to come to equilibrium with the surrounding ambient gas.
In a variation of this process, a first gas within the void 140 and an ambient gas may be comprised of different gases to facilitate the diffusion of the first gas into and through the encapsulant 130 at a greater rate than the rate of diffusion of the ambient gas into the encapsulant. After the step of sealing the gap between the chip 100 and the substrate 120, the first gas surrounding the assembly may be evacuated and another ambient gas may take its place. In such an embodiment, the first gas contained within the void 140 may have smaller molecules than the ambient gas accelerating first gas' diffusion into the encapsulant 130. Choosing the correct sealed first gas will necessarily entail choosing the correct ambient gas and vice-versa. Examples of sealed first gases include helium, hydrogen, H2O vapor, etc. Examples of ambient gases when compared with the first gases listed above include argon, air, nitrogen, carbon dioxide and Krypton.
In a further variant of this process, hydrostatic pressure could be used instead of the isostatic pressure discussed above to compress the voids/bubbles. Typically in such a process, inert fluids would be used to compress the voids/bubbles.
II. Injection of an Encapsulant
As shown in
As described above, the adjacent compliant pads 250 provide the structure for the gap between the chip 200 and the first substrate 225 and provide and define channels therebetween for the encapsulant 230 to eventually flow; however other alternatives could be used instead, such as cellular foam, loosely woven non-conductive strands, etc. It is only important that a gap be provided between the chip 200 and the first substrate 225 while holding the two items in a substantially coplanar relationship. The compliant pad embodiment will be described in this example. As described in the '669 application, the compliant pads 250 are typically deposited, as by stenciling, and cured so that the chip 200 and the first substrate 225 are attached to each other in a substantially coplanar relationship. A curable liquid encapsulant 230 may then be deposited completely around the perimeter of the gap between the chip 200 and the first substrate 225 so as to seal the pads 250 and create a sealed void (void/gas bubble) 240 out of the network of the channels therewithin, very much like the sealed assembly described in the flip chip embodiment above. Typically, a curable, compliant thermoset resin is used as an encapsulant, such as silicone and flexiblized epoxy. Alternately, thermoplastic materials may be used if they are specially formulated to undergo a phase change such that they go liquid under certain conditions and not under others, such as at a temperature which would be typically higher than the normal operating temperature of the resulting device.
An isostatic pressure is then applied to the assembly causing the encapsulant to flow between the chip 200 and the first substrate 225 and into the channels within the void 240. Again, the ambient gas pressure applied will depend on the encapsulant material selected and the amount of time desired for the process of removing the void 240; and further on whether the pressure is applied in a virtual step or is applied gradually. The typical applied ambient gas pressure here will be approximately between 10 and 450 pounds per square inch (“psi”), and preferably between about 30 and 200 psi, for a time period of between about thirty minutes and several hours (the time period also depends on the volume to be encapsulated). A virtual step of ambient gas pressure is preferred in order to increase the rapidity of the void removal.
As described above, the step of applying pressure on the assembly after the void 240 has been sealed will cause a pressure differential between the compressive, ambient gas applied to the outside of the assembly and any first gas trapped within the void 240. The average diameter of the void 240 will thus be reduced allowing the encapsulant to begin encapsulating the outermost compliant pads 250 on all four sides of the chip 200.
The pressure from the ambient gas combined with the pressure from the surface tension of the void 240 itself will cause the void to grow smaller. If there is a first gas trapped within the void, as the first gas pressure becomes greater than the pressure due to the ambient gas pressure, the first gas will begin to diffuse into the encapsulant 230. Since any first gas within the void 240 is under higher pressure, during the second time period, than the ambient gas acting on the outside of the assembly, the rate of diffusion of the first gas into the encapsulant will be greater than the rate of diffusion of the ambient gas into the encapsulant. As the diameter of the void 240 gets smaller and smaller, the pressure due to the surface tension of the void 240 will progressively grow greater and greater, up until the point where the void 240 is completely removed from the encapsulant, as shown in
As described in the last section, energy is typically applied to cure the encapsulant 230. The type of energy applied depends on the encapsulant 230 selected and under what conditions the selected encapsulant 230 cures. If a silicone is used as the encapsulant, the energy applied is typically heat. The amount of heat and the length of time the heat is applied is again dependent upon the selected encapsulant material and the volume of material that needs to be cured. As described above, the application of energy will typically occur prior to the termination of the step of applying pressure so that no new voids are allowed to develop in the encapsulant by the reduction of the ambient pressure. A fully cured, thermoset encapsulant 130 will maintain its structural integrity so that gas bubbles and voids do not reenter the encapsulant. The above mentioned variations and embodiments listed in the Flip Chip Underfill Encapsulation section, above, would also facilitate this injection process.
Thus, in the configuration shown in
As described above and shown in
After the gap has been sealed, the frame assembly 222 is placed within a pressure chamber, such as the aforementioned autoclave chamber, and an isostatic pressure is applied to collapse the voids and/or gas bubbles 240 thereby causing the encapsulant to engulf the supports 250 and provide a substantially void free interposer layer, as described above. Preferably, a plurality of frames 280 are placed within a frame assembly carrier 285 so that the frames 280 may be more easily stacked together and placed within the pressure chamber. In the embodiment shown in
The fully encapsulated semiconductor chip packages within the frame assemblies 221 are next separated (or “diced”) from their respective frame/substrate into single packaged chips, such as that shown in
As shown in
Such a releasable package structure would encounter durability problems in use of the finished package due to the possibility of the pads 250′″/251′″ peeling away from either the substrate 225 or the chip 200 or both unless, at some point before the package is shipped to a customer, the peelable nature of the pad is neutralized.
In a variation to this process, a pressure sealed membrane 231 may be applied or deposited in a sheet form atop the assembly, as shown in
In a still further variant of this process, hydrostatic pressure could be used instead of the isostatic pressure discussed above to compress the voids/bubbles. Typically in such a process, inert fluids would be used to compress the voids/bubbles.
Treating an Interposer Layer
The pad 330 may be positioned and attached as a solid piece, as with adhesive on opposing sides thereof, or it may be stenciled or screened onto the face surface of the chip 300 or onto the opposing surface of the first substrate 325. Typically, it is stenciled onto the first substrate 325 prior to the leads 360 being detached from a sacrificial outer portion 327 of the first substrate and formed and bonded to respective chip contacts 370. The stenciled pad 330 is then at least partially cured. If a thicker compliant pad 330 is desired or if added adhesive properties are required a chip attach layer (not shown) may then be deposited on top of a typically fully cured pad 330, as by a stenciling step. The chip attach layer may then be left either uncured or may be partially cured (“B-staged”) prior to the attachment of the chip 300. Preferably, the chip is attached using a heated collet placement system so that the chip is relatively hot when it is pressed against the chip attach layer so as to minimize the number and size of any voids (or gas bubbles) 340/340′. Typically, these voids will occur at the boundary between the different materials in the assembly, e.g. first substrate/compliant pad, compliant pad/chip or even compliant pad/chip attach layer depending upon the materials chosen for those two materials. Even using a hot chip placement system, gas bubbles or voids 340/340′ are difficult to avoid in the uncured chip attach layer whether from the entrapment of gas when the chip is attached (
After the chip 300 has been attached and the voids 340/340′ have been sealed within the package assembly, the assembly is placed under isostatic pressure for a given amount of time to remove the voids 340/340′. As in the embodiments described above, the step of applying an isostatic ambient gas to the outside of the assembly is used to create a pressure gradient between the lower pressure first gas/vacuum within the voids 340/340′ and the ambient gas pressure be applied to the outside of the assembly. This has the effect of compressing any first gas in the voids 340/340′ thereby reducing the volume of the void and increasing the pressure therewith. If there is a sealed first gas within the voids 340/340′, the pressure within each void 340/340′ is the sum of the pressure from the compressed first gas and the pressure from the surface tension of the void. As the void volume decreases, the pressure from the surface tension of the void will increase dramatically. At some point during a second time period, the sum of the pressures within the void 340 will become greater than the ambient pressure acting on the outside of the assembly. Because of the greater pressure within the void in relation to the pressure outside the assembly during second time period, the first gas within the void will begin to diffuse into the compliant pad/chip attach layer 330 faster than the ambient gas diffuses into the compliant pad/chip attach layer 330. The greater rate of diffusion of the first gas combined with the increased pressure of the first gas will cause the first gas to completely diffuse into the compliant pad/chip attach layer 330 such that the bubble has been removed.
As described in the above sections, the pressure which is needed to remove the voids will depend on the materials used as the compliant pad and the hip attach layer and will also depend on the time allotted for their removal and the total volume of the voids to be removed. An example of a suitable pressure/time range where both the compliant pad and the chip attach layers are comprised of silicone resin includes between about 10 and 1000 psi for anywhere over approximately one hour. The assembly may be kept under pressure for more than the specified amount of time, without harm coming to it.
Any first gas sealed within the void 340 may be comprised of the same gas as the ambient gas; however, the first gas and the ambient gas may also be different in order to facilitate a greater rate of diffusion of the sealed first gas. After the step of sealing the first gas by attaching the chip to the compliant pad/chip attach layer 330, the first gas present on the outside of the assembly may be evacuated and replaced with a different pressurized ambient gas. Desirably, the second ambient gas should have an inherent rate of diffusivity with respect to the chip attach layer material that is less than the rate of diffusivity of the first gas into the same chip attach material. If the chip attach material is a curable thermoset resin material, suitable examples of possible first gases include: helium, hydrogen, H2O vapor, methane and fluorinated hydrocarbons. Examples of suitable second ambient gases in such a situation include: argon, air, nitrogen, and carbon dioxide.
Typically, after the voids 340/340′ have been removed from the compliant pad/chip attach layer 330, the assembly is heated in order to cure (or fully cross link) the chip attach layer to ensure that the voids 340/340′ do not return prior to the removal of the ambient gas pressure being applied to the assembly. As described above, other types of energy may be used to cause the chip attach layer to cure depending upon what the material is comprised.
As shown in
In a further variant of this process, hydrostatic pressure could be used instead of the isostatic pressure discussed above to compress the voids/bubbles. Typically in such a encapsulant between a face process, inert fluids would be used to compress the voids/bubbles.
The method of the present invention has thus far been described with respect to individual semiconductor chips. However, it is contemplated that the method of encapsulation may be employed with a plurality of chips simultaneously provided on a semiconductor wafer. As illustrated in
After the interposers 442 and chips 428 are encapsulated, the individual chips are separated from the wafer 430 and from one another, as by cutting the wafer using conventional wafer severing or “dicing” equipment commonly utilized to sever individual chips without interposers. This procedure yields a plurality of encapsulated chips and interposer subassemblies, each of which may be secured to an individual substrate.
As illustrated in
Having fully described several embodiments of the present invention, it will be apparent to those of ordinary skill in the art that numerous alternatives and equivalents exist which do not depart from the invention set forth above. It is therefore to be understood that the present invention is not to be limited by the foregoing description, but only by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3390308||Mar 31, 1966||Jun 25, 1968||Itt||Multiple chip integrated circuit assembly|
|US3413713||Jun 18, 1965||Dec 3, 1968||Motorola Inc||Plastic encapsulated transistor and method of making same|
|US3614832||Mar 9, 1966||Oct 26, 1971||Ibm||Decal connectors and methods of forming decal connections to solid state devices|
|US3811183||Jan 27, 1972||May 21, 1974||Philips Corp||Method of manufacturing a semiconductor device and semiconductor device manufactured by the method|
|US3868724||Nov 21, 1973||Feb 25, 1975||Fairchild Camera Instr Co||Multi-layer connecting structures for packaging semiconductor devices mounted on a flexible carrier|
|US3906144||Dec 28, 1973||Sep 16, 1975||Lucas Electrical Co Ltd||Film circuit assemblies|
|US4012766||Oct 8, 1975||Mar 15, 1977||Western Digital Corporation||Semiconductor package and method of manufacture thereof|
|US4017495||Oct 23, 1975||Apr 12, 1977||Bell Telephone Laboratories, Incorporated||Encapsulation of integrated circuits|
|US4143456||Jun 20, 1977||Mar 13, 1979||Citizen Watch Commpany Ltd.||Semiconductor device insulation method|
|US4163072||Jun 7, 1977||Jul 31, 1979||Bell Telephone Laboratories, Incorporated||Encapsulation of circuits|
|US4300153||Sep 25, 1980||Nov 10, 1981||Sharp Kabushiki Kaisha||Flat shaped semiconductor encapsulation|
|US4312116||Apr 14, 1980||Jan 26, 1982||International Business Machines Corporation||Method of sealing an electronic module in a cap|
|US4366187||Oct 31, 1980||Dec 28, 1982||Western Electric Company, Inc.||Immersion curing of encapsulating material|
|US4374080||Jan 13, 1981||Feb 15, 1983||Indy Electronics, Inc.||Method and apparatus for encapsulation casting|
|US4381602||Dec 29, 1980||May 3, 1983||Honeywell Information Systems Inc.||Method of mounting an I.C. chip on a substrate|
|US4536469||Nov 23, 1981||Aug 20, 1985||Raytheon Company||Semiconductor structures and manufacturing methods|
|US4566184||Nov 19, 1984||Jan 28, 1986||Rockwell International Corporation||Process for making a probe for high speed integrated circuits|
|US4604644||Jan 28, 1985||Aug 5, 1986||International Business Machines Corporation||Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making|
|US4605153||Jun 17, 1985||Aug 12, 1986||Northern Telecom Limited||Shaped solder pad for reflow soldering of surface mounting cylindrical devices on a circuit board|
|US4616412||Nov 4, 1983||Oct 14, 1986||Schroeder Jon M||Method for bonding electrical leads to electronic devices|
|US4658332||Sep 19, 1985||Apr 14, 1987||Raytheon Company||Compliant layer printed circuit board|
|US4697203||Jun 4, 1985||Sep 29, 1987||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device and manufacturing method therefor|
|US4701999||Dec 17, 1985||Oct 27, 1987||Pnc, Inc.||Method of making sealed housings containing delicate structures|
|US4707724||Jan 2, 1987||Nov 17, 1987||Hitachi, Ltd.||Semiconductor device and method of manufacturing thereof|
|US4710798||Sep 12, 1985||Dec 1, 1987||Northern Telecom Limited||Integrated circuit chip package|
|US4746392||Sep 22, 1986||May 24, 1988||Gao Gesellschaft Fur Automation Und Organisation Mbh||Method for producing an identification card with an integrated circuit|
|US4766670||Feb 2, 1987||Aug 30, 1988||International Business Machines Corporation||Full panel electronic packaging structure and method of making same|
|US4825284||Dec 10, 1986||Apr 25, 1989||Hitachi, Ltd.||Semiconductor resin package structure|
|US4829666||Jul 20, 1984||May 16, 1989||Gao Gesellschaft Fur Automation Und Organisation Mbh||Method for producing a carrier element for an IC-chip|
|US4847146||Mar 21, 1988||Jul 11, 1989||Hughes Aircraft Company||Process for fabricating compliant layer board with selectively isolated solder pads|
|US4857483||Apr 29, 1987||Aug 15, 1989||Sgs-Thomson Microelectronics S.A.||Method for the encapsulation of integrated circuits|
|US4860088||Sep 14, 1987||Aug 22, 1989||Microelectronics And Computer Technology Corporation||Electrical interconnect tape|
|US4900501||Oct 30, 1986||Feb 13, 1990||Hitachi, Ltd.||Method and apparatus for encapsulating semi-conductors|
|US4904610 *||Jan 27, 1988||Feb 27, 1990||General Instrument Corporation||Wafer level process for fabricating passivated semiconductor devices|
|US4913930||Mar 31, 1989||Apr 3, 1990||Wacker Silicones Corporation||Method for coating semiconductor components on a dielectric film|
|US4915607||Oct 6, 1988||Apr 10, 1990||Texas Instruments Incorporated||Lead frame assembly for an integrated circuit molding system|
|US4918811||Aug 8, 1989||Apr 24, 1990||General Electric Company||Multichip integrated circuit packaging method|
|US4920074||Feb 25, 1988||Apr 24, 1990||Hitachi, Ltd.||Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof|
|US4940181||Apr 6, 1989||Jul 10, 1990||Motorola, Inc.||Pad grid array for receiving a solder bumped chip carrier|
|US4942140||Jun 9, 1989||Jul 17, 1990||Mitsubishi Denki Kabushiki Kaisha||Method of packaging semiconductor device|
|US4953173||Aug 4, 1988||Aug 28, 1990||Kabushiki Kaisha Toshiba||Semiconductor device|
|US4955132||Nov 15, 1988||Sep 11, 1990||Sharp Kabushiki Kaisha||Method for mounting a semiconductor chip|
|US4975765||Jul 7, 1989||Dec 4, 1990||Contraves Ag||Highly integrated circuit and method for the production thereof|
|US4999319||Apr 6, 1989||Mar 12, 1991||Fujitsu Limited||Method of manufacturing semiconductor device having package structure|
|US4999699||Mar 14, 1990||Mar 12, 1991||International Business Machines Corporation||Solder interconnection structure and process for making|
|US5019673 *||Aug 22, 1990||May 28, 1991||Motorola, Inc.||Flip-chip package for integrated circuits|
|US5037779||May 16, 1990||Aug 6, 1991||Whalley Peter D||Method of encapsulating a sensor device using capillary action and the device so encapsulated|
|US5052907||Jul 3, 1990||Oct 1, 1991||Kabushiki Kaisha Toshiba||Resin sealing apparatus for use in manufacturing a resin-sealed semiconductor device|
|US5053357||Aug 14, 1990||Oct 1, 1991||Motorola, Inc.||Method of aligning and mounting an electronic device on a printed circuit board using a flexible substrate having fixed lead arrays thereon|
|US5055913||Oct 26, 1989||Oct 8, 1991||Gao Gesellschaft Fur Automation Und Organisation Mbh||Terminal arrangement for integrated circuit device|
|US5075760||May 31, 1990||Dec 24, 1991||Texas Instruments Incorporated||Semiconductor device package assembly employing flexible tape|
|US5089440||Dec 10, 1990||Feb 18, 1992||International Business Machines Corporation||Solder interconnection structure and process for making|
|US5120678||Nov 5, 1990||Jun 9, 1992||Motorola Inc.||Electrical component package comprising polymer-reinforced solder bump interconnection|
|US5121190||Mar 14, 1990||Jun 9, 1992||International Business Machines Corp.||Solder interconnection structure on organic substrates|
|US5130781||Oct 1, 1990||Jul 14, 1992||Ibm Corporation||Dam for lead encapsulation|
|US5144747||Mar 27, 1991||Sep 8, 1992||Integrated System Assemblies Corporation||Apparatus and method for positioning an integrated circuit chip within a multichip module|
|US5148265||Mar 21, 1991||Sep 15, 1992||Ist Associates, Inc.||Semiconductor chip assemblies with fan-in leads|
|US5148266||Sep 24, 1990||Sep 15, 1992||Ist Associates, Inc.||Semiconductor chip assemblies having interposer and flexible lead|
|US5173764||Apr 8, 1991||Dec 22, 1992||Motorola, Inc.||Semiconductor device having a particular lid means and encapsulant to reduce die stress|
|US5182632||Dec 2, 1991||Jan 26, 1993||Tactical Fabs, Inc.||High density multichip package with interconnect structure and heatsink|
|US5193732||Oct 4, 1991||Mar 16, 1993||International Business Machines Corporation||Apparatus and methods for making simultaneous electrical connections|
|US5194930||Sep 16, 1991||Mar 16, 1993||International Business Machines||Dielectric composition and solder interconnection structure for its use|
|US5203076 *||Dec 23, 1991||Apr 20, 1993||Motorola, Inc.||Vacuum infiltration of underfill material for flip-chip devices|
|US5203706||Jan 21, 1992||Apr 20, 1993||Amos Zamir||Educational device|
|US5218234||Dec 23, 1991||Jun 8, 1993||Motorola, Inc.||Semiconductor device with controlled spread polymeric underfill|
|US5249101||Jul 6, 1992||Sep 28, 1993||International Business Machines Corporation||Chip carrier with protective coating for circuitized surface|
|US5252784||May 27, 1992||Oct 12, 1993||Ibiden Co., Ltd.||Electronic-parts mounting board and electronic-parts mounting board frame|
|US5258330||Feb 17, 1993||Nov 2, 1993||Tessera, Inc.||Semiconductor chip assemblies with fan-in leads|
|US5288944||Jun 17, 1993||Feb 22, 1994||International Business Machines, Inc.||Pinned ceramic chip carrier|
|US5289346||Feb 16, 1993||Feb 22, 1994||Microelectronics And Computer Technology Corporation||Peripheral to area adapter with protective bumper for an integrated circuit chip|
|US5296738||Aug 10, 1992||Mar 22, 1994||Motorola, Inc.||Moisture relief for chip carrier|
|US5302101||Jan 21, 1993||Apr 12, 1994||Rohm Co., Ltd.||Mold for resin-packaging electronic components|
|US5304252||Aug 28, 1992||Apr 19, 1994||Oliver Sales Company||Method of removing a permanent photoimagable film from a printed circuit board|
|US5304512||Dec 22, 1992||Apr 19, 1994||Hitachi, Ltd.||Process for manufacturing semiconductor integrated circuit device, and molding apparatus and molding material for the process|
|US5311059||Jan 24, 1992||May 10, 1994||Motorola, Inc.||Backplane grounding for flip-chip integrated circuit|
|US5336931||Sep 3, 1993||Aug 9, 1994||Motorola, Inc.||Anchoring method for flow formed integrated circuit covers|
|US5355283||Apr 14, 1993||Oct 11, 1994||Amkor Electronics, Inc.||Ball grid array with via interconnection|
|US5371044||Apr 30, 1992||Dec 6, 1994||Hitachi, Ltd.||Method of uniformly encapsulating a semiconductor device in resin|
|US5385869||Jul 22, 1993||Jan 31, 1995||Motorola, Inc.||Semiconductor chip bonded to a substrate and method of making|
|US5394009||Jul 30, 1993||Feb 28, 1995||Sun Microsystems, Inc.||Tab semiconductor package with cushioned land grid array outer lead bumps|
|US5409362||Jul 6, 1994||Apr 25, 1995||Neu Dynamics Corp.||Encapsulation molding equipment|
|US5409865||Feb 25, 1994||Apr 25, 1995||Advanced Semiconductor Assembly Technology||Process for assembling a TAB grid array package for an integrated circuit|
|US5409866||Dec 24, 1992||Apr 25, 1995||Fujitsu Ltd.||Process for manufacturing a semiconductor device affixed to an upper and a lower leadframe|
|US5473512||Jun 16, 1994||Dec 5, 1995||At&T Corp.||Electronic device package having electronic device boonded, at a localized region thereof, to circuit board|
|US5473814||Jan 7, 1994||Dec 12, 1995||International Business Machines Corporation||Process for surface mounting flip chip carrier modules|
|US5477611||Sep 20, 1993||Dec 26, 1995||Tessera, Inc.||Method of forming interface between die and chip carrier|
|US5483106||Jul 29, 1994||Jan 9, 1996||Nippondenso Co., Ltd.||Semiconductor device for sensing strain on a substrate|
|US5488200 *||Jun 8, 1994||Jan 30, 1996||International Business Machines Corporation||Interconnect structure with replaced semiconductor chips|
|US5563445||Apr 4, 1994||Oct 8, 1996||Seiko Epson Corporation||Semiconductor device|
|US5594626||May 2, 1995||Jan 14, 1997||Lsi Logic Corporation||Partially-molded, PCB chip carrier package for certain non-square die shapes|
|US5629566 *||Aug 7, 1995||May 13, 1997||Kabushiki Kaisha Toshiba||Flip-chip semiconductor devices having two encapsulants|
|US5710071||Dec 4, 1995||Jan 20, 1998||Motorola, Inc.||Process for underfilling a flip-chip semiconductor device|
|US5720100||Dec 29, 1995||Feb 24, 1998||Motorola, Inc.||Assembly having a frame embedded in a polymeric encapsulant and method for forming same|
|US5817545||Jan 24, 1996||Oct 6, 1998||Cornell Research Foundation, Inc.||Pressurized underfill encapsulation of integrated circuits|
|US5834339||Mar 7, 1996||Nov 10, 1998||Tessera, Inc.||Methods for providing void-free layers for semiconductor assemblies|
|US5834340||Nov 24, 1997||Nov 10, 1998||Mitsubishi Denki Kabushiki Kaisha||Plastic molded semiconductor package and method of manufacturing the same|
|US6048656||May 11, 1999||Apr 11, 2000||Micron Technology, Inc.||Void-free underfill of surface mounted chips|
|US6207478||Jun 15, 1999||Mar 27, 2001||Samsung Electronics Co., Ltd.||Method for manufacturing semiconductor package of center pad type device|
|US6221697||Dec 30, 1999||Apr 24, 2001||Advanced Semiconductor Engineering, Inc.||Chip scale package and manufacturing method thereof|
|JPS5511361A||Title not available|
|JPS6077446A||Title not available|
|JPS53139468A||Title not available|
|JPS55117254A||Title not available|
|JPS59143333A||Title not available|
|JPS63241955A *||Title not available|
|1||Action Closing Prosecution, dated Sep. 21, 2009, Control No. 95/001,035.|
|2||Adamson, S., "Underfill Design and Process Considerations", Proc. SMTA Int'l., Chicago, IL, Aug. 2000, p. 69.|
|3||Babiarz, A.J., et al.; "Process Notes for Successful Encapsulation and Underfilling in MCM Assembly;" Electronic Packaging & Production; pp. 20-22 (Nov. 1994).|
|4||Bascom et al., "Air Entrapment in the Use of Structural Adhesive Films," J. Adhesion, 1972, vol. 4, pp. 193-209, Copyrgt. 1972 Gordon and Breach Science Publishers Ltd.|
|5||Bouras, C.E., "Adhesive Dispensing for Flip Chip-on-Board;" Electronic Packaging & Production; pp. S9-S11 (Oct. 1995).|
|6||Clementi et al., "Flip-Chip Encapsulation on Ceramic Substrates", 1993 Proceedings, 43rd Electronic Components and Technology Conference, IEEE, New York, NY, pp. 175-181 Jun. 1, 1993.|
|7||Excerpts from Response of Acer Inc. And Acer America Corp. To Complaint And Notice Of Investigation Under Section 337 Of the Tariff Act Of 1930, As Amended, dated Feb. 15, 2008, In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products Containing Same (III), ITC Investigation No. 337-TA-630.|
|8||Excerpts from Response of Nanya Technology Corp. And Nanya Technology Corp. U.S.A. To Complaint and Notice Of Investigation Under Section 337 Of The Tariff Act of 1930, As Amended, dated Feb. 15, 2008, In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products Containing Same (III), ITC Investigation No. 337-TA-630.|
|9||Excerpts from Response of Powerchip Semiconductor Corp. To Complaint And Notice Of Investigation Under Section 337 Of The Tariff Act of 1930, As Amended, with 22 attachments dated Feb. 15, 2008, In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products Containing Same (III), ITC Investigation No. 337-TA-630.|
|10||Excerpts from Response of Respondents Elpida Memory, Inc. and Elpida Memory (USA) Inc. To The Complaint And Notice Of Investigation, dated Feb. 15, 2008, In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products Containing Same (III), ITC Investigation No. 337-TA-630.|
|11||IBM Tech Disclosure Bull., vol. 23, No. 5, Oct. 1980, pp. 1877-1878.|
|12||IBM Tech Disclosure Bull., vol. 29, No. 11, Apr. 1987, pp. 4718-4719.|
|13||IBM Tech Disclosure Bull., vol. 32, No. 10B, Mar. 1990, p. 480.|
|14||Inter Partes Reexamination Certificate, dated Oct. 26, 2010, Control No. 95/001,035.|
|15||Nakano, F. et al., "Resin-Insertion Effect on Thermal Cycle Resistivity of Flip-Chip Mounted LSI Devices", ISHM '87 Proceedings, pp. 536-541, 1987.|
|16||Office Action in Inter Partes Reexamination, dated Jun. 6, 2008, Control No. 95/001,035.|
|17||Order Granting/Denying Request for Inter Partes Reexamination, dated Jun. 6, 2008, Control No. 95/001,035.|
|18||Park et al., "Evaluation of Epoxy Underfill Materials for Use in Chip-on-Board Method of Packaging Silicon Integrated Circuits", Annual Tech. Conf. Proceedings, pp. 2871-2876 1995.|
|19||Request for Inter Partes Reexamination and Exhibits of U.S. Patent 6,458,681, dated Apr. 2, 2008, Control No. 95/001,035.|
|20||Response to Action Closing Prosecution, dated Oct. 21, 2009, Control No. 95/001,035.|
|21||Response to Official Action, dated Aug. 6, 2008, Control No. 95/001,035.|
|22||Salmon, Edward R., Encapsulation of Electronic Devices and Components (Marcel Dekker, Inc. 1987).|
|23||Suryanarayana et al., "Encapsulants Used in Flip-Chip Packages", 1993 Proceedings, 43rd Electronic Components and Technology Conference, IEEE, New York, NY , pp. 193-198 Jun. 1, 1993.|
|24||Suryanarayana, D. et al., "Enhancement of Flip-Chip Fatigue Life by Encapsulation", IEEE Transactions on Components and Hybrids, and Manufacturing Technology, vol. 14, No. 1, Mar. 1991, pp. 218-223.|
|25||Third Party Requestor's Comments to Patent Owner's Response to Action Closing Prosecution, dated Nov. 20, 2009, Control No. 95/001,035.|
|26||Third Party's Requestor's Comments to Patent Owner's Response to Official Action, dated Oct. 10, 2008, Control No. 95/001,035.|
|27||Tummala et al., Microelectronics Packaging Handbook, 1989, pp. 420-423, 1132.|
|28||Wang, D. And K. Papathomas, "Encapsulant For Fatigue Life Enhancement of Controlled Collapse Chip Connection (C4)", Proc. Of 43rd Electronic Components & Technology Conference, Orlando, FL, Jun. 1993, p. 780.|
|U.S. Classification||438/612, 438/106, 438/118|
|International Classification||H01L21/44, H01L23/495, H01L21/68, H01L21/56, H01L23/31|
|Cooperative Classification||H01L2224/32225, H01L2924/0105, H01L2924/01075, H01L2924/014, H01L23/3107, H01L2224/97, H01L24/97, H01L24/32, H01L2924/01082, H01L21/568, H01L2924/01005, H01L2924/01078, H01L2224/16225, H01L21/6835, H01L2924/15311, H01L2224/73204, H01L2924/01033, H01L2924/01006, H01L23/49572, H01L23/3114, H01L21/561, H01L2924/01002, H01L2924/01018, H01L21/565|
|European Classification||H01L24/97, H01L21/56M, H01L23/495J, H01L21/56T, H01L23/31H1, H01L24/32, H01L21/683T, H01L21/56B, H01L23/31H|
|Mar 22, 2012||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DISTEFANO, THOMAS H.;FJELSTAD, JOSEPH;REEL/FRAME:027925/0673
Owner name: TESSERA, INC., CALIFORNIA
Effective date: 19960821
|Mar 28, 2014||FPAY||Fee payment|
Year of fee payment: 12