|Publication number||USRE43443 E1|
|Application number||US 09/987,978|
|Publication date||Jun 5, 2012|
|Priority date||Mar 27, 1992|
|Also published as||US5378656, US5637913|
|Publication number||09987978, 987978, US RE43443 E1, US RE43443E1, US-E1-RE43443, USRE43443 E1, USRE43443E1|
|Inventors||Yujiro Kajihara, Kazunari Suzuki, Kunihiro Tsubosaki, Hiromichi Suzuki, Yoshinori Miyaki, Takahiro Naito, Sueo Kawai|
|Original Assignee||Renesas Electronics Corporation, Hitachi Ulsi Systems Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (39), Non-Patent Citations (4), Referenced by (4), Classifications (72), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a 37 CFR §1.60 divisional of prior application Ser. No. 08/038,684, filed Mar. 29, 1993 (allowed). Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,637,913 now abandoned. The reissue cases are application Ser. No. 09/328,910 filed 9 Jun. 1999, pending, and its divisions, application Ser. No. 09/987,978 filed 16 Nov. 2001 (the present case), pending, and application Ser. No. 09/989,242 filed 21 Nov. 2001, pending. U.S. application Ser. No. 08/311,021 filed on Sep. 22, 1994, now U.S. Pat. No. 5,637,913, issued on Jun. 10, 1997 is a 35 USC §120 Divisional of prior application Ser. No. 08/038,684, filed Mar. 29, 1993, now U.S. Pat. No. 5,378,656, issued on Jan. 3, 1995. This application Ser. No. 09/987,978, filed Nov. 16, 2001, is a divisional application of Ser. No. 09/328,910, filed Jun. 9, 1999.
The present invention relates to a leadframe for mounting a semiconductor chip, a semiconductor integrated circuit device using the same, and a method of and process for fabricating the two. More particularly, the present invention relates to a technology which is effective when applied for standardizing the leadframe and for improving the reflow cracking resistance of an LSI package.
The resin body, i.e., LSI package of a surface mounting type resin molded device (or surface mount device) such as a QFP (i.e., Quad Flat Package) has an important target of suppressing the package cracking (i.e., resin body cracking) in a reflow soldering step.
In case the resin body (i.e., plastic body) of the LSI package absorbs moisture, the interface between the resin and a die pad will peel due to the internal stress which is caused by the high temperature at the reflow soldering step for heating the LSI package in its entirety. This package cracking is a phenomenon the peeling is enlarged by the expansion of the moisture condensed at the die pad interface, i.e., the water vapor pressure to crack the resin body. This phenomenon causes the deterioration of moisture resistance and an insufficient soldering due to the bulging of the package body. If this package cracking takes place on the face of the semiconductor chip, it will cause a serious defect such as the breakage of wires.
As the existing counter-measures for preventing the peel of the interface between the resin and the die pad, there is known either a method (as disclosed in Japanese Patent laid-Open No. 83961/1990), in which the die pad is partially formed with through holes so that the back of the semiconductor chip and the resin may be held in close contact through those through holes, or a method in which the adhesion between the resin and the die pad is improved by dimpling the back face of the die pad.
On the other hand, even the chips having an equal pin number but different sizes, e.g., an ASIC (i.e., Application Specific Integrated Circuit) having a small production number for one kind are required to be capable of packaging density and it is a tendency that the chip is mounted on the surface mounted LSI package such as the aforementioned QFP. In the prior art, therefore, the products have been manufactured by fabricating a leadframe according to the chip size so that their production cost are raised.
As the leadframe capable of corresponding to the ASIC of various chip sizes but a small production number, therefore, there is disclosed on pp. 76 to 78 of “Nikkei MICRODEVICES, December, 1987” a leadframe, in which a semiconductor chip is mounted on a tape of a polyimide resin attached as the die pad to the inner leads.
In the LSI packages of recent years, however, the ratio of the area of the package body occupied by the semiconductor chip increases more and more. Since the resin is made far thinner than that of the prior LSI package, the aforementioned counter-measures, i.e., the method of forming the through holes in the die pad or dimpling the die pad has found it difficult to prevent the package body cracking effectively.
Moreover, investigations have been made not by forming a leadframe according to the chip size but by using the leadframe of the prior art, i.e., the leadframe in which the external size (i.e., the area of the chip mounting face) of the die pad is made larger than that (i.e., the area of the principal or back face) of the semiconductor chip. However, these investigations have revealed that a considerable restriction is exerted upon the size of the chip to be mounted on the die pad. Specifically, if there is mounted a semiconductor chip having an external size smaller by 1 to 2 mm or more than that of the die pad, the wires will hang as far as to contact with the die pad ends thereby to cause a wire bonding defect. This makes it impossible to use a relatively small chip. On the other hand, the positions of the leading ends of the inner leads are restricted by the die pad, and the length of the wires are also restricted (or determined to a suitable value of 1.0 mm to 5.0 mm by the performance of the wire bonder or by the electric characteristics) so that the relatively small chip cannot be used. On the other hand, the size of the chip to be mounted is limited to the external size of the die pad to raise an upper limit to the chip size.
The aforementioned die pad, which is prepared by adhering the tape of polyimide resin to the inner leads, has no restriction on the size of the chip. Since, however, the tape has a coefficient of thermal expansion different from those of the leadframe and the semiconductor chip, a peel may take place at their interface due to the difference in the coefficients of thermal expansion at the soldering fellow step thereby to cause the package body cracking. This makes it necessary to provide a package which can prevent the interface peel and the package body cracking and mounting a variety of chip sizes.
It is, therefore, an object of the present invention to provide a technology capable of improving the package body cracking resistance of the LSI package at the reflow soldering
Another object of the present invention is to provide a leadframe which can correspond to the flexible manufacturing system of the LSI.
Still another object of the present invention is to provide a semiconductor integrated circuit device using the aforementioned leadframe and a technology for fabricating the same.
Representatives of the invention to be disclosed herein will be summarized in the following.
(1) According to the present invention, there is provided a leadframe in which the external size of a die pad for mounting a semiconductor chip is made smaller than that of the semiconductor chip and in which the leading ends of leads can be cut to a predetermined length in accordance with the external size of the semiconductor chip.
Specifically, there is provided a leadframe capable of mounting a plurality of kinds of semiconductor chips having different sizes thereon, comprising:
(2) According to the present invention, there is also provided a method of fabricating a leadframe capable of mounting a plurality of kinds of semiconductor chips having different sizes thereon, comprising the steps of:
(3) According to the present invention, there is further provided a process for fabricating a semiconductor integrated circuit device by using a leadframe capable of mounting a plurality of kinds of semiconductor chips having different sizes thereon, comprising the steps of:
According to the means described above, the external size of the die pad is made smaller than that of the semiconductor chip to be mounted thereon, and the leading ends of the leads are cut to a predetermined length in accordance with the external size of the semiconductor chip to be mounted on the die pad. As a result, a variety of semiconductor chips having external sizes made different over a considerable wide range can be commonly used to provide a leadframe which matches the flexible manufacturing system of the LSI package.
More specifically, in case the leadframe of the prior art, i.e., the leadframe in which the external size of the die pad is larger than the chip size is used, the size of the chips to be commonly used is limited to a considerable small range (i.e., 1 to 2 mm from the contour of the tab to the chip end) so that the leading ends of the inner leads need not be cut. On the other hand, the leadframe of the present invention has a smaller die pad than the chip size so that it can commonly use chips o a wider size range (e.g., 5×5 mm to 15×15 mm). Thus, the leadframe of the present invention can sufficiently match the case in which the positions of the leading ends of the inner leads have to be changed according to the limits to the wire length.
Moreover, it is possible to provide a leadframe which can match the flexible manufacturing system of the LSI package. At the same time, the external size of the die pad is made smaller than that of the semiconductor chip so that the periphery of the semiconductor chip mounted on the die pad is adhered to the resin. Since this adhesion of the interface between the semiconductor chip (of silicon) and the resin is stronger than that of the interface between the die pad (of metal) and the resin, the moisture can be prevented from invading into the interface between the die pad and the resin. Thus, it is possible to suppress the package body cracking which might otherwise be caused when the LSI package is to be mounted on the substrate by the solder fellow.
A leadframe 1 is formed at its central portion with a circular die pad for mounting a semiconductor chip 2 which is formed with a semiconductor circuit and bonding pads on its principal face. The die pad 3 is supported by four suspension leads 4. The die pad 3 has its chip mounting face characterized to have a smaller area than that of the principal face of the semiconductor chip 2 mounted thereon.
The die pad 3 is arranged therearound with a plurality of leads 5. To the wider portions of the suspension leads 4 and the middle portions of the leads 5, there is adhered a quadrangular frame-shaped tape 6 which is made of an insulating, thin synthetic resin film. Outside of the tape 6, there is formed a dam bar 7 for supporting the leads 5 and preventing the resin from overflowing at a molding time. The dam bar 7 is formed into a frame shape to connect the individual leads 5.
The outermost periphery of the leadframe 1 is constructed of an outer frame 8 formed to connect a plurality of unit frames and an inner frame 9 formed to isolate the individual leadframes. The outer frame 8 is partially formed with guide holes for acting as guides when the leadframe 1 is to be positioned in the mold.
The aforementioned components of the leadframe 1, i.e., the die pad 3, the suspension leads 4, the leads 5, the dam bar 7, the outer frame 8 and the inner frame 9 are made of an electrically conductive material such as 42-alloy or copper. The portions of the leads 5, i.e., the inner lead portions 5a to be sealed with a resin have their leading ends plated with Ag. Although not shown, the leadframe 1 is constructed by juxtaposing a plurality of unit frames having those portions, in one direction.
Next, one embodiment of a method of fabricating the aforementioned leadframe 1 will be described with reference to
First of all, as shown in
In case the aforementioned individual portions are formed by the pressing, burrs 11 are left on the back of the cut portions. Since the leadframe 1 of the present embodiment is made such that the die pad 3 has a smaller area than that of the semiconductor chip 2 to be mounted thereon, the burrs 11, if any, on the face of the die pad 3 for mounting the semiconductor chip 2 will be unable to mount the chip 2. When the die pad 3 is to be pressed, therefore, it is pressed with its chip mounting Face face being directed upward so that the burrs 11 may be left on the back opposed to the chip mounting face.
On the other hand, the inner lead portions 5a are reluctant, if the burrs 11 are left at the lower side at a wire bonding step, to have wires bonded thereto so that the bonding is defective. When the inner lead portions 5a are to be pressed, the pressing is carried out downward with the bonding face being directed downward, to leave the burrs 11 on the wire bonding face.
Next, as shown in
Next, the leadframe 1 is subjected to a down-setting step. This down-setting step is a treatment to lower the height of the die pad 3 than that of the leads 5, as viewed horizontally, by bending the midway portions (as indicated at S in
Thanks to the aforementioned down-setting treatment, the resin thickness is substantially equalized at the upper face side of the semiconductor chip 2 and at the lower face side of the die pad 3 when a package is to be molded by fitting up a mold with the leadframe 1 having the semiconductor chip 2.
Next, the tape 6 is adhered to both the midway portions (i.e., wider portions) of the suspension leads 4 for supporting the die pad 3 and the inner lead portions 5a.
The adhesion of the tape 6 is carried out, as shown in
For example, the tape 6 is constructed such that an adhesive 6b of an acrylic resin is applied to a thickness of about 0.02 mm onto one side of a film 6a of a polyimide resin having an external size of about 18.5 mm×18.5 mm, a width of about 1.5 mm and a thickness of about 0.05 mm.
When the leadframe 1 having the semiconductor chip 2 is attached to the mold to form the package body, the die pad 3 can be prevented, by adhering the tape 6, i.e., the insulating film to the midway portions of the suspension leads 4 to fix the die pad 3, from being fluctuated by the flow of the molten resin. As a result, the flow velocities of the molten resin can be equalized at the upper face side of the semiconductor chip 2 and the lower face side of the die pad 3 to prevent the molding defect such as through voids.
Since the leadframe 1 of the present embodiment thus achieved is constructed such that the area of the chip mounting face of the die pad 3 is smaller than that of either the principal face of the semiconductor chip 2 to be mounted thereon or the back face opposed to the aforementioned principal face, it can mount semiconductor chips having different external sizes thereon. By cutting the leading ends of the leads 5 to shorten them, moreover, it is possible to mount a semiconductor chip 2a or 2b having a larger area.
Thus, in case the die pad 3 has a diameter of about 3 mm, for example, it is possible to mount a variety of semiconductor chips having external sizes ranging from about 5 mm×5 mm to about 15 mm×15 mm. The cutting step of the leads 5 is carried out by means of a press but with the wire bonding region being directed downward, so as to prevent the plated Ag layer from peeling from the wire bonding regions 32. As shown in
Next, one embodiment of a process for fabricating a QFP by using the aforementioned leadframe 1 will be described with reference to
First of all, as shown in
The application of the adhesive 15 is carried out, as shown in
Since the die pad 3 of the aforementioned leadframe 1 has a small area, the adhesive 15 may be applied to one point of the principal face of the die pad 3. This application results in such an advantage over the existing leadframe having a larger die pad that the structure of the nozzle 18 used may be simpler and that the application time of the adhesive 15 may be shorter.
As shown in
Since a sufficient adhesion strength is thus achieved, it is possible to prevent a disadvantage that the semiconductor chip 2 rotationally goes out of position over the die pad 3. Thanks to the formation of the small pads (i.e., adhesion-applied portions) 20, moreover, the rigidity of the suspension leads 4 can be substantially enhanced to prevent the die pad 3 from being fluctuated by the flow of the molten resin when the package is to be prepared by fitting up the mold with the leadframe 1 having the semiconductor chip 2 mounted thereon.
The aforementioned small pads 20 may be formed midway of the individual suspension leads 4, namely, between the die pads 3 and the midway portions S, as shown in
Next, as shown in
When the semiconductor chip 2 is to be positioned over the die pad 3, the locations of the V-shaped grooves 22 are detected from above the leadframe 1 by means of a (not-shown) camera, as shown in
As shown in
Next, as shown in
Next, as shown in
As shown in
Since the heat stage 27 is formed in its principal face with the aforementioned relief grooves 28, either the leadframe 1 (as shown in
Next, the aforementioned leadframe 1 is fitted in the mold, and the semiconductor chip 2, the die pads 3, the inner lead portions 5a and the wires 26 are molded of an epoxy resin, as shown in
Since the QFP 30 thus fabricated by using the leadframe 1 of the present embodiment has its die pad made smaller than the semiconductor chip 2 mounted thereon, the peripheral portion of the semiconductor chip 2 has its back contacting closely to the sealing resin.
Since the adhesion of the interface between the sealing resin and the die pad 3 is sufficient, the interface can be suppressed from peeling even if it should be expanded by the moisture having invaded and been heated at the fellow soldering step. Thus, it is possible to provide the QFP 30 having an improved reflow cracking resistance.
Moreover, since the leadframe 1 of the present embodiment can mount a variety of semiconductor chips 2 of different external sizes, the troubles of preparing a leadframe for each of the semiconductor chips having different external sizes are eliminated. As a result, the leadframe 1 can be standardized to reduce its production cost thereby to provide the QFP 30 at a reasonable cost.
Still moreover, since the leadframe 1 of the present embodiment reduces the external size of the die pad 3, the amount of the adhesive 15 to be used for mounting the semiconductor chip 2 on the die pad 3 can also be reduced to provide the QFP 30 at a more reasonable cost.
Although our invention has been specifically described in connection with the embodiments thereof, it should not be limited to the foregoing embodiments but can naturally be modified in various manners without departing from the gist thereof.
The shape of the die pad should not be limited to the circle but may be another such as a rectangle, if the adhering strength of the chip to the die pad and the minimum application region of the adhesive are retained. As shown in
As shown in
In the foregoing embodiments, the present invention has been described in case it is applied to the leadframe for fabricating the QFP, but can also be applied generally to the leadframes to be used for assembling the surface-mounting LSI package. The present invention can also be applied to a leadframe to be used for fabricating a pin-inserted LSI package such as DIP (i.e., Dual In-line Package).
The effects to be achieved by the representatives of the invention disclosed herein will be briefly summarized in the following:
(1) According to the present invention, it is possible to provide an LSI package having an improved reflow cracking resistance; and
(2) According to the present invention, a leadframe matching the flexible manufacturing system of the LSI package can be provided to reduce the production cost of the LSI package.
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|U.S. Classification||257/666, 257/672, 257/676, 257/670, 257/E23.031, 257/E23.052, 257/783, 257/674, 257/E23.037|
|International Classification||H01L21/48, H01L23/495, H01L21/60, H01L23/50, H01L21/52|
|Cooperative Classification||H01L24/73, H01L2924/00014, H01L2924/181, H01L2224/859, Y10T29/49121, H01L24/49, H01L24/48, H01L24/32, H01L2224/85181, H01L2224/45144, H01L2224/92, H01L2224/73265, H01L2224/48465, H01L2224/48247, H01L2224/83192, H01L24/27, H01L2224/48091, H01L24/45, H01L2224/82181, H01L24/29, H01L2924/01079, H01L2224/92247, H01L2924/01014, H01L24/743, H01L2224/49171, H01L2924/01082, H01L2924/01047, H01L2224/743, H01L2224/02166, H01L2224/32245, H01L2924/01005, H01L2224/32014, H01L2224/2919, H01L21/4842, H01L2924/01004, H01L2224/83194, H01L2924/01029, H01L2924/14, H01L23/49503, H01L24/83, H01L2224/838, H01L2924/0665, H01L2224/29007, H01L2924/014, H01L2924/01023, H01L2924/01078, H01L2924/01006, H01L2924/1433, H01L23/49513, H01L2924/01033, H01L23/49541|
|European Classification||H01L23/495A, H01L24/31, H01L21/48C3M, H01L24/83, H01L23/495G, H01L24/27, H01L23/495A6|
|Sep 26, 2003||AS||Assignment|
Owner name: RENESAS TECHNOLOGY CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:014570/0380
Effective date: 20030912
|Jul 23, 2010||AS||Assignment|
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN
Free format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:024736/0381
Effective date: 20100401