|Publication number||USRE43514 E1|
|Application number||US 12/349,989|
|Publication date||Jul 17, 2012|
|Filing date||Jan 7, 2009|
|Priority date||Mar 18, 2004|
|Also published as||US7161385, US20050206408|
|Publication number||12349989, 349989, US RE43514 E1, US RE43514E1, US-E1-RE43514, USRE43514 E1, USRE43514E1|
|Original Assignee||Intellectual Ventures I Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Classifications (9), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a Reissue application of U.S. Ser. No. 10/803,094, filed Mar. 18, 2004, now U.S. Pat. No. 7,161,385, granted Jan. 9, 2007.
The invention relates to parallel computational networks and circuit elements for such networks. The invention can be used in several applications in which variable values are connected by logical rules, including but not limited to applications in which the object is to perform reverse calculations, ie, calculations in which a result is known but the object is to find a set of starting values that gives the known result. There are several mathematical or logical operations which are grossly asymmetrical, which means that it is a straightforward task to carry out the operation in one direction but no fast algorithms are known or even supposed to exist for the reverse calculation.
An object of the present invention is to provide a circuit element and a parallel computational network that facilitate performing such operations. The object of the invention is achieved by the methods and equipment which are characterized by what is stated in the independent claims. Preferred embodiments of the invention are disclosed in the dependent claims.
In order to provide a concrete but non-limiting example, the invention is first described in the context of reverse computation. In forward computation, a given set of input variables produces a definite set of output variables. But with reverse computation a set of given output variables is not always sufficient to determine a corresponding set of input variables. A simple example is the exclusive or operation, or XOR: C=A XOR B. As is well known, C is true if and only if precisely one of the input variables A and B is true. For any set of input variables A and B, the output variable C can be determined, but the reverse is not true: a given value of C is not sufficient in itself to determine the values of A and B. For instance, if C is true then either A is true and B false or B is true and A is false. In this way both A and B may have the values of true and false and are thus in an indefinite state. However, these states are logically entangled; as soon as the value of A or B is fixed the value of the other is fixed, too. If the value of A is set to be true then B must be false and vice versa, and no degrees of freedom remain. Thus the A and B variables of a reverse-XOR element are logically entangled.
Thus an aspect of the invention is a circuit element capable of sustaining and processing a set of logically entangled variables with indefinite states. Another aspect of the invention is a parallel computational network that employs these inventive circuit elements. Yet another aspect is computer software whose execution in a computer creates the inventive circuit elements and parallel computational networks by computer simulation.
A key concept underlying the present invention is the logical entanglement. The entanglement, as used herein, means that the allowed logical value of a variable in a set of two or more variables depends on the logical values of the other variables in the set. For example: Let there be a number of logical variables Ai that may have two different values: 1 (logical true) and 0 (logical false). Let the value of each Ai be related to other Aj:s by a given logical rule fi:
Ai=fi(A1, A2, . . . , Aj)
The rule fi defines the logical entanglement between the variables Ai. The simplest rule is the exclusion between two variables A1 and A2:
EITHER A1 OR A2=1; A1≠A2
The exclusion rule means that if A1 is given the value 1 then A2 must be 0 and vice versa, because they both cannot have the value 1 or 0 at the same time. The true value of one variable excludes the true value of the other one and the false value of one variable excludes the false value of the other one, this is forced by the logical entanglement.
Instead of one fixed rule, a more complicated deduction may require several sets of rules between the logical variables. Let there be a number of rules fi that can be chosen by a number of other logical variables Bi:
fi=g(B1, B2, . . . , Bi)
Here g is the rule that gives the rule fi when the variables Bi are given.
An aspect of the invention is a circuit element that implements these principles. The circuit realizes the abovementioned rules f and g. The element's A variable inputs A1 to An are bi-directional and may function as inputs as well as outputs. The circuit's B inputs B1 to Bn that select the f rule via the g rule are unidirectional and operate as inputs only. There may be two or more A inputs and zero or more B inputs. If the number of B inputs is zero, no B inputs exist and there will be only one f rule available in the circuit.
In practical applications several of the above circuits are assembled in a network in which a number of the A variable inputs are tied to other A inputs and B inputs. This presents a problem; the A inputs also operate as outputs and according to normal circuit practice, the outputs of logical circuits should not be tied together as the competition of high and low levels may occur, which may result in the destruction of the connected circuits. Therefore the actual circuitry must be designed in a special way that solves this problem. Likewise, when we consider the previous example of the exclusion between two variables A1 and A2 (either A1 or A2=1; A1≠A2), we will notice that as soon as A1 or A2 is defined, the other one will be defined too, but if neither is defined then neither may take the value of 1 or 0. This means that at that moment both A1 and A2 must remain at an indefinite state that is not 1 or 0. Such a state can be considered as a superimposition of the states 1 and 0. This state will not output 1 or 0 value, but will accept either one of those values as input and consequently set itself to this input value and will thereafter resolve the remaining entangled variables according to the given rule.
Thus a first aspect of the invention is a logic element or component that permits logical deduction as described above. The circuit element comprises:
A second aspect of the invention is a parallel computing network that comprises:
two or more circuit elements, each of which comprises:
two or more logically entangled bi-directional terminals, wherein each bi-directional terminal can assume any one of three logical states, which are:
(a) a logical true state;
(b) a logical false state; and
(c) an indefinite state, in which state the bi-directional terminal accepts one of the logical true and logical false states as an external input from an external source; and
an entanglement logic for resolving the logical state of each of the bi-directional terminals according to a predetermined set of logical entanglement rules between the bi-directional terminals;
wherein the network further comprises a set of additional terminals, each additional terminal accepting a logical true state or logical false state as an input, wherein the inputs to the set of additional terminals collectively determine which of several sets of logical entanglement rules are to be used for said resolving.
A third aspect of the invention is a computer program product that comprises computer program code for implementing the first and/or second aspects of the invention via computer simulation.
In the following the invention will be described in greater detail by means of preferred embodiments with reference to the attached drawings, in which:
Here this example is described in more detail. There is a bi-directional entanglement rule between the A1 and A2 terminals:
The comparators Comp1, Comp2 and the OR-gate OR1 form a window detector 31. The output of the window detector 31 (the output of OR-gate OR1) is at logical zero (0 V) whenever the input A1 is at indefinite state and at logical one (5 V) whenever the input A1 is at logical zero or one. The window detector 31 has a high input impedance, (10 MΩ in this example), since the input impedance of the comparators is very high, and the only other contributing circuit element, the three-state gate TRI-S2 is at a high-impedance state. The window detector 31 accepts a very high impedance source, open circuit and 2.5 V voltage as the indefinite state input. When a logical one (input voltage>3.33 V) or zero (input voltage<1.66 V) input is detected, the window detector's output will be at logical one and this will propagate through the gate AND1 to enable the three-state gate TRI-S1 which will then pass the inverted (by inverter INV3) A1 input as its output to the terminal A2, which will now act as a low-impedance (5 kΩ) output terminal. Normally the TRI-S1 gate output is at a high-impedance state and does not contribute to the state of A2. The logical one signal from the gate AND1 is also inverted by INV1 and forwarded to AND2. The output of AND2 will now become zero and the TRI-S2 gate output will remain at high impedance state. Thus the inverting signal path from A2 to A1 is cut off while the inverting signal path from A1 to A2 is enabled. The 5 kΩ resistors at A1 and A2 serve as current limiting devices in case a possible input logic state contests a possible output logic state.
When a logical signal is connected to the A2 input instead of A1, the operation is the mirror image of the previous description, and the inverting signal path from A2 to A1 is enabled. Thus it can be seen that this circuit implements the bi-directional entanglement rule between two bi-directional terminals.
The circuit shown in
It is self-evident that the circuit shown in
Next the invention will be described in the context of reverse computation of functions. Certain mathematical functions are easy to compute in one direction, but difficult and time consuming in the reverse direction. An example of these computations is the factoring of large integers. A product of two large integers can be easily computed, but if the product is given, then finding the factors is extremely time-consuming with any of the algorithms generally known today.
According to common practice the forward computation of a function can be realized by a network of logic elements. When input numbers are inserted, signal paths emerge and converge at the correct output. A hypothetical reverse computation would involve the activation of these signal paths in reverse order so that the given result would evoke signal paths that would converge at the desired input values. Usually this reverse activation will not lead to unequivocal signal paths, however. Indefinite states will occur here and there; these states can be considered as the superimposition of logical one and zero. However, this superimposition can be made to collapse due to the constrictions given by the overall computation; in that case the logical nodes would be entangled according to the rules of computation. In other cases some superimposed nodes could be forced into one or the other state; in that case the rest of the network nodes would collapse due to the entanglement rules. In this way the network could be made to execute the computation in reversed order. However, this kind of reverse computation is not possible with existing logic elements as these do not communicate any information at their output nodes back to their input nodes. Also they do not contain the necessary superimposed states. Accordingly, one aspect of this invention is the logic circuitry that enables this kind of reverse computation of logic functions.
Conventional logic circuits include the elements NOT (logical inversion), AND, OR, NOT-AND (“NAND”), NOT-OR (“NOR”), EXCLUSIVE-OR (“XOR”), etc. A NOT element has only one input, while the others have multiple inputs. The operation of each of these elements is defined by a truth table that gives an unequivocal output for each combination of inputs. At any point of time, each input or output may have only one of two values, either “true” (“1”) or “false” (“0”). The construction of a reverse logic circuit would involve the realization of its truth table in reversed order.
If the input C 62 of the reverse AND element 61 is set to “0”, the outputs A and B, 63 and 64, will have ones and zeros superimposed, as depicted by the “φ” symbols. This superimposition will collapse if one of the outputs A and B is forced to logical one. This kind of collapse can take place in networks consisting of interconnected logic elements.
It is well known that a NAND gate, which can be created from an inverter (NOT element) plus an AND gate, is a logically complete element, since any logical operation can be realized by various combinations of NAND gates. For practical circuits, however, some combinatory circuits will be considered directly. In the following two basic binary summing circuits will be considered.
It can be seen that a condition S=1 and CO=1 does not exist. Furthermore, there is a set 88 of two unequivocal conditions:
If S=0 and CO=0 then A=B=0;
If S=0 and CO=1 then A=B=1.
The only superimposed condition occurs when S=1 and CO=0. In that case A and B are entangled. The superimposed condition is denoted by reference sign 89, as follows:
If S=1 and CO=0 then
If A=1 then B=0;
If B=1 then A=0.
S=1 and CO=0; or
S=0 and CO=1.
Working Example: a Reverse Multiplier
In the following, a practical implementation of a reverse multiplier will be described. The reverse multiplier of this example is simple enough that its operation can be figured out by pen and paper using the rules for reverse logic elements that were presented earlier. Alternatively a computer program can be devised for this purpose. Moreover actual electronic circuits can be designed for the logic elements and thereafter an ordinary circuit simulation program can be used to simulate the operation of the network if the network is a small one. Larger networks can be simulated, but the simulation time will eventually be prohibitive whereas an actual electronic circuit will deliver the result instantly.
Let us consider the multiplication of a three-bit binary number by a two-bit binary number. The binary numbers to be multiplied are [a2 a1 a0] and [b1 b0] wherein a0 and b0 are the least significant digits. The intermediate steps of the multiplication are shown in
The carry digits are marked as c0, c1 and c2. The binary product is [p4 p3 p2 p1 p0] where p0 is the least significant digit. Here the digit-by-digit multiplication is followed by addition.
Binary digit multiplication can be performed by the AND Operation. The addition can be performed by the half adders and full adders that were described earlier.
For demonstration purposes, the network 120 was simulated with a circuit simulator. For example, Electronics Workbench by Interactive Image Technologies, Toronto, Canada, is an example of suitable circuit simulators. The largest number that can be handled with this network is 7×3=21 or in binary notation 111×11=10101. In order to test the network this number 10101 was set as the product to be factored. The network yielded correctly factors 111 and 11. It can be seen that this is kind of a trivial case as there is no ambiguity in the network,
However, in a general case one or more of the nodes marked bi0 to bi6 will remain in a superimposed state, and the network 120 will not settle towards a solution. Due to the symmetry of the possibilities, the network cannot decide between possible signal paths. Therefore the superimposition must be made to collapse by the introduction of slight asymmetry. This can be achieved by feeding appropriate bias signals into the nodes bi0 to bi6, in such a way that the nodes are drawn towards a logical one or zero. The bias must be made weak, for example, by feeding it via a high-impedance element, such that the circuit can override it if contested by other signals.
For example, the network 120 is not able to factor 010102 (decimal 10) but will remain in a superimposed state. But in response to an appropriate bias (a weak logical one to nodes bi1, bi4 and bi6), the network 120 settles towards [a2 a1 a0]=1012 (decimal 5) and [b1 b0]=102 (decimal 2), which is the correct result. Reference sign 128 denotes a set of input and output bit combinations, as well as the bias applied to the nodes bi0 to bi6 and the actual state of the network at these nodes. It will be seen that the network 120 overrides the weak bias applied to node bi4.
A given number may be a product of multiple set of factors. For instance, 16=2×8 or 4×4. Certain bias signals will give one possibility, other bias signals will reveal other possibilities. An integer P, that is the product of two prime numbers A and B, leads to the possibilities 1×P, P×1, A×B and B×A only, and is easier to factorize by the technique according to the invention because there are only small number of possible reverse logic paths.
It is apparent that larger reverse multipliers can be designed along these lines. The exemplary network 120 is described only as a simple illustration of the principles of the invention. It is also apparent that the technique according to the invention is not limited to factorization but can be used to other types of calculations involving reverse computing, provided that the logical reverse computing network is set up appropriately for each specific case.
Hardware Realizations for Reverse Logic Elements
In the above description the reverse logic elements have been shown as “black boxes” in the sense that their internal construction has not been discussed yet. In the following, we will discuss hardware realizations for a logically complete family of logic elements.
As stated above, a key concept of the invention is a superimposition of logical one (true) and zero (false) states. The superimposition of states persists until caused to collapse by means of further information as determined by one or more sets of entanglement rules.
According to an aspect of the invention, the superimposition of states is realized by means of logic elements having a high-impedance state in addition to the conventional states of logical zero or one. In the high-impedance state, the logic element neither supplies nor draws any significant amount of current via its bi-directional terminals. Thus the high-impedance state can be utilized to accept logical states and bias information from external sources (see
The entanglement rules that that specify the allowable bit patterns at the input or output nodes of the circuit can be realized by conventional cross-connected combinatory logic.
As an alternative to a physical realization of such circuits, the circuits can be simulated by computer software.
In practical applications the bias settings can be variable. In the arrangement shown in
For instance, if the circuits shown in
Up to this point in the description of the invention, the true (=one) and false (=zero) states of logical circuits have been free of any connections to any physical quantity, such as voltage, current of electric charge. But in the description of a hardware realization, a connection to some physical quantity must be made, and from now on, the convention to be used is that a high voltage means a logical one and a low voltage means a logical zero, but this convention is not meant to restrict the scope of the invention, and the circuits could be redesigned such that the convention is reversed.
When a logical one, ie a high voltage, is applied to the reverse C input 162, the reverse A and B outputs 163 and 164 will be set to logical one via the two diodes 165 and 166. Thus the logical AND rule 1×1=1 is realized in the reverse direction. Now three rules remain; 1×0=0, 0×1=0 and 0×0=0. It can be seen that when the reverse C input 162 is set to zero, the reverse A and B outputs 163, 164 may have the logical value zero or one and only one of the reverse outputs may have the logical value one. Thus an input value of zero at the reverse C input 162 must not force the reverse A and B outputs 163, 164 to one or zero. Instead, both values (one and zero) must be allowed simultaneously; thus the superimposed state is needed. This is provided by the high reverse impedance of the two diodes 165A and 165B and the high-impedance outputs states of the 3-state gates. However, if one of the reverse outputs 163, 164 is externally forced to logical one, then the other output must be forced to zero, because 0×1=0 or 1×0=0. An entanglement rule is needed here that does this. This rule is implemented here by the two cross-connected 3-state logic gates 166A and 166B. If, for example, the reverse A output 163 is forced to logical one, then the 3-state logic gate 166B of the reverse B output is set to conducting state and the logical zero at the reverse C input 162 is transmitted to the reverse B output 164. Thus the required entanglement rule is implemented. It is obvious that other circuit implementations exist that realize the required superimposition and entanglement rules within the framework of this invention.
As stated above, in connection with 4, a reverse NOT element is the NOT element itself with the input and output terminals swapped. As is well known, AND elements and NOT elements can be combined in various ways to implement any logical circuit, and the same is true for their reverse variants, and the above description can be considered enabling, at least theoretically. For practical purposes, however, it is beneficial to consider some more complex circuits directly.
It is readily apparent to a person skilled in the art that, as the technology advances, the inventive concept can be implemented in various ways. Hardware realizations of the embodiments of the invention have been described in the context of electronic circuits in which a high voltage means logical true and a low voltage means logical false, but this is only a non-restricting example. The invention and its embodiments are not limited to the examples described above but may vary within the scope of the claims.
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|U.S. Classification||326/56, 326/136, 326/21|
|International Classification||H03K19/003, G06F17/50, G06F17/00, H03K19/02|
|Mar 29, 2011||AS||Assignment|
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Effective date: 20070322
Owner name: SPYDER NAVIGATIONS L.L.C., DELAWARE
|Jul 22, 2011||AS||Assignment|
Effective date: 20110718
Free format text: MERGER;ASSIGNOR:SPYDER NAVIGATIONS L.L.C.;REEL/FRAME:026637/0611
Owner name: INTELLECTUAL VENTURES I LLC, DELAWARE
|Jun 24, 2014||FPAY||Fee payment|
Year of fee payment: 8