US RE43514 E1 Abstract The invention relates to circuit elements and computing networks for resolving logical entanglement, in which the allowed logical value of a variable in a set of variables depends on the logical values of the other variables in the set. A circuit element according to the invention comprises two or more logically entangled bi-directional terminals, wherein each bi-directional terminal can assume any one of three logical states, which are a logical true state, a logical false state, and an indefinite state, in which state the bi-directional terminal accepts one of the logical true and logical false states as an external input from an external source. An entanglement logic resolves the logical state of the bi-directional terminals according to a predetermined set of logical entanglement rules between the bi-directional terminals.
Claims(21) 1. A circuit element comprising:
two or more logically entangled bi-directional terminals, wherein each bi-directional terminal can assume any one of three logical states, which are:
(a) a logical true state;
(b) a logical false state; and
(c) an indefinite state, in which state the bi-directional terminal accepts one of the logical true and logical false states as an external input from an external source; and
an entanglement logic for resolving the logical state of each of the bi-directional terminals according to a predetermined set of logical entanglement rules between the bi-directional terminals, wherein the logical state of one of the two or more logically entangled bi-directional terminals is dependent on the logical state of another of the two or more logically entangled bi-directional terminals.
2. A circuit element according to
3. A circuit element according to
4. A circuit element according to claim
1 3, wherein the inputs to the set of additional terminals collectively determine the logical state of one or more of the bi-directional terminals.5. A circuit element according to
6. A computer program product including program instructions, wherein the program instructions cause a computer to simulate the circuit element according to
instructions to accept one of a logical true state and a logical false state as an input from an external source at one of two or more logically entangled bi-directional terminals; and
instructions to resolve a logical state of each of the two or more logically entangled bi-directional terminals according to a predetermined set of logical entanglement rules between the two or more logically entangled bi-directional terminals, wherein the logical state of one of the two or more logically entangled bi-directional terminals is dependent on the logical state of another of the two or more logically entangled bi-directional terminals.
7. A network for logical deduction, the network comprising:
two or more circuit elements, each of which comprises:
two or more logically entangled bi-directional terminals, wherein each bi-directional terminal can assume any one of three logical states, which are:
(a) a logical true state;
(b) a logical false state; and
(c) an indefinite state, in which state the bi-directional terminal accepts one of the logical true and logical false states as an external input from an external source; and
an entanglement logic for resolving the logical state of each of the bi-directional terminals according to a predetermined set of logical entanglement rules between the bi-directional terminals;
wherein the network further comprises a set of additional terminals, each additional terminal accepting a logical true state or logical false state as an input, wherein the inputs to the set of additional terminals collectively determine which of several sets of logical entanglement rules are to be used for said resolving.
8. A network according to
9. A network according to
10. A network according to
11. A network according to
12. A network according to
13. A network according to
14. A network according to
15. A network according to
a first routine for entering a set of bias values to the bias elements;
a second routine for verifying an output provided by the network under the set of bias values; and
a third routine for modifying the set of bias values and for re-executing the first and second routines until the second routine positively verifies the output.
16. A computer program product including program instructions, wherein the program instructions cause a computer to simulate the network according to
instructions to accept one of a logical true state and a logical false state as an input from an external source at one of two or more logically entangled bi-directional terminals; and
instructions to resolve a logical state of each of the two or more logically entangled bi-directional terminals according to a predetermined set of logical entanglement rules between the two or more logically entangled bi-directional terminals; and
instructions to accept one of a second logical true state or a second logical false state as an input at each terminal of a set of additional terminals, wherein the inputs to the set of additional terminals collectively determine which of several sets of logical entanglement rules are to be used to resolve the logical state.
17. A method comprising:
accepting one of a logical true state and a logical false state as an input from an external source at one of two or more logically entangled bi-directional terminals; and resolving a logical state of each of the two or more logically entangled bi-directional terminals according to a predetermined set of logical entanglement rules between the two or more logically entangled bi-directional terminals, wherein the logical state of one of the two or more logically entangled bi-directional terminals is dependent on the logical state of another of the two or more logically entangled bi-directional terminals. 18. The method of claim 17, further comprising biasing one or more nodes of a network towards one of the logical states.
19. The method of claim 18, further comprising entering a set of bias values to bias elements in the network.
20. The method of claim 19, further comprising verifying an output provided by the network under the set of bias values.
21. The method of claim 20, further comprising modifying the set of bias values until the output is positively verified.
Description This application is a Reissue application of U.S. Ser. No. 10/803,094, filed Mar. 18, 2004, now U.S. Pat. No. 7,161,385, granted Jan. 9, 2007. The invention relates to parallel computational networks and circuit elements for such networks. The invention can be used in several applications in which variable values are connected by logical rules, including but not limited to applications in which the object is to perform reverse calculations, ie, calculations in which a result is known but the object is to find a set of starting values that gives the known result. There are several mathematical or logical operations which are grossly asymmetrical, which means that it is a straightforward task to carry out the operation in one direction but no fast algorithms are known or even supposed to exist for the reverse calculation. An object of the present invention is to provide a circuit element and a parallel computational network that facilitate performing such operations. The object of the invention is achieved by the methods and equipment which are characterized by what is stated in the independent claims. Preferred embodiments of the invention are disclosed in the dependent claims. In order to provide a concrete but non-limiting example, the invention is first described in the context of reverse computation. In forward computation, a given set of input variables produces a definite set of output variables. But with reverse computation a set of given output variables is not always sufficient to determine a corresponding set of input variables. A simple example is the exclusive or operation, or XOR: C=A XOR B. As is well known, C is true if and only if precisely one of the input variables A and B is true. For any set of input variables A and B, the output variable C can be determined, but the reverse is not true: a given value of C is not sufficient in itself to determine the values of A and B. For instance, if C is true then either A is true and B false or B is true and A is false. In this way both A and B may have the values of true and false and are thus in an indefinite state. However, these states are logically entangled; as soon as the value of A or B is fixed the value of the other is fixed, too. If the value of A is set to be true then B must be false and vice versa, and no degrees of freedom remain. Thus the A and B variables of a reverse-XOR element are logically entangled. Thus an aspect of the invention is a circuit element capable of sustaining and processing a set of logically entangled variables with indefinite states. Another aspect of the invention is a parallel computational network that employs these inventive circuit elements. Yet another aspect is computer software whose execution in a computer creates the inventive circuit elements and parallel computational networks by computer simulation. A key concept underlying the present invention is the logical entanglement. The entanglement, as used herein, means that the allowed logical value of a variable in a set of two or more variables depends on the logical values of the other variables in the set. For example: Let there be a number of logical variables A The rule f The exclusion rule means that if A Instead of one fixed rule, a more complicated deduction may require several sets of rules between the logical variables. Let there be a number of rules f Here g is the rule that gives the rule f An aspect of the invention is a circuit element that implements these principles. The circuit realizes the abovementioned rules f and g. The element's A variable inputs A In practical applications several of the above circuits are assembled in a network in which a number of the A variable inputs are tied to other A inputs and B inputs. This presents a problem; the A inputs also operate as outputs and according to normal circuit practice, the outputs of logical circuits should not be tied together as the competition of high and low levels may occur, which may result in the destruction of the connected circuits. Therefore the actual circuitry must be designed in a special way that solves this problem. Likewise, when we consider the previous example of the exclusion between two variables A Thus a first aspect of the invention is a logic element or component that permits logical deduction as described above. The circuit element comprises: -
- two or more logically entangled bi-directional terminals, wherein each bi-directional terminal can assume any one of three logical states, which are:
- (a) a logical true state;
- (b) a logical false state; and
- (c) an indefinite state, in which state the bi-directional terminal accepts one of the logical true and logical false states as an external input from an external source; and
- an entanglement logic for resolving the logical state of each of the bi-directional terminals according to a predetermined set of logical entanglement rules between the bi-directional terminals.
A second aspect of the invention is a parallel computing network that comprises: two or more circuit elements, each of which comprises: (a) a logical true state; (b) a logical false state; and an entanglement logic for resolving the logical state of each of the bi-directional terminals according to a predetermined set of logical entanglement rules between the bi-directional terminals; wherein the network further comprises a set of additional terminals, each additional terminal accepting a logical true state or logical false state as an input, wherein the inputs to the set of additional terminals collectively determine which of several sets of logical entanglement rules are to be used for said resolving. A third aspect of the invention is a computer program product that comprises computer program code for implementing the first and/or second aspects of the invention via computer simulation. In the following the invention will be described in greater detail by means of preferred embodiments with reference to the attached drawings, in which: Here this example is described in more detail. There is a bi-directional entanglement rule between the A -
- if A
**1**=φ (an indefinite state) then the state of A**2**is not affected - If A
**1**=0 then A**2**=1 - if A
**1**=1 then A**2**=0 - if A
**2**=φ (indefinite state) then the state of A**1**is not affected - if A
**2**=0 then A**1**=1 - if A
**2**=1 then A**1**=0
- if A
The comparators Comp When a logical signal is connected to the A The circuit shown in It is self-evident that the circuit shown in Next the invention will be described in the context of reverse computation of functions. Certain mathematical functions are easy to compute in one direction, but difficult and time consuming in the reverse direction. An example of these computations is the factoring of large integers. A product of two large integers can be easily computed, but if the product is given, then finding the factors is extremely time-consuming with any of the algorithms generally known today. According to common practice the forward computation of a function can be realized by a network of logic elements. When input numbers are inserted, signal paths emerge and converge at the correct output. A hypothetical reverse computation would involve the activation of these signal paths in reverse order so that the given result would evoke signal paths that would converge at the desired input values. Usually this reverse activation will not lead to unequivocal signal paths, however. Indefinite states will occur here and there; these states can be considered as the superimposition of logical one and zero. However, this superimposition can be made to collapse due to the constrictions given by the overall computation; in that case the logical nodes would be entangled according to the rules of computation. In other cases some superimposed nodes could be forced into one or the other state; in that case the rest of the network nodes would collapse due to the entanglement rules. In this way the network could be made to execute the computation in reversed order. However, this kind of reverse computation is not possible with existing logic elements as these do not communicate any information at their output nodes back to their input nodes. Also they do not contain the necessary superimposed states. Accordingly, one aspect of this invention is the logic circuitry that enables this kind of reverse computation of logic functions. Conventional logic circuits include the elements NOT (logical inversion), AND, OR, NOT-AND (“NAND”), NOT-OR (“NOR”), EXCLUSIVE-OR (“XOR”), etc. A NOT element has only one input, while the others have multiple inputs. The operation of each of these elements is defined by a truth table that gives an unequivocal output for each combination of inputs. At any point of time, each input or output may have only one of two values, either “true” (“1”) or “false” (“0”). The construction of a reverse logic circuit would involve the realization of its truth table in reversed order. If the input C It is well known that a NAND gate, which can be created from an inverter (NOT element) plus an AND gate, is a logically complete element, since any logical operation can be realized by various combinations of NAND gates. For practical circuits, however, some combinatory circuits will be considered directly. In the following two basic binary summing circuits will be considered. It can be seen that a condition S=1 and C If S=0 and C If S=0 and C The only superimposed condition occurs when S=1 and C If S=1 and C If A=1 then B=0; If B=1 then A=0. S=1 and C S=0 and C Working Example: a Reverse Multiplier In the following, a practical implementation of a reverse multiplier will be described. The reverse multiplier of this example is simple enough that its operation can be figured out by pen and paper using the rules for reverse logic elements that were presented earlier. Alternatively a computer program can be devised for this purpose. Moreover actual electronic circuits can be designed for the logic elements and thereafter an ordinary circuit simulation program can be used to simulate the operation of the network if the network is a small one. Larger networks can be simulated, but the simulation time will eventually be prohibitive whereas an actual electronic circuit will deliver the result instantly. Let us consider the multiplication of a three-bit binary number by a two-bit binary number. The binary numbers to be multiplied are [a The carry digits are marked as c Binary digit multiplication can be performed by the AND Operation. The addition can be performed by the half adders and full adders that were described earlier. For demonstration purposes, the network However, in a general case one or more of the nodes marked bi For example, the network A given number may be a product of multiple set of factors. For instance, 16=2×8 or 4×4. Certain bias signals will give one possibility, other bias signals will reveal other possibilities. An integer P, that is the product of two prime numbers A and B, leads to the possibilities 1×P, P×1, A×B and B×A only, and is easier to factorize by the technique according to the invention because there are only small number of possible reverse logic paths. It is apparent that larger reverse multipliers can be designed along these lines. The exemplary network Hardware Realizations for Reverse Logic Elements In the above description the reverse logic elements have been shown as “black boxes” in the sense that their internal construction has not been discussed yet. In the following, we will discuss hardware realizations for a logically complete family of logic elements. As stated above, a key concept of the invention is a superimposition of logical one (true) and zero (false) states. The superimposition of states persists until caused to collapse by means of further information as determined by one or more sets of entanglement rules. According to an aspect of the invention, the superimposition of states is realized by means of logic elements having a high-impedance state in addition to the conventional states of logical zero or one. In the high-impedance state, the logic element neither supplies nor draws any significant amount of current via its bi-directional terminals. Thus the high-impedance state can be utilized to accept logical states and bias information from external sources (see The entanglement rules that that specify the allowable bit patterns at the input or output nodes of the circuit can be realized by conventional cross-connected combinatory logic. As an alternative to a physical realization of such circuits, the circuits can be simulated by computer software. In practical applications the bias settings can be variable. In the arrangement shown in For instance, if the circuits shown in Up to this point in the description of the invention, the true (=one) and false (=zero) states of logical circuits have been free of any connections to any physical quantity, such as voltage, current of electric charge. But in the description of a hardware realization, a connection to some physical quantity must be made, and from now on, the convention to be used is that a high voltage means a logical one and a low voltage means a logical zero, but this convention is not meant to restrict the scope of the invention, and the circuits could be redesigned such that the convention is reversed. When a logical one, ie a high voltage, is applied to the reverse C input As stated above, in connection with 4, a reverse NOT element is the NOT element itself with the input and output terminals swapped. As is well known, AND elements and NOT elements can be combined in various ways to implement any logical circuit, and the same is true for their reverse variants, and the above description can be considered enabling, at least theoretically. For practical purposes, however, it is beneficial to consider some more complex circuits directly. It is readily apparent to a person skilled in the art that, as the technology advances, the inventive concept can be implemented in various ways. Hardware realizations of the embodiments of the invention have been described in the context of electronic circuits in which a high voltage means logical true and a low voltage means logical false, but this is only a non-restricting example. The invention and its embodiments are not limited to the examples described above but may vary within the scope of the claims. Patent Citations
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