|Publication number||USRE43536 E1|
|Application number||US 12/500,434|
|Publication date||Jul 24, 2012|
|Filing date||Jul 9, 2009|
|Priority date||Feb 7, 2002|
|Also published as||US7242082, US20060055039|
|Publication number||12500434, 500434, US RE43536 E1, US RE43536E1, US-E1-RE43536, USRE43536 E1, USRE43536E1|
|Original Assignee||Aprolase Development Co., Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (46), Non-Patent Citations (8), Classifications (23), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of U.S. patent application Ser. No. 10/360,244 filed Feb. 7, 2003, U.S. Pat. No. 6,967,411, entitled “Stackable Layers Containing Ball Grid Array Packages”, which in turn claims priority to provisional application No. 60/354,442 filed Feb. 7, 2002 and provisional application No. 60/355,955 filed Feb. 12, 2002. This is a broadening Reissue application of U.S. patent application Ser. No. 11/229,351, filed Sep. 15, 2005 (now U.S. Pat. No. 7,242,082, granted Jul. 10, 2007). U.S. patent application Ser. No. 11/229,351 is a continuation of U.S. patent application Ser. No. 10/360,244, filed on Feb. 7, 2003 (now U.S. Pat. No. 6,967,411), which in turn claims priority to U.S. Provisional Patent Application No. 60/354,442, filed on Feb. 7, 2002, and to U.S. Provisional Patent Application No. 60/355,955, filed on Feb. 12, 2002.
1. Field of the Invention
The present invention relates to the dense packaging of electronic circuitry and specifically to the stacking of ball grid army (BGA) integrated circuit packages. The invention is also suitable for the stacking of fine ball grid array (FBGA) integrated circuit packages, micro-ball grid array packages and for bump-bonded bare die to form stackable layers which can be combined to form multi-layer electronic modules.
2. Description of the Background Art
The electronics industry continues to seek smaller, denser electronic packaging. An important advance in this regard has been the use of three-dimensional packaging techniques using stacked bare or packaged integrated circuit die.
Most of the background art disclosures describe methods of stacking multiple unpackaged IC chips. Oguchi et al., U.S. Pat. No. 5,332,922, Miyano et al., U.S. Pat. No. 5,440,171, and Choi et al., U.S. Pat. No. 5,677,569, disclose methods of stacking IC chips within a single package. Jeong et al., U.S. Pat. No. 5,744,827, discloses a new type of custom chip packaging which permits stacking, but which does not allow the use of off-the-shelf packaged IC's. Burns, U.S. Pat. No. 5,484,959, shows a method of stacking TSOP packages which requires multiple leadframes attached above and below each TSOP and a system of vertical bus-bar interconnections, but which does not conveniently allow an expansion of the number of vertically interconnecting leads.
The assignee of this application, Irvine Sensors Corporation, has been a leader in developing high-density packaging of IC chips, for use in focal plane modules and for use in a variety of computer functions such as electronic memory. Examples of Irvine Sensors Corp.'s high-density electronic packaging are disclosed in U.S. Pat. No. 4,672,737, to Carson, et al.; U.S. Pat. No. 4,551,629, to Carson et al.; U.S. Pat. No. 5,688,721, to Johnson; U.S. Pat. No. 5,347,428 to Carson, et al.; and U.S. Pat. No. 6,028,352 to Eide, all of which are fully incorporated herein.
The present invention relates to the stacking of layers containing integrated circuit chips (ICs), thereby obtaining high-density electronic circuitry. In general, the goal of the present invention is to combine high circuit density with reasonable cost. A unique aspect of this invention is that it provides a low cost method of stacking commercially available IC's in BGA packages while allowing the independent routing of several non-common I/O (input/output) signals from upper-level layers to lower layers or to the bottom of the stack. Cost reduction is accomplished by utilizing relatively low cost interposer boards to reroute leads to an access plane and by the ability to stack pre-packaged and pre-tested off-the-shelf BGA packages.
None of the background art addresses the need for compact, dense memory stacks that take advantage of the high speed and small outline of a BGA package that are both low cost and highly reliable. It is therefore an object of the invention to provide a stackable layer formed from a BGA package that can be assembled at a relatively low cost and which is structurally and thermally sound. It is a further object of the invention to provide a stack of BGA layers that can provide high electronic density in a very small volume and which is compatible with a conventional BGA footprint on a printed circuit board. It is yet a further object of the invention to provide a low-cost method for manufacturing a stackable layer incorporating a BGA package and a method for manufacturing a stack of such layers.
The present invention provides stackable layers which may be interconnected to form a high-density electronic module. This application further discloses a stack of layers electrically interconnected in the vertical direction, suitable for mounting onto a PCB (printed circuit board) or other electronic device. This application further discloses a method for starting with standard BGA packages and manufacturing a stacked IC-containing package using interposer interconnections which are routed in the vertical direction along one or more access planes.
The invention generally consists of BGA packaged die that are electrically interconnected to conductive traces on an interposer board formed from a dielectric material. The interposer board serves to reroute electronic signals from the BGA to the periphery, or access edge, of the interposer. The interposer may have a single layer or multiple layers of conductive traces much like conventional printed circuit board technology.
The BGA package is solder-reflowed to the interposer and under-filled with an epoxy to form a stackable layer. The formed individual layers may then be aligned and bonded to form a multi-layer structure which includes at least one access plane. The conductive traces that terminate at the access edges are lapped and exposed, then rerouted to the desired locations to allow the interconnection of several non-common signals (e.g., chip enable and/or data lines) from an upper layer to a lower layer of a stack of layers.
Referring now to the figures where like numerals designate like elements among the several views,
Conductive traces made of copper or other conductive material are formed on the interposer board in a manner similar to that used in printed circuit board manufacturing. The conductive traces are patterned on the interposer board using conventional photolithography techniques so as to form solder ball pads 20 for the receiving and electrical connection of solder balls 5. The interposer board may include a single layer of conductive traces 15 or, in an alternative embodiment, multiple layers of conductive traces (not shown).
To assemble the device, solder balls 5 of BGA package 1 are aligned and electrically connected to solder ball pads 20 as is shown in
Upon completion of the reflow process, a stackable BGA layer 35 is formed as is illustrated in
Turning now to
Mechanical assembly of multiple layers consists generally of aligning two or more layers 35 in a suitable fixture and bonding together using the appropriate adhesive. After the adhesive has cured, the sides of stack 40 that include access leads 30, i.e., access plane 45, are ground and lapped to expose the access leads as is illustrated in
In this manner a high capacity, multi-layer module is provided that is low cost and which is readily received into existing BGA footprints.
From the foregoing description, it will be apparent the apparatus and method disclosed in this application will provide the significant functional benefits summarized in the introductory portion of the specification.
The following claims are intended not only to cover the specific embodiments disclosed, but also to cover the inventive concepts explained herein with the maximum breadth and comprehensiveness permitted by the prior art.
Many alterations and modifications may be made by those having ordinary skill in the art without departing from the spirit and scope of the invention. Therefore, it must be understood that the illustrated embodiment has been set forth only for the purposes of example and that it should not be taken as limiting the invention as defined by the following claims. For example, notwithstanding the fact the elements of a claim are set forth below in a certain combination, it must be expressly understood that the invention includes other combinations of fewer, more or different elements, which are disclosed above even though not claimed in such combinations.
The words used in this specification to describe the invention and its various embodiments are to be understood not only in the sense of their commonly defined meanings, but to include by special definition in this specification structure, material or acts beyond the scope of the commonly defined meanings. Thus, if an element can be understood in the context of this specification as including more than one meaning, then its use in a claim must be understood as being generic to all possible meanings supported by the specification and by the word itself.
The definitions of the words or elements of the following claims are, therefore, defined in this specification to include not only the combination of elements which are literally set forth, but all equivalent structure, material or acts for performing substantially the same function in substantially the same way to obtain substantially the same result. In this sense it is therefore contemplated that an equivalent substitution of two or more elements may be made for any one of the elements in the claims below or that a single element may be substituted for two or more elements in a claim. Although elements may be described above as acting in certain combinations and even initially claimed as such, it is to be expressly understood that one or more elements from a claimed combination can in some cases be excised from the combination and that the claimed combination may be directed to a sub-combination or variation of a sub-combination.
Insubstantial changes from the claimed subject matter as viewed by a person with ordinary skill in the art, now known or later devised, are expressly contemplated as being equivalently within the scope of the claims. Therefore, obvious substitutions now or later known to one with ordinary skill in the art are defined to be within the scope of the defined elements.
The claims are thus to be understood to include what is specifically illustrated and described above, what is conceptually equivalent, what can be obviously substituted and also what essentially incorporates the essential idea of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4551629 *||Jan 23, 1984||Nov 5, 1985||Irvine Sensors Corporation||Detector array module-structure and fabrication|
|US4672737||Aug 2, 1985||Jun 16, 1987||Irvine Sensors Corporation||Detector array module fabrication process|
|US5043794||Sep 24, 1990||Aug 27, 1991||At&T Bell Laboratories||Integrated circuit package and compact assemblies thereof|
|US5332922||Apr 26, 1991||Jul 26, 1994||Hitachi, Ltd.||Multi-chip semiconductor package|
|US5347428||Dec 3, 1992||Sep 13, 1994||Irvine Sensors Corporation||Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip|
|US5440171||Mar 8, 1993||Aug 8, 1995||Hitachi, Ltd.||Semiconductor device with reinforcement|
|US5484959||Dec 11, 1992||Jan 16, 1996||Staktek Corporation||High density lead-on-package fabrication method and apparatus|
|US5675180||Jun 23, 1994||Oct 7, 1997||Cubic Memory, Inc.||Vertical interconnect process for silicon segments|
|US5677569||Oct 27, 1995||Oct 14, 1997||Samsung Electronics Co., Ltd.||Semiconductor multi-package stack|
|US5688721||Mar 26, 1996||Nov 18, 1997||Irvine Sensors Corporation||3D stack of IC chips having leads reached by vias through passivation covering access plane|
|US5696031||Nov 20, 1996||Dec 9, 1997||Micron Technology, Inc.||Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice|
|US5744827||Nov 26, 1996||Apr 28, 1998||Samsung Electronics Co., Ltd.||Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements|
|US5786237||Aug 16, 1995||Jul 28, 1998||International Business Machines Corporation||Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips|
|US5973403||Aug 19, 1997||Oct 26, 1999||Micron Technology, Inc.||Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice|
|US6023098||Jan 25, 1996||Feb 8, 2000||Fujitsu Limited||Semiconductor device having terminals for heat radiation|
|US6028352||Jun 10, 1998||Feb 22, 2000||Irvine Sensors Corporation||IC stack utilizing secondary leadframes|
|US6052287 *||Dec 9, 1997||Apr 18, 2000||Sandia Corporation||Silicon ball grid array chip carrier|
|US6081026||Nov 13, 1998||Jun 27, 2000||Fujitsu Limited||High density signal interposer with power and ground wrap|
|US6084781 *||Jun 4, 1998||Jul 4, 2000||Micron Electronics, Inc.||Assembly aid for mounting packaged integrated circuit devices to printed circuit boards|
|US6271598||Aug 22, 1997||Aug 7, 2001||Cubic Memory, Inc.||Conductive epoxy flip-chip on chip|
|US6303992||Jul 6, 1999||Oct 16, 2001||Visteon Global Technologies, Inc.||Interposer for mounting semiconductor dice on substrates|
|US6323060||May 5, 1999||Nov 27, 2001||Dense-Pac Microsystems, Inc.||Stackable flex circuit IC package and method of making same|
|US6365978||Apr 2, 1999||Apr 2, 2002||Texas Instruments Incorporated||Electrical redundancy for improved mechanical reliability in ball grid array packages|
|US6639416||Jul 2, 2001||Oct 28, 2003||Micron Technology, Inc.||Method and apparatus for testing semiconductor dice|
|US6787921||Nov 8, 2002||Sep 7, 2004||Siliconware Precision Industries Co., Ltd.||Array structure of solder balls able to control collapse|
|US6818977||Jul 17, 2002||Nov 16, 2004||Micron Technology, Inc.||Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages|
|US6967411||Feb 7, 2003||Nov 22, 2005||Irvine Sensors Corporation||Stackable layers containing ball grid array packages|
|US7511369||Feb 22, 2005||Mar 31, 2009||Irvine Sensors Corp.||BGA-scale stacks comprised of layers containing integrated circuit die and a method for making the same|
|US7652362||Jul 12, 2006||Jan 26, 2010||Hynix Semiconductor Inc.||Semiconductor package stack with through-via connection|
|US20020048849||Jun 25, 2001||Apr 25, 2002||Isaak Harlan R.||Stackable flex circuit IC package and method of making same|
|US20020061665||Jan 14, 2002||May 23, 2002||Victor Batinovich||Method and apparatus for vertically stacking and interconnecting ball grid array (BGA) electronic circuit devices|
|US20020076919||May 23, 2001||Jun 20, 2002||Peters Michael G.||Composite interposer and method for producing a composite interposer|
|US20020094603||Mar 6, 2002||Jul 18, 2002||Isaak Harlan R.||Three-dimensional memory stacking using anisotropic epoxy interconnections|
|US20020105083||Feb 1, 2002||Aug 8, 2002||Eic Corporation||Multi-layer interconnect module and method of interconnection|
|US20030043650||Jul 31, 2002||Mar 6, 2003||Mitsubishi Denki Kabushiki Kaisha||Multilayered memory device|
|US20030173673||Jul 20, 2001||Sep 18, 2003||Christian Val||Method for distributed shielding and/or bypass for electronic device with three dimensional interconnection|
|US20030232460||Jun 27, 2002||Dec 18, 2003||Poo Chia Yong||Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods|
|US20040012078||Jul 22, 2002||Jan 22, 2004||Hortaleza Edgardo R.||Folded tape area array package with one metal layer|
|JP2001085606A||Title not available|
|JP2001223325A||Title not available|
|JP2003188312A||Title not available|
|JPH03501428A||Title not available|
|WO1992006904A1||Oct 22, 1990||Apr 30, 1992||Hansen Darrell L||Optical storage disc protector|
|WO1998031738A1||Jan 16, 1998||Jul 23, 1998||Loctite Corporation||Thermosetting resin compositions|
|WO2003038861A2||Oct 25, 2002||May 8, 2003||Irvine Sensors Corporation||A method of stacking layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers|
|WO2005018000A1||Aug 8, 2003||Feb 24, 2005||Irvine Sensors Corporation||Stackable layers containing ball grid array packages|
|1||International Search Report for PCT/US2003/024706 mailed on Mar. 8, 2004.|
|2||Non-final Office Action issued in U.S. Appl. No. 11/825,643 and mailed on Sep. 4, 2009.|
|3||Notice of Allowance for U.S. Appl. No. 11/825,643 mailed Dec. 14, 2009.|
|4||Notice of Allowance issued in U.S. Appl. No. 12/731,970 and mailed Jan. 6, 2011.|
|5||Notice of Allowance issued in U.S. Appl. No. 12/731,970 and mailed Mar. 11, 2011.|
|6||Office Action for Japanese Patent Application No. 2005-507894 dispatched Oct. 27, 2009. (English translation provided).|
|7||Office Action issued in Japanese Patent Application No. 2005-507894 drafted on May 18, 2009 and mailed on May 26, 2009 (English translation provided).|
|8||Supplementary European Search Report for European Patent Application No. 03818224.2 dated Oct. 28, 2009.|
|U.S. Classification||257/690, 257/E21.614, 257/776, 257/E23.001, 257/686, 257/693, 257/E25.006, 257/781, 257/780, 257/773, 257/777, 257/784, 438/109|
|International Classification||H01L21/00, H01L23/48|
|Cooperative Classification||H01L2924/0002, H01L2225/1064, H01L2225/1023, H01L2225/06572, H01L25/105, H01L2225/06517, H01L2225/06551|
|Nov 4, 2009||AS||Assignment|
Owner name: APROLASE DEVELOPMENT CO., LLC, DELAWARE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IRVINE SENSORS CORPORATION;REEL/FRAME:023469/0062
Effective date: 20090316
|Jan 1, 2013||CC||Certificate of correction|
|Dec 29, 2014||FPAY||Fee payment|
Year of fee payment: 8
|Dec 30, 2015||AS||Assignment|
Owner name: NYTELL SOFTWARE LLC, DELAWARE
Free format text: MERGER;ASSIGNOR:APROLASE DEVELOPMENT CO., LLC;REEL/FRAME:037406/0200
Effective date: 20150826