|Publication number||USRE43557 E1|
|Application number||US 12/714,400|
|Publication date||Jul 31, 2012|
|Filing date||Feb 26, 2010|
|Priority date||Nov 12, 1998|
|Also published as||US6545730|
|Publication number||12714400, 714400, US RE43557 E1, US RE43557E1, US-E1-RE43557, USRE43557 E1, USRE43557E1|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Classifications (12), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
(a) Field of the Invention
The present invention relates to a thin film transistor (TFT) array panel for a liquid crystal display (LCD) and a method for manufacturing the same.
(b) Description of the Related Art
Thin film transistors, which are typically used as a switching element in each pixel of an LCD, have an amorphous silicon layer or a polysilicon layer as an active layer.
The polysilicon thin film transistor, because it has a higher carrier mobility compared to the amorphous silicon thin film transistor, may narrow the widths of signal lines for driving the pixels and may be used in a large-scale, high-quality LCD since a driving circuit may be integrated on the substrate of an LCD. Also, because the driving circuit can be formed on the substrate, the overall cost for manufacturing the LCD may be reduced and the overall LCD size may be reduced.
This liquid crystal display using the polysilicon thin film transistor generally includes a first substrate having a plurality of thin film transistors, and a second substrate having a plurality of red, green and blue color filters. Also, a second substrate has a black matrix having an opening that defines a pixel which serves as a light shield for the regions between adjacent pixels where the electric field cannot fully control the liquid crystal layer.
However, the black matrix decreases the aperture ratio of the LCD because it covers a wider area than is necessary for covering the light leakage in order to compensate for misalignment between the two substrates. To avoid this problem, it is suggested that the black matrix be formed on the first substrate. However, this method increases the total number of processes in manufacturing the LCD because an align key must be formed on the second substrate to align the first substrate and the second substrate.
It is an object of the present invention to provide a TFT array panel for an LCD and a method of manufacturing the same in which the manufacturing method is simplified, and an aperture ratio of the LCD is increased.
To achieve the above object, the present invention provides a TFT array panel for LCDs that a pixel electrode overlaps insulatedly a storage electrode, functioning as a shield that prevents light leakage around the data line. Methods of Manufacturing a TFT array panel for an LCD are also provided.
Further objects and other advantages of the present invention will become apparent from the following description in conjunction with the attached drawings, in which:
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
As shown in
A polysilicon layer 30 is formed on the buffer layer 20. The polysilicon layer 30 includes an undoped channel region 33 located at the center of the polysilicon layer 30, and the source region 31 and the drain region 32 doped with N or P-type impurities. The source region 31 and the drain region 32 are located opposite to each other with respect to the channel region 33. A plurality of gate insulating layers 40 are formed on the polysilicon layer 30 and on the buffer layer 20 between pixels.
A plurality of gate lines 50 are formed on the gate insulating layer 40 in a horizontal direction (in
A plurality of first insulating layers 60, having widths substantially the same as the gate insulating layer 40 and covering the gate lines 50, the gate electrodes 51, the storage electrodes 10 and the storage line 11, are formed on the gate insulating layers 40. Portions of the source region 31 and the drain region 32 of the polysilicon layer 30 are covered by the first insulating layer 60 and the gate insulating layer 40, while remaining portions of the source region 31 and the drain region 32 of the polysilicon layer 30 are left exposed. Source ITO electrode 81 and drain ITO electrode 82 made of indium tin oxide are formed on the exposed portions of the source region 31 and the drain region 32. A pixel electrode 80, integrally connected to the drain ITO electrode 82, is formed on the buffer layer 20. Here, longitudinal edge portions of both sides of the pixel electrode 80 overlap edge portions of the storage electrodes 10, and a lower portion of the pixel electrode 80 overlaps the storage line 11 and the lower gate line 50.
A second insulating layer 90 is formed covering the source ITO electrode 81, the drain ITO electrode 82 and the pixel electrode 80. The second insulating layer 90 has a contact hole 91 exposing a portion of the source ITO electrode 81.
A plurality of data lines 70, transmitting data signals and defining pixels by intersecting the gate line 50, is formed on the second insulating layer 90. The data lines 70 are connected to the source ITO electrode 81 through the contact hole 91 of the second insulating layer 90. The data lines 70 are located between adjacent pixel electrodes 80 and overlap the storage electrodes 10.
A black matrix 210 is formed on an upper insulating substrate 200 facing to the lower substrate 100. The black matrix 210 is provided on the upper insulating substrate 200 at a position corresponding to the location of the thin film transistor comprises the polysilicon layer 30, the source and drain ITO electrodes 81 and 82, the gate electrode 51, and the gate lines 50. Furthermore, a common electrode 220 is formed over an entire surface of the upper substrate 200 covering the black matrix 210 as well.
In the polysilicon liquid crystal display of the first embodiment according to the present invention, the storage electrodes 10 act as a black matrix by preventing the light leakage between pixels. Accordingly, as shown in
In the first embodiment according to the present invention, as shown in
To solve this problem, the second insulating layer 90 may be removed from the areas covering the pixel electrodes 80. This will be described in detail hereinafter.
As shown in
Another problem in the structure of the first (and second) embodiment as shown in
As shown in
In the structure according to third embodiment, the third insulating layer 900 covering the data lines 70 prevents the data lines 70 from shortening with signal lines, even if the signal lines are densely formed on the same layer that the data lines 70 are formed.
A method for manufacturing a thin film transistor array panel according to the first embodiment through the third embodiment of the present invention will now be described with reference to the
First, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Finally, a conductive material is deposited and patterned to form a data line 70 defining pixels by intersecting with the gate line 50. The data line 70 is connected to the source ITO electrode 81 through the contact hole 91.
Here, to manufacture the thin film transistor array panel according to the second embodiment as shown in
Furthermore, to manufacture the thin film transistor array panel according the third embodiment as shown in
In the method of manufacturing a polysilicon TFT array panel according to a preferred embodiment of the present invention, it is desirable that the pixel electrode 80 and the data line 70 do not overlap to minimize parasitic capacitance generated between the pixel electrode 80 and the data line 70. This is realized by making the width of the data line 70 smaller than that of the storage electrode 10, and forming the data line 70 in the boundary of the storage electrode 10.
Furthermore, if there is sufficient storage capacitance, it is possible to omit the forming of the storage line 11. In this case, the storage electrodes 10 are connected to the lower gate line 50.
In the TFT array panel for liquid crystal displays according to the present invention, by forming the storage electrodes such that they function as a black matrix to prevent the leakage of light between pixels on the lower substrate, and a black matrix in only the horizontal direction on the upper substrate, the aperture ratio of the LCD may be increased without encountering misalignment problems between the two substrates, and the manufacturing method may be simplified by reducing the number of manufacturing steps.
In the drawings and specification, there have been disclosed typical preferred embodiments of the present invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5339181 *||Aug 25, 1992||Aug 16, 1994||Samsung Electronics Co., Ltd.||Liquid crystal display comprising a storage capacitor including the closed-ended electrode for providing a current bath for circumventing break|
|US5574582 *||May 18, 1995||Nov 12, 1996||Matsushita Electric Industrial Co., Ltd||Active matrix liquid crystal display panel with scanning electrodes acting as capacitor electrode and black matrix|
|US5742363 *||Aug 21, 1996||Apr 21, 1998||Lg Electronics Inc.||Liquid crystal display and method for fabricating the same in which the gate electrode is formed from two layers having differing widths|
|US5953088 *||Dec 23, 1998||Sep 14, 1999||Kabushiki Kaisha Toshiba||Liquid crystal display with shield electrodes arranged to alternately overlap adjacent pixel electrodes|
|US6118506||Sep 25, 1998||Sep 12, 2000||Semiconductor Energy Laboratory Co., Ltd.||Electro-optical device and method of fabricating same|
|US6275278||Jun 29, 1999||Aug 14, 2001||Hitachi, Ltd.||Liquid crystal display device and method of making same|
|US6281953||Aug 23, 1999||Aug 28, 2001||Hyundai Electronics Industries Co., Ltd.||Liquid crystal display having high aperture ratio and high transmittance and method of manufacturing the same|
|US6330042||Sep 2, 1998||Dec 11, 2001||Lg. Philips Lcd Co., Ltd.||Liquid crystal display and the method of manufacturing the same|
|US6330044||Feb 23, 1998||Dec 11, 2001||Seiko Epson Corporation||Apparatus for providing light shielding in a liquid crystal display|
|US6337234||Jan 22, 2001||Jan 8, 2002||Lg.Philips Lcd Co., Ltd.||Method of fabricating a buried bus coplanar thin film transistor|
|US6344885||Apr 1, 1999||Feb 5, 2002||Hitachi, Ltd.||Liquid crystal display device|
|US6365916||Jul 16, 1999||Apr 2, 2002||Lg. Philips Lcd Co., Ltd.||High aperture LCD with insulating color filters overlapping bus lines on active substrate|
|US6710372 *||Aug 26, 2002||Mar 23, 2004||Samsung Electronics Co., Ltd.||Thin film transistor array panel for liquid crystal display|
|U.S. Classification||349/43, 349/110, 349/38, 349/39|
|International Classification||G02F1/1333, G02F1/1343, G02F1/136, G02F1/1362|
|Cooperative Classification||G02F1/136209, G02F1/136213|
|European Classification||G02F1/1362C, G02F1/1362B|
|Sep 19, 2012||AS||Assignment|
Owner name: SAMSUNG DISPLAY CO., LTD, KOREA, REPUBLIC OF
Effective date: 20120904
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAMSUNG ELECTRONICS, CO., LTD;REEL/FRAME:028989/0629
|Sep 30, 2014||FPAY||Fee payment|
Year of fee payment: 12