Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUST104803 I4
Publication typeGrant
Application numberUS 06/580,962
Publication dateNov 6, 1984
Filing dateFeb 16, 1984
Priority dateJul 13, 1981
Publication number06580962, 580962, US T104803 I4, US T104803I4, US-I4-T104803, UST104803 I4, UST104803I4
InventorsCheng T. Horng
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Self-aligned process for providing an improved high performance bipolar transistor
US T104803 I4
Abstract
A bipolar transistor structure formed in a monolithic silicon semiconductor substrate of p type having a planar surface comprising: a subcollector of n type formed in the substrate; an epitaxial layer of n type formed on said planar surface of said substrate and also having a planar surface, the epitaxial layer having a thickness in the order of 1.0 to 1.5 micrometers; an enclosed deep recessed oxide isolation trench enclosing a transistor structure area of the substrate and the epitaxial layer, the enclosed deep recessed oxide isolation trench having a depth extending from said planar surface of said epitaxial layer through the subcollector region; a shallow recessed oxide isolation trench, the relatively shallow recessed oxide isolation trench being wholly enclosed by the deep recessed oxide isolation trench and intersecting the deep recessed oxide isolation trench at two spaced apart points to divide said transistor structure area enclosed by the deep recessed oxide isolation trench into first and second areas, the first and second areas being electrically connected one to the other by the subcollector region;
a shallow depth emitter region formed in a limited portion of the first area of said epitaxial layer, the emitter region having a depth in the order of 0.1 micrometers;
an active base region formed beneath said emitter region in the limited portion the first area of said epitaxial layer, the active base region having a width in the order of 0.1 micrometers;
an inactive base region surrounding the emitter region and active base region, the inactive base region being wholly contained within the first area of said epitaxial layer;
an emitter-base junction contained within said first area of the epitaxial layer and extending to the surface of the epitaxial layer;
a composite layer of silicon dioxide and silicon nitride having a width of approximately 0.2 to 0.3 micrometers, the composite layer being positioned on the planar surface of the epitaxial layer over the surface juncture of said emitter-base junction, the silicon dioxide having a thickness of approximately 500Å and the silicon nitride layer having a thickness of approximately 500Å;
the second area of the epitaxial layer containing a collector reach through, the shallow recessed oxide isolation trench isolating the collector reach through from the inactive base region;
a layer of polysilicon p type on said planar surface of the epitaxial layer and in physical and electrical contact with the inactive base region, the polysilicon layer extending over a portion of said enclosed relatively deep recessed oxide isolation trench; and,
a base contact physically and electrically contacting the portion of the polysilicon layer which extends over the enclosed deep recessed oxide isolation trench.
Images(5)
Previous page
Next page
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4829015 *Mar 21, 1988May 9, 1989Siemens AktiengesellschaftMethod for manufacturing a fully self-adjusted bipolar transistor
US5234846 *Apr 30, 1992Aug 10, 1993International Business Machines CorporationCodeposition of polysilicon base contact and epitaxial layer, using doped glass layer as dopant source, dielectric, etch stop
US6483163Dec 4, 2000Nov 19, 2002Nikon CorporationPhotoelectric conversion devices and photoelectric conversion apparatus employing the same
EP0293641A1 *May 9, 1988Dec 7, 1988Siemens AktiengesellschaftProcess for the manufacture of a full self-aligned bipolar transistor
Classifications
U.S. Classification257/514, 257/518
International ClassificationH01L29/732
Cooperative ClassificationH01L29/7325
European ClassificationH01L29/732C