Total state condition
US T930005 I4
Description (OCR text may contain errors)
DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16. 1980, 869 0.6. 687. The abstracts 02? Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each abstract indicates the number of pages of specification. including claims and sheets of drawings contained in the application as originally died. The dies or these applications are available to the public tor inspection and reproduction may be purchased for 30 cents a sheet.
Defensive Publication applications have not been examined as to the merits o! alleged invention. The Patent Othce makes no assertion as to the novelty of the disclosed subject matter.
PUBLISHED JANUARY 7, 1975 METHOD FOR PLACING AN ASYNCHRONOUS SEQUENTIAL CIRCUIT INTO A STATE FOR TESTING Dennis K. Chin, New Paltz, and Mu-Yue Hsiao, Poughkeepsie, N.Y., assignors to International Business Machines Corporation, Armonk, N.Y.
Continuation of abandoned application Ser. No. 265,035, June 21, 1972. This application Feb. 21, 1974, Ser. No.
Int. Cl. G06! 15/20 US. Cl. 444-1 2 Sheets Drawing. 23 Pages Specificah'on sianisip vm TESH TESi PATTERN LOGIC GENERATION ClRUUIT IsTAPE PATIERNSi PROGRAM DEStRlPllUii lESlER 2 APPLY} FBUFFER m INPUTS mmwiwcm QEiSERVE unwary is m1 REEULTS A method for determining the homing sequence input patterns required to place any asynchronous sequential circuit into a set-state for testing is provided. The setstate is determined from the total states of an asynchronous sequential circuit generaied by any test pattern generating machine, then deriving the total-state sequence from said set-state in a reverse order starting with the last total-state. The end of the total-state sequence is determined by recognizing the total-state in which there are no state variables. The total-state input patterns generated from this method are utilized in the forward order to place the asynchronous sequential machine into said set-state regardless of the initial state of said asynchronous sequential circuit.
Jan. 7, 1975 0. K. cum ETAL T930,005
METHOD FOR PLACING AN ASYNCHRONOUS SEQUENTIAL CIRCUIT INTO A STATE FOR TESTING Original Filed June 21 1972 2 Sheets-Sheet 1 FIG. 1
STORAGE DEVICE TEST) I TEST PATTERN LOGIC TAPE 4 GENERATION l 7 menu I PATTERNS PROGRAM DESCRIPTiON TESTER 42 fi APPLY V LOGIC BUFFER AND 'NPUTS (HRCUH ilw i OBSERVE UNDER TEST \40 L omPuTy 46 TEST RESULTS 3 26 x 7 A 4 F A 1 8 0R 4 0 0 G5 f FIG. 2 y A V A Li 7 x x z1 00MB lNPUT f LOGIC F1 OUYPUT f (N0 DELAY) F V m FIG. 4
P D =Dj=DELAY=M 52 STATE 9 VARIABLES 4 FIG.6
Jan. 7, 1975 D. K. CHIA ETAL T930,005
MB'IHOD FQIK PLACING AN ASYNCHRONOUS SEQUENTIAL CIRCUIT INTO A STATE FOR TEsTmG Original Filed June 21, 1972 2 Sheets-Sheet :5
l TOTAL STATE CONDITION T GIVEN BY TPG PROGRAM 52 W K=w, KEEP w FIXED 5e kl k OBTAIN s FROM T c0NPNTT-:I* =T* FB" ---F so "-1 N s2 64 ALTERNATE BACK TRACE SELECTkA TERM H 0N STEP k+1 BY FROMIfTQFORM PRETVIOUSLY k 'QB'L 'LE J T SELECTED N0 HDMiNG k-1 SEQUENCE k+1 k ELTNFIQTSTJEI EXISTS f CONTAIN ANY YES NO STATE VARIABLES as T5 N0 70 YES L Y8/KTCOMPUTE w TW'...T1 DETERMNED