Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUST935003 I4
Publication typeGrant
Publication dateJun 3, 1975
Filing dateFeb 19, 1974
Priority dateFeb 19, 1974
Publication numberUS T935003 I4, US T935003I4, US-I4-T935003, UST935003 I4, UST935003I4
InventorsPacific Lighting Service Co.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Process for selecting circuits with optimum
US T935003 I4
Images(7)
Previous page
Next page
Description  (OCR text may contain errors)

FNsW PUBLTCATN UNITED sra'rns P TENT AND TRADEMARK OFFIC Published at the request of the applicant 0r-owner in accordance with the Notice of Dec. 16, 1969, 869 O.G 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents a sheet.

Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent and Trademark Oiiice makes no assertion as to the novelty of the disclosed subject matter.

PUBLISHED JUNE 3, 1975 ITEAO III USER SPFCIFICATION I-LOOIC CIiT BLOCK OITAPIl ZIIAXIIAUM CIlT DELAYS ECHIP CELL SIZE LIMITATIONS T-AVAILABLE OAT TIL'ICTIOIIS,

SIZES AIID CHARACTERISTICS 5-KI I T TO TOITM AVAILABLE OKT TIJIIDTIOII-SIZE (AFSI ARITAY TITOM USE SPECS.

FUAII NET LOAD on) man NET NUMBER (mun) uuvamornn m (mu) RATS SPECIFIED cu DELAY (SPOT sunnuc CIRCUIT ruucnoi- IIIITIALIZE INDEX t-i CALCULATE FOR EACH OAT (Ci) TIIE METAL AIIO IIITFLISFON INTERCOIII|'ECTIO|\ LEIlOTIi REQUIRED FOR THE OUTPUT NET RESET i I 15 CALCULATE FOR CKT (Oi) ,20 TOTAL OUTPUT LOAD (ZT) DELAY Oi) This is an automatic process for selecting circuits to be placed on a large scale integrated (LSI) circuit chip. The process selects a minimum circuit size which satisfies the power and timing requirements of the individual circuits on the chip. Minimization is achieved by selecting from user specification lists, that circuit which satisfies the requircmeuts. The large scale integrated circuit chip resulting from the design process contains field effect transistor circuits of difierent physical size. By matching the required power and timing with a satisfactory circuit, the LS1 chip is more highly compacted in the number of circuits and performance available Within the chip structure.

ISSUE OF AUGUST 19, 1975 UNDER PAT., T.M. & SEPARATES NOTICES ERRATA In the notices of Defensive Publications appearing on pages 9-12 in the Oflicial Gazette of June 3, 1975, the names of the assignees were omitted and should be added as indicated below T935,001. E. L du Pont de Nemours and Company, Wilmington, Del. T935,002. Pacific Lighting Service 00., Los Angeles, Calif.

T935903. International Business Machines Corporation, Armonk, NY. T935004. International Business Machines Corporation, Armonk, N.Y. T935,005. International Business Machines Corporation, Armonk, NY. T935,006. E. I. du Pont de Nemours and Company, Wilmington, Del.

In the notices of Defensiw'e Publications appearing on pages 7 and 8 in the Official Gazette of July 1, 1975, the following names of assignees were omitted and should be added:

T936,001. E. I. du Pont de Nemours and Company, Wilmington, Del. T936,002. E. I. du Pont de Nemours and Company, Wilmington, Del. T936,005. DuPont of Canada Limited, Quebec, Canada Rune 3, i3

yg LLE PROCESS FOR SELECTING CIRCUITS WITH OPTIMUM POWER AND AREA REQUIREMENTS Original Filed Dec. 30, 1971.

'7 Sheets-Sheet 1 FIG.

READ IN USER SPECIFICATION I-LOCIC CKT BLOCK GRAPH Z'MAXIMUM CKT DELAYS 3-CHIP CELL SIZE LIMITATIONS FIG.

4-AVAILABLE CIIT FUNCTIONS,

SIZES AND CHARACTERISTICS 5-KM II IID FORM AVAILABLE CKT FUNCTION-SIZE (AFSI ARRAY FROM USE SPECS.

FIG.IA

FORM NET LOAD (NL) INPUT NET NUMBER (INNETI NUMBER OF FAN IN (NFAN) SPECIFIED CIIT DELAY (SPD) STARTING CIRCUIT FUNCTION- SIZEICFS) ARRAYS INITIALIZE INDEX i=1 CALCULATE FOR EACH CIIT (Ci) THE METAL THE OUTPUT NET DIFFUSION INTERCONNECTION LENCTH REQUIRED FOR AND RESET L =1 [/15 CALCULATE FOR CKT (CI), TOTAL OUTPUT LOAD (ZT) DELAY I DI) June 3, 1975 T. P. LINVILLE ETAL PROCESS FOR SELECTING CIRCUITS WITH OPTIMUM POWER AND AREA RE UIR E T orlglnal Flled Dec. 50, 1971 Q EM N s 7 Sheets-Sheet z N DOES SPECIFIED CKT IN NS SATISFY 50 CALCULATED REQUIREMENTS NO YES OPTIMIZE CIRCUIT SIZE FOR CALCULATED LOAD WAS CIRCUIT SIZE INCREASED YES NO 4 HAVE ALL cmcuns (Ci) BEEN PROCESSED NO YES F|G.1B

IS TOTAL CHIP POWER DISSIPATION FOR ALL 0E EXCEEDED? No YES HAS CFS BEEN UPDATED DURING RECENT PASS YES NO OUTPUT CFS T0 USER June 3, 1975 p LTNVlLLE ETAL T935,003

PROCESS FOR SELECTING CIRCUITS WITH OPTIMUM POWER AND AREA REQUIREMENTS Original Filed Dec. 50, 1971 7 sheets sheet 5 OBTAIN USER ORT PLACEMENT SPECIFICATION. FIG. /10 2A FIG CALCULATE EACH CIRCUIT COORDINATE POSITION.

FIG. 2C OONPOTE DISTANCE TOVERTICAL AND HORIZONTAL COORDINATES',

CONNECT CIRCUITS IN EACH NET,

VERTICAL METALIZATION, (VM) HORIZONTAL-DIFFUSION, (HD) RESET 1 L FIG. 2A

I DETERMINE AFS NUMBER FOR CKTICI) AND LOAD PARAMETERS FORICI) ASA FUNCTION OF FANIN, FROM AFS.

CALCULATE CIRCUIT LOAD CALCULATE CIRCUIT INTERCONNECTION. LOADIZI) DUE TO METAL AND DIFFUSION. INTERCONNECTION LENCTHSIVM AND HD) ON CKT OUTPUT.

ZI=VM+KM HD+KD.

DETERMINE AFS NUMBER OF DRIVEN CKTS AS SPECIFIED IN NL.

OBTAIN LOAD PARAMETER OF DRIVEN CIRCUITS CONNECTED TO CIVEN CIFRSCUIT OUTPUT FROM June 3, 1975 p N L EI'AL T935,003

PROCESS FOR SELECTING CIRCUITS WITH OPTIMUM POWER AND AREA BE UIREMENTS Ongmal Flled Dec. 30, 1971 Q 7 Sheets-Sheet 4 CALCULATE DRIVEN CIRCUIT LOAD (ZD) COMPUTE TOTAL OUTPUT LOAD 2o ZT=ZC+ZI+ZD LOOK UP CIRCUIT EQUATION FORICI) FROM AFS AND CALCULATE CIRCUH DELAY USINCZT,

D=m ZT+K OBTAIN SPECIFIED CKT DELAY (SPD'L) FOR CL FROM SPD.

DFSPDL? 0 YES IS FASTER CIRCUIT AVAILABLE YES I No LOOK UP, USING AFS, CRT SIZE AS A FUNCTION OF FANIN FOR FASTER CKT.

DOES FASTER CKT EXCEED CELL SIZE LIMIT NO YES HAVE ALL cL's BEEN PROCESSED CALCULATE 0L FOR ALL June 3, 1975 R UNVILLE I AL T935,003

PROCESS FOR SELECTING CIRCUITS WITH OPTIMUM POWER AND AREA REQUIREMENTS Original Filed Dec. 30, .1971 7 Sheets-Sheet 5 I T I LOOK UP CIRCUITS CONNECTED TO ,40 INPUTS OF CIRCUIT CL IN NET.

COMPUTE DIFFERENCE A BETWEEN CALCULATED DELAY AND SPECIFIED CIRCUIT DELAY FOR ALL INPUT CIRCUITS T0 CI, USING D AND SPD.

IDENTIFY CRITICAL INPUT CIRCUIT BY MAXIMUM A.

COMPUTE DT= Di Dcrit FIG.2C

MAKE HYPOTHETICAL INCREMENT OF ALL CKT SIZES DRIVEN BY CRITICAL INPUT CKT WITH- OUT EXCEEDING SPECIFICATION.

COMPUTE DT'= DL'+ DcriL' FOR HYPOTH" ETI-CAL INCREMENT.

YES

UPDATE CFS T0 CONTAIN INCREASED CKT SIZE FOR CL CONTINUE PROCESS, BRANCH TO BLOCK 50.

June 3, 1975 p LINVILLE ETAL T935,003

PROCESS FOR SELECTING CIRCUITS WITH OPTIMUM POWER AND AREA REQUIREMENTS orlglnal Filed Dec. 30, 1971 7 Sheets-Sheet 6 CIRCUIT BLOCK GRAPH FIG. 3

June 3, 1975 T. P. LiNVlLLE EI'AL T935,003 PROCESS FOR SELECTING CIRCUITS WITH OPTIMUM 7 Sheets-Sheet 7 POWER AND AREA REQUIREMENTS Original Filed Dec. 30, 1971 FIG. 4

MAX. CELL SIZE SIZE PARAMETER PWR.

LOAD

ADDRESS A1 A2 A3 AFS ARRAY FIG.5

N N- m M T N 'v 5 050 05 R 1.... R mq 000 0 0 LA 00 22444466 L P F. u 0 X s NAI S F. 0 CA A AAAAAAAA A Y Y D A 5 0555 0 21.11. D 11. M B U M DI N A II F 1170515221 N 0 m 0 N N 4 TIVI ION 1. 5 EA 1 1 5 R 014.... 6 NR EL 2 IA N 1 Cw l K 0 6 N 56 E 1 00 W 45 R R 5 R D A L N NET NO.

CKT. N0.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5010493 *Apr 26, 1989Apr 23, 1991Hitachi, Ltd.Load distribution method
US5012427 *Jan 30, 1989Apr 30, 1991Kabushiki Kaisha ToshibaSemiconductor integrated circuit and method of manufacturing the same
US5031111 *Aug 8, 1988Jul 9, 1991Trw Inc.Automated circuit design method
US5168455 *Mar 28, 1991Dec 1, 1992Digital Equipment CorporationProcedure for incorporating timing parameters in the synthesis of logic circuit designs
US5175696 *May 21, 1991Dec 29, 1992Digital Equipment CorporationRule structure in a procedure for synthesis of logic circuits
US5212650 *Aug 3, 1989May 18, 1993Digital Equipment CorporationProcedure and data structure for synthesis and transformation of logic circuit designs
US5222029 *Dec 8, 1992Jun 22, 1993Digital Equipment CorporationBitwise implementation mechanism for a circuit design synthesis procedure
US5267175 *Apr 5, 1993Nov 30, 1993Digital Equipment CorporationData base access mechanism for rules utilized by a synthesis procedure for logic circuit design
US5452226 *May 21, 1991Sep 19, 1995Digital Equipment CorporationRule structure for insertion of new elements in a circuit design synthesis procedure
US5504694 *Oct 28, 1993Apr 2, 1996Motorola, Inc.Method of cell characterization for energy dissipation
US5521834 *Nov 30, 1993May 28, 1996At&T Global Information Solutions CompanyMethod and apparatus for calculating dynamic power dissipation in CMOS integrated circuits
US5715172 *Apr 26, 1996Feb 3, 1998Quickturn Design Systems, Inc.Method for automatic clock qualifier selection in reprogrammable hardware emulation systems
Classifications
U.S. Classification716/113, 716/134, 716/122, 716/135
International ClassificationG06F17/50
Cooperative ClassificationG06F17/5045
European ClassificationG06F17/50D