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US T938005 I4
Description (OCR text may contain errors)
DEFENSIVE PULICATION UNITED STATES PATENT AND TRADEMARK OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 O.G. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered seriesand are arranged chronologically. Ihe heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents a sheet.
Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent and Trademark Otfice makes no assertion as to the novelty of the disclosed subject matter.
PUBLISHED SEPTEMBER 2, 1975 Int. Cl. G06f 15/20 US. Cl. 444-1 6 Sheets Drawing. 11 Pages Specification CHIP DESIIGNER LOGIC DESCRIPTiON 'Q HSS Q PER RULES I [)RlENTAllON FREEFORM DESCRIPTION -RULES DESIGN DESCRIPTION mp R E ORIENTATION TOTAL CHIP DESCRIPTION 20 GRAPHICAL LANGUAGE DESCRIPTION Stored in a design automation (DA) system is a library of predesigned graphical descriptions that describe circuits designed by the free form technique. A chip designer would layout a chip including both free form and rules driven portions. An input is fed to the DA system which specifies the rules driven design in the established manner and specifies the free form design by defining the library description thereof, and the relative placement of the design on the chip. The system in response to such input generates a graphical description of the rules driven design Without doing any automatic checking of the internals of the free form design. The generated description or topology is then merged with the free form description or topology from the library to form a complete chip description from which is derived data for making the masks.
Sept. 2, 1975 w. F. COLTON ETAL T938,005
PROCESS FOR MAKING LSI CHIPS HAVING BOTH RULES DRIVEN AND FREE FORM DESIGN Original Filed Sept. 2'7, 1973 6 Sheets-Sheet 1 Fl 6 1 PRIOR ART & INVENTION I GRAPHICAL CHIP GRIP LANGUAGE ARTWORK MASKS LANGUAGE r DESIGNER DESIGN DESCRIPHON PRocEsso GENER TOR \IO NH K42 I5 CHIP DESIGNER H G 2 LOG) DESCRlPTlON FREEFORM IDENTIFICATION PER RU LOCATION 8A ORIENTATION FADS INAGER BOOK LIBRARY 48 FREEFORM DESCRIPTION I0 RULES DESIGN DESCRIPTION my N U N RI N X N A DESCRIPTION MERGE 22 I ORIENTATION TOTAL CH|P DESCRIPTION 20 GRAPHICAL LANGUAGE DESCRIPTION Sept. 2, 1975 w. F. COLTON ETAL T938,005
MAKING PROCESS FOR LSI CHIPS HAVING BOTH RULES DRI AND FREE FORM DESIGN Original Filed Sept. 2'7, 197 6 Sheets-Sheet 2 UDUDUEIUUUUUU DEBUBUUEDUU i GL GR I UU@EJBU@UE@UU w. F. COLTON ETAL T933,005 PROCESS FOR MAKING LSI CHIPS HAVING BOTH RULES DRIVEN AND FREE FORM DESIGN Original Filed Sept. 2'7, 1973 6 Sheets-Sheet 3 Sept. 2, 1975 Fl G. 4
IMAGE IMAGE P/N & E/C TYPE DESCRIPTION L 44 58 i CHIP IMAGE IMAGE PAD SPEC GENERATION 46 50 CIRCUIT DATA FREEFORM N0 PLACEMENT DATA MLL 42 INITIAL DEVICE GATE SIZING & DATA SIZING CHECKING CIRCUIT DATA I 56 WITH PLACEMENT k 52 54 wIIIE CIRCUIT LIST PLACEMENT RULES J CIRCUITS Ie DIGIT y WIRE K58 ROUTING \60 40 I WIRING RULES DESCRIPTION Sept. 2, 1975 w. F, co ToN ETAL T938,005
PROCESS FOR MAKING LSI CHIPS HAVING BOTH RULES DRIVEN AND FREE FORM DESIGN Original Filed Sept. 27, 1.973 6 Sheets-Sheet 4 FIG. 5d
1' g E f E g E 2 Z Q 5 0: L1 O PAD DATA 2 g 1 E i r: E Z :2
3 X N g z 5 1011 a b c o 1021 d e f o 1051 s n i o DIGIT DATA FIG. 51 54 IMAGE TYPE Sept. 2, 1975 w. F. COLTON ETAL T938,005 PROCESS FOR MAKING LSI CHIPS HAVING BOTH RULES DRIVEN AND FREE FORM DESIGN Or1g1nal Filed Sept. 27, 1973 ZEZQZSEMW ZQZOZE Ems; zoom CIRCUIT DATA $2232 zoom FREEFORM DATA D H P:
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MASTER LOGIC LIST MLL Sept. 2, 1975 w. F. COLTON ETAL T938,005
PROCESS FOR MAKING LSI CHIPS HAVING BOTH RULES DRIVEN AND FREE FORM DESIGN Original Filed Sept. 2'7, 197?: 6 Sheets-Sheet 6 FIG. 6
PREDESIGN PREDESIGN RULES BOOKS FREEFORM BOOKS STORE BOOKS OF TOPOLOGICAL DATAS ELECTRICAL CHARACTERISTICS OF CIRCUITS INCLUDING GRAPHICAL DESCRIPTION OF EREEFORM DESIGNS CENERATE GRAPHICAL DESCRIPTION OF IMAGE, RULES CIRCUITS & WIRING I PRODUCE MASKS PRODUCE LS1 DEVICE