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Publication numberUST940020 I4
Publication typeGrant
Publication dateNov 4, 1975
Filing dateApr 17, 1974
Priority dateApr 17, 1974
Publication numberUS T940020 I4, US T940020I4, US-I4-T940020, UST940020 I4, UST940020I4
InventorsG. E. Brechling
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Automatic circuit generation process and apparatus
US T940020 I4
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Description  (OCR text may contain errors)

Ulhfl l or UNIETED STATES li- T AND TRADEEKARL @FFIQE Published at the request of the applicanc or owner in accordance with the Notice of Dec. 16, 1869, 869 0.6 687. The abstracts of Defensive Publication applications are iclenilfiecl by all inctly numbered series and are arranged chronolo; cally. The heacllng of each abstract indicates the number of I lclucling claims anrl sheets of drawings coneeined in the application as originally filed. 'lh files of these a to the public for inspection and reproduckion may be purchased for 30 cents a sheet.

Defensive Publication applications have not been examiner to the merits of alleged invention. The Parent and Trademark Oifice makes no assertion as to the novelty of the disclosed subject matter.

PUBLISH D NGVEMBER 4-, 1975 9&0 ll

Film n5 11m" STORAGE J5 msmonm. was 3 i DNA I lleuwll Apparatus and method for automatically generating a topology for a logic circuit to he embodied in a semiconductor wafer. Fixed data, designer origioatcd data an control data are generated as an input to a computer. The fixed data provides electrical, and topological qualities of each logical elcmcnt in the logic circuit to be omborlicd in the semiconductor Wafer. The designer originaled data provides location in an ordered grid layout. "he control data c cscrilacs (l) combinations of logical elements in the logic circuit by type of combination, start and end in the grid array descriptive of tho semiconductor wafer and (2) electrically common combinations. A program employs Lhc fixed, designer originated and control data to generaie coordinate data for each logical element in the grid array as an input to a graphical processor which translates the coordinates into a topological pattern dcscrictivc of the logic circuit to be embodied in the semiconductor Wafer.

PROCESS AND APPARATUS Original Filed April 17, 1974 T I G. E. BRECHLING et a1. AUTOMATIC CIRCUIT GENERATION Sheet 1 of 10 FIGJ SEE FIG.I2 F

STORAGE MEANS GENERAL PURPOSE COMPUTER RAIIIIAI DATA FOR I 92 Mm FOPOLTIGTCTTL I DATA FOR LL AEJE E I FIG.3

INSTRUCTIONS I J TABLE 111 RAILS WLR SEGMENTTSI 11 TABLE 05v. LOCATION x=1 CHANTC) -0 FIG 5 NOV. 4, 1975 G. E. BRECHLING et a1. T940,020

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April 17, 1974 Sheet 2 of 10 ABCDEFGHLJKLM I3 CHANNELS 2 3 4 5 6 STARTING ENDING No. OF FET'S GROUP START GROUP END RAIL No. RAIL No. 4 IN GROUP NET No. NET No.

I I I 2 3 I 2 0= SERIES I= PARALLEL 2=ALT. SERIES 3=DIFFUSION SUB-GROUP INPUTS |N3TR TALE 1 A,B,C i=1' 1 1 2 3 1 2 3 EF 3 I 5 e 2 3 4 4 H 4 0 3 e 2 2 4 5 1M 5 2 3 4 3 2 s 6 L 6 0 5 e 1 5 4 IJA FIG.7C

NOV. 4, 1975 G. E. BRECHLING et a1. T940,02O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April 17, 1974 Sheet 3 0f 10 F|G.6A

RAIL 6 I05 RAIL 5 START Y COORD. RAIL WIDTH 79 (GRID UNITS) (GRIDUNITS) RAIL 4 I 7 8 5 2 29 I2 3 3 41 I2 2 RAIL 3 41 4 62 I2 RAIL 2 5 79 I2 29 6 I05 8 I5 7 RAIL I H658 x (GRID UNITS) x x XGX d a y IDE PENING METALLIZATION F ox 0 A '-DIFFUSION I I i CHANNEL I I LENGTH I VADIFFUSION CHANNEL WIDTH FIG.6C

X METAL DIFFUSION OVERLAP (4 GRID UNITS) X D|FFUSION /OXIDE OVERLAP (4 GRID UNITS) X 0XIDE /DIFFUSION OVERLAP I I GRID UNIT) X y DIFFUSION METAL DVERLAP I O GRID UNIT) I X DIFFUSION WIDTH (8 GRID UNITS) NOV. 4, 1975 G. E. BRECHLING et a1. T940,02O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Origin Filed Apn'l 17, 1974 Sheet 5 Of 10 I00 IIs ENTER cIRcIIIT GEN. I'

INSTRUCTIONS YSTART IN TABLE II ACCESS wLRs FROM I02 I x= Xy CTR 118 DATA BASE STORED ACCESS TABLET FOR IN TABLET BEvIcE PARAMETERS ACCESS DEVICE FORM sTART SEGMENT 120 COORDINATES LOCATIONS FROM DATA CHECK INTERSECTION sToRE IN TABLET ORDER DEVICES BY 106 ASCENDING I; cooRBINATE SEPARATE BY Y COORDINATE ASSIGN sTART SEGMENT COORDINATES To NET TABLE 108 T I 0 f T ACCIiiSG: ITiArB1LE II 11O INTERPRET INSTRUGTIONI YZYH FORM END SEGMENT RAIL YES 152 ASSIGN END SEGMENT T0 NET TABLE NOV. 4, 1975 G. E. BRECHLING et a1. T940,020

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April 17, 1974 Sheet 6 of 10 YES ; 219 A TNTT. T (Y,X) FORM COORD. Y=START RAIL-1 VERTICAL DIFFUSION ExTENsToN 204 Y=Y+1 1 x cTR =x CTR+1 TABLE FOR DEVICE PARAMETERS T 206 FORM sTART ASSIGN LAST SEGMENT GENERATED T0 NET TABLE ASSIGN SOURCE sTART SEGMENT To NET TABLE 214 Y=Y+1 J F|G.|2B FORM END SEGMENT CHECK 1 NTERSECTION LAsT DEVICE TN NOV. 4, 1975 G. E. BRECHLING et a1. T940,02O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April 17, 1974 Sheet 7 of 10 320 FORM DIFF. COORD.

BETWEEN RAILS CHECK 1 AND 1+1 LOCATED INTERSECTTON VERTICALLY ABovE LAST DEVICE SUBGROUP ,304 306 Y=STARTRAIL+1 Y STARTRAlL-1 k=0 k=1 =0 1 =0 k= 308 y FW I FORM 1 I x CTR =X CTR+1 1 TABLE I INTERSECTION ASSIGN START SEGMENT T0 NET TABLE NOV. 4, 1975 G. E. BRECHLING et a1. T94D,O2O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April 17, 1974 Sheet 8 of 10 ZZ mm II II II COO N =N +I ADDRESS END I 404 SEGMENTS IN X=X+I NEW NET TABLE ACCESS I (N ,N3,X)

FOR END SEGMENT FORM SINGLE QHAPE CONNECT T0 END SEGMENT x IF ANY I X=X+I ACCESS J I (NE ,N3 ,x)

ADDRESS START I 409 SEGMENTS IN FORM 1 SAME NET TABLE SINGLE SHAPE X=X+I 414 ACCESS I IN ,N ,XI FOR START 4T8 STORE STORE STORE X START SHAPE X START SHAPE X START SHAPE IN "UNDER SPAN" IN "OVER SPAN" IN IN SPAN TABLE TABLE TABLE NOV. 4, 1975 G. E. BRECHLING et a1. T940,02O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April 17, 1974 Sheet 9 of 10 FIG. I2E

SHAPES T N OVERSPAN ACCESS HTCHEST ACCESS LOWEST 456 x COORO. SHAPE xCOORO. SHAPE CONNECT TO CONNECT TO FIRST END SHAPE LAST END SHAPE CHECK CHECK ACCESS NEXT ACCESS NEXT LOWEST HTCHEST START SHAPE START SHAPE A CONNECT CONNECT T0 HIGHER TO LOWER 440 START SHAPE, START SHAPE,

IF ANY IF ANY ACCESS IN SPAN SHAPES OBTAIN NON -NET 1 446 SEGMENT, COORDINATE STORE OUTPUT Nov. 4, 1975 G. E. BRECHLING et al. T940,020

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April 17, 1974 Sheet 10 of 10 m. fi

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5164908 *Feb 21, 1990Nov 17, 1992Nec CorporationCAD system for generating a schematic diagram of identifier sets connected by signal bundle names
US5278769 *Apr 12, 1991Jan 11, 1994Lsi Logic CorporationAutomatic logic model generation from schematic data base
US5463563 *Jun 30, 1993Oct 31, 1995Lsi Logic CorporationAutomatic logic model generation from schematic data base
US5526277 *Dec 13, 1994Jun 11, 1996Lsi Logic CorporationECAD system for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic descriptions thereof
US5526517 *May 15, 1992Jun 11, 1996Lsi Logic CorporationConcurrently operating design tools in an electronic computer aided design system
US5541849 *Jun 14, 1993Jul 30, 1996Lsi Logic CorporationMethod and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters
US5544066 *Jun 14, 1993Aug 6, 1996Lsi Logic CorporationMethod and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints
US5544067 *Jun 14, 1993Aug 6, 1996Lsi Logic CorporationIn an ecad system
US5553002 *Jun 14, 1993Sep 3, 1996Lsi Logic CorporationMethod and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface
US5555201 *Feb 10, 1994Sep 10, 1996Lsi Logic CorporationMethod and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
US5557531 *Jun 14, 1993Sep 17, 1996Lsi Logic CorporationMethod and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation
US5572436 *Jun 2, 1994Nov 5, 1996Lsi Logic CorporationMethod and system for creating and validating low level description of electronic design
US5572437 *May 20, 1994Nov 5, 1996Lsi Logic CorporationMethod and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
US5598344 *Feb 8, 1994Jan 28, 1997Lsi Logic CorporationMethod and system for creating, validating, and scaling structural description of electronic device
US5623418 *Jun 14, 1993Apr 22, 1997Lsi Logic CorporationSystem and method for creating and validating structural description of electronic system
US5801958 *Sep 10, 1996Sep 1, 1998Lsi Logic CorporationMethod and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
US5867399 *Apr 21, 1997Feb 2, 1999Lsi Logic CorporationSystem and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description
US5870308 *Nov 1, 1996Feb 9, 1999Lsi Logic CorporationMethod and system for creating and validating low-level description of electronic design
US5933356 *Nov 5, 1996Aug 3, 1999Lsi Logic CorporationMethod and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
US6137546 *Jul 20, 1998Oct 24, 2000Sony CorporationAuto program feature for a television receiver
US6216252Aug 22, 1996Apr 10, 2001Lsi Logic CorporationMethod and system for creating, validating, and scaling structural description of electronic device
US6324678Aug 22, 1996Nov 27, 2001Lsi Logic CorporationMethod and system for creating and validating low level description of electronic design
US6470482Aug 5, 1996Oct 22, 2002Lsi Logic CorporationMethod and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
Classifications
U.S. Classification716/119, 708/190
International ClassificationG06F17/50
Cooperative ClassificationG06F17/5068
European ClassificationG06F17/50L