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Publication numberUST943001 I4
Publication typeGrant
Publication dateFeb 3, 1976
Filing dateJun 13, 1974
Priority dateJun 13, 1974
Publication numberUS T943001 I4, US T943001I4, US-I4-T943001, UST943001 I4, UST943001I4
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet

US T943001 I4
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5229953 *Oct 12, 1990Jul 20, 1993Hitachi, Ltd.Method of and apparatus for assigning logic gates to a plurality of hardware components
US5416717 *Sep 4, 1990May 16, 1995Hitachi, Ltd.Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern
US5461577 *Mar 3, 1992Oct 24, 1995Texas Instruments IncorporatedComprehensive logic circuit layout system
US5617573 *May 23, 1994Apr 1, 1997Xilinx, Inc.State splitting for level reduction
US5629859 *Sep 12, 1994May 13, 1997Texas Instruments IncorporatedMethod for timing-directed circuit optimizations
US6345378 *Mar 23, 1995Feb 5, 2002Lsi Logic CorporationSynthesis shell generation and use in ASIC design
Classifications
U.S. Classification716/104, 708/190
International ClassificationG06F17/50
Cooperative ClassificationG06F17/5072
European ClassificationG06F17/50L1