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Publication numberUST955006 I4
Publication typeGrant
Application numberUS 05/695,716
Publication dateFeb 1, 1977
Filing dateJun 14, 1976
Priority dateDec 24, 1974
Publication number05695716, 695716, US T955006 I4, US T955006I4, US-I4-T955006, UST955006 I4, UST955006I4
InventorsJoseph Richard Cavaliere, David Barry Eardley
Original AssigneeInternational Business Machines Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Delay circuits using negative resistance CMOS circuits
US T955006 I4
Abstract
A negative resistance circuit constructed of complementary field effect transistors has several applications. A voltage change at an input to the negative resistance circuit alters the current at the input node in a direction inverse to that normally caused by such a voltage change. The circuit can be used to speed up the charging or the discharging of a circuit node capacitance.
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
EP0023127A1 *Jul 16, 1980Jan 28, 1981Fujitsu LimitedCMOS Schmitt-trigger circuit
EP0023655A2 *Jul 18, 1980Feb 11, 1981Kabushiki Kaisha ToshibaSemiconductor memory device
EP0023655A3 *Jul 18, 1980Nov 17, 1982Tokyo Shibaura Denki Kabushiki KaishaSemiconductor memory device
Classifications
U.S. Classification327/437, 327/399, 327/568
International ClassificationH03K3/3565, H03H1/00, H03K5/02, H03K17/0416, H03K19/017, H04B3/18, H03H11/52
Cooperative ClassificationH03H11/52, H03K19/017, H04B3/18, H03K19/01721, H03K5/023, H03K3/3565, H03K17/04163, H03H1/00, H01L2924/0002
European ClassificationH04B3/18, H03H11/52, H03K3/3565, H03K19/017B2, H03K17/0416B, H03H1/00, H03K19/017, H03K5/02B