WO1982000930A1 - Delay stage for a clock generator - Google Patents

Delay stage for a clock generator Download PDF

Info

Publication number
WO1982000930A1
WO1982000930A1 PCT/US1980/001163 US8001163W WO8200930A1 WO 1982000930 A1 WO1982000930 A1 WO 1982000930A1 US 8001163 W US8001163 W US 8001163W WO 8200930 A1 WO8200930 A1 WO 8200930A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
transistor
node
gate
source
Prior art date
Application number
PCT/US1980/001163
Other languages
French (fr)
Inventor
Corp Mostek
Original Assignee
Plachno R
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plachno R filed Critical Plachno R
Publication of WO1982000930A1 publication Critical patent/WO1982000930A1/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/02Shaping pulses by amplifying
    • H03K5/023Shaping pulses by amplifying using field effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/3565Bistables with hysteresis, e.g. Schmitt trigger
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015Layout of the delay element
    • H03K2005/00195Layout of the delay element using FET's

Definitions

  • This invention relates to MOS integrated circuits, and more particularly relates to a clock generator and delay stage utilizing a Schmitt trigger release with a push-pull buffered output.
  • a clock generator is provided for random logic applications using MOS technology to substantially eliminate the problems heretofore associated with clock generators and which offers the advantages of insensitivity to input slew rates and voltage patterns without the need for a precharge input clock.
  • a delay stage for a clock generator circuit for providing clocking signals and which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals.
  • a detector circuit is connected between the first and second power terminals and is connected to the input terminal for receiving the input signal. The detector circuit generates a detection signal upon detecting a predetermined level of the input signal.
  • a buffer circuit is connected between the first power terminal and the detection circuit for receiving the detection signal and for generating the output signal at the output terminal.
  • a clock generator circuit for producing clocking signals and which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals.
  • First, second and third transistors each having drain, source and gate terminals are connected in series between the first power terminal and the second power terminal.
  • a first node is formed between the first and second transistors, and a second node is formed between the second and third transistors.
  • a fourth transistor having drain, source and gate terminals is connected between the first power terminal and the second node. The gate terminal of the fourth transistor is connected to the first node.
  • Fifth and sixth transistors are further provided, each having drain, source and gate terminals.
  • the fifth and sixth transistors are connected in series between the first power terminal and the second node.
  • the fifth and sixth transistors form a third node therebetween forming the output terminal.
  • the gate terminal of the fifth transistor is connected to the first node.
  • the gate terminal of the second transistor, the gate terminal of the third transistor and the gate terminal of the sixth transistor are connected to the input terminal.
  • a clock generator circuit for providing clocking signals and which receives an input signal at an input terminal and which is powered through first and second power terminals is provided.
  • a first transistor having drain, source and gate terminals is. provided wherein the drain terminal is connected to the first power terminal.
  • the circuit includes a second transistor having drain, source and gate terminals wherein the drain terminal is connected to the source terminal and gate terminal of the first transistor thereby forming a first node.
  • the gate terminal of the second transistor is connected to the input terminal.
  • a third transistor having drain, source and gate terminals is provided in the clock generator.
  • the drain terminal of the third transistor is connected to the source terminal of the second transistor thereby forming a second node.
  • the gate terminal of the third transistor is connected to the input terminal and the source terminal thereof is connected to the second power terminal.
  • a fourth transistor is provided having drain, source and gate
  • the drain terminal of the fourth transistor is connected to the first power terminal, the gate terminal thereof is connected to the first node, and the source terminal thereof is connected to the second node.
  • a fifth transistor is further provided having drain, source and gate terminals. The drain terminal of the fifth transistor is connected to the first power terminal and the gate terminal thereof is connected to the first node.
  • a sixth transistor having drain, source and gate terminals is provided. The drain terminal of the sixth transistor is connected to the source terminal of the fifth transistor, the gate terminal thereof is connected to the input terminal and the source terminal of the sixth transistor is connected to the second node.
  • FIGURE 1 is a schematic circuit diagram of the clock generator of the present invention
  • FIGURE 2 illustrates signal waveforms illustrating the operation of the present clock generator
  • FIGURE 3 illustrates signal waveforms illustrating the operation of the present clock generator.
  • clock generator 10 is supplied with power through a power supply terminal 12 and a power supply terminal 14.
  • Power supply terminal 12 is designated as Vv_»C and is typically, for example,
  • Power terminal 14 is designated as V and is typically, for example, 0.0 volts.
  • Input signals are applied to clock generator 10 via an input terminal 16 to a node 18.
  • transistors 20, 22 and 24 Interconnected in series between power terminal 12 and power terminal 14 are transistors 20, 22 and 24.
  • the drain terminal of transistor 20 is connected to power terminal 12.
  • the gate and source terminals of transistor 20 are interconnected to form a node 26.
  • Node 26 is interconnected to the drain of transistor 22.
  • the gate of transistor 22 is interconnected to node 18 to receive the input to clock generator 10.
  • the source of transistor 22 and drain of transistor 24 are interconnected to form a node 28.
  • the gate of transistor 24 is interconnected to node 18.
  • the source of transistor 24 is interconnected to power terminal 14.
  • Node 26 is interconnected to the gate of a transistor 40.
  • the drain ⁇ f transistor 40 is interconnected to pov/er terminal 12, and the source of transistor 40 is interconnected to node 28.
  • Transistors 20, 22, 24 and 40 comprise a Schmitt trigger generally identified by the numeral 30 which functions as a level detector to detect changes in the level of the input to clock generator 10.
  • Transistor 20 may comprise, for example, as shown, a depletion type MOSFET wherein V TM is minus three volts or alternatively, a saturated enhancement type MOSFET in which case the gate thereof is connected to pov/er terminal 12.
  • Transistors 22, 24 and 40 may comprise, for example, an enhancement MOSFET wherein TM is one volt.
  • Connected in series between power terminal 12 and node 28 are transistors 42 and 44. The drain of transistor 42 is connected to power terminal 12 and the gate thereof is connected to node 26.
  • the source terminal of transistor 42 is interconnected to the drain terminal of transistor 44 thereby forming a node 46.
  • the gate terminal of transistor 44 is interconnected to node 18 to receive the input signal to clock generator 10.
  • the source terminal of transistor 44 is - interconnected to node 28.
  • Transistors 42 and 44 comprise a push-pull buffer circuit generally, identified by the numeral 50, for receiving the output of Schmitt trigger 30 for application to the remaining portion of clock generator 10 to be subsequently described and for buffering Schmitt trigger 30 from the capacitance present in clock generator 10.
  • Transistor 44 may comprise, for example, enhancement type MOSFETs.
  • Transistor 42 may comprise, for example, a natural type MOSFET of low enhancement where " ⁇ equals zero volts. '
  • Node 18 is interconnected to the drain of a transistor 54.
  • the gate of transistor 54 is inter ⁇ connected to the drain of a transistor 56 forming a node 58 therebetween.
  • the source of transistor 56 is connected to node 46, and the gate of transistor 56 is connected to power terminal 12.
  • Clock generator 10 further includes transistors 60 and 62 interconnected in series between power terminal 12 and power terminal 14.
  • the drain of transistor 60 is connected to power terminal 12.
  • the gate of transistor 60 is connected to the source of transistor 54, forming a node 64.
  • the source of transistor 60 is connected to the drain of transistor 62 thereby forming a node 66.
  • the gate of transistor 62 is connected to node 46, and the source of transistor 62 is connected to power terminal 14.
  • a MOS capacitor 68 Interconnected between nodes 64 and 66 is a MOS capacitor 68 wherein the gate is connected to node 64 and the source
  • Transistors 60 and 62 comprise enhancement type MOSFETs.
  • MOS capacitor 68 may be utilized, for example, with a depletion implant wherein V ⁇ equals minus three volts.
  • transistors 70 and 72 Interconnected in series between power terminal 12 and power terminal 14 are transistors 70 and 72 forming a node 74 therebetween.
  • the gate of transistor 70 is connected to power terminal 12, and the drain of transistor 70 is connected to node 64.
  • the source of transistor 72 is connected to power terminal 14.
  • the gate of transistor 72 is connected to receive via a node 75 a reset signal from a reset terminal 76.
  • transistors 78 and 80- Also interconnected between power terminal 12 and pov/er terminal 14 are transistors 78 and 80- forming a node 82 therebetween.
  • the gate of transistors 78 is connected to node 64.
  • the drain of transistor 78 is connected to power terminal 12.
  • the gate of transistor 80 is connected to node 46.
  • the source terminal of transistor 80 is connected to power terminal 14.
  • the output signal of clock generator 10 is produced at node 82 for application to an output terminal 86.
  • Transistors 70, 72, 78 and 80 may comprise, for example, enhancement type MOSFETs.
  • the reset signal from terminal 76 is also applied via node 75 to the gate of a transistor 88.
  • the drain of transistor 88 is connected to node 82.
  • the source of transistor 88 is connected to power terminal 14.
  • Transistor 88 may comprise, for example, an enhancement type MOSFET.
  • Transistors 70, 72 and 88 are not a necessary part of clock generator 10, but are utilized if it is desired that clock generator 10 be reset at a time different than the reset of the input to clock generator 10 as will subsequently be described.
  • the operation of clock generator 10 may best be understood by referring simultaneously to FIGURES 1 and 2.
  • FIGURE 2 illustrates the voltage levels of the input signal, node 18, (FIGURE 2a), the output signal, node 82, 5 (FIGURE 2d), the voltage level of node 64 (FIGURE 2b) and the voltage level of node 46 (FIGURE 2c).
  • Clock generator 10 provides a delay and buffer, such that as the input to clock generator 10 goes high, after a predetermined amount of delay, the output of clock generator 10 at node 82 will 10 go high.
  • node 64 is precharged through transistor 54.
  • Schmitt trigger 30 guarantees that a high level has been achieved on node 64 (reference numeral 90, FIGURE 2b) and after a delay forces node 46 low
  • node 64 is bootstrapped by the action of capacitor 68 to a level above the input voltage (reference numeral 93, FIGURE 2b), for example, if an 80 percent bootstrap was utilized,
  • node 64 would increase to nine volts. This voltage at node 64 allows transistor 78 to turn on hard to generate the output at node 82 of five volts.
  • trigger 30 is such that when the input to clock generator 10 via input terminal 16 is zero, transistors 22 and 24 • are cutoff such that transistor 20 pulls node 26 to the voltage level of V cc and transistor 40 pulls node 28 to a voltage level of V cc less one threshold.
  • transistor 24 turns on while transistor 22 still remains cutoff.
  • a resistor divider network is formed between transistor 40 and 24 to set the voltage at node 28. Since the gate of transistor 40 is at a voltage 5 level of V and the gate of transistor 24 is at the input voltage which is now rising, transistors 40 and 24 set the source voltage of transistor 22 such that Schmitt trigger 30 will not switch until the input voltage rises above the voltage level of node 28 plus one threshold.
  • the switching level is set for Schmitt trigger 30 such that when the rising edge of the input signal to clock generator 10 goes from zero to a high, transistor 22 will switch with the generation of one volt provided by the resistor divider network of transistors 40 and 24.
  • node 26 is pulled close to zero volts which then causes cutoff of transistor 40, such that node 28 will also be at zero volts.
  • Schmitt trigger 30 will switch at a voltage level of less than a threshold to cutoff transistors 22 and 24 allowing node 26 to go to the level of V and node 28 to follow.
  • the push-pull buffer circuit 50 comprising transistors 42 and 44 does not influence the operation of Schmitt trigger 30 since transistor 44 is always cutoff when transistor 22 is cutoff.
  • Transistor 44 is not turned on until transistor 22 is turned on since their respective gate terminals and source terminals are respectively interconnected. Buffer 50, therefore, does not change the trigger point of Schmitt trigger 30.
  • Buffer 50 allows transistor 20 to be fabricated very small such that a minimal value of current is dissipated when clock generator 10 is active since transistor 20 must only drive transistors 40 and 42.
  • Clock generator 10 is reset naturally by node 64 discharging through transistor 54 and node 46 going high as illustrated in FIGURES 2b and 2c.
  • the output at node 82 cannot go low until node 46 goes high.
  • node 58 goes high such that node 64 can go low. Since node 58 must go high before node 64 goes low, there is a delay between node 46 going high and node 64 going low.
  • Clock generator 10 can also be reset without using the natural discharge of node 64 through transistor 54.
  • the waveforms illustrating the operation of clock generator 10 for resetting the output voltage at node 82 for application to output terminal 86 is shown in FIGURE 3.
  • FIGURE 3b illustrates the reset voltage (reference numeral 94) applied at node 75 while the input voltage shown in FIGURE 3a is high.
  • the reset signal is applied to transistors 88 and 72 which causes nodes 64 and 82 to discharge as shown in FIGURES 3c and 3e.
  • the present clock generator 10 using Schmitt trigger 30 has improved response times while being independent of the input signal slew rate and input voltage patterns.
  • the clock generator of the present invention achieves a fast reset time either by natural discharge or utilizing a reset signal. Furthermore, no precharge clock signal is necessary for the operation of the present clock generator.
  • the use of buffer 50 prevents capacitive loading on Schmitt trigger 30 such that Schmitt trigger 30 can properly trigger, being pattern insensitive to the input voltage applied to clock generator 10. Without- the use of buffer 50, the capacitive loading due to the Miller capacitance of transistors 62 and 80 on Schmitt trigger 30 would not allow Schmitt trigger 30 to trigger in response to a rapidly changing pattern on the input to clock generator 10.

Abstract

A delay stage (30, 50) receives input signals at input terminal (16) and power from power terminals (12, 14). A detector circuit (30) is connected between power terminals (12, 14) and to the input terminal (16) for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal. A buffer circuit (50) is connected between the power terminals (12, 14) and to the detector circuit (30) for receiving the detection signal whicle not capacitively loading the detector circuit (30).

Description

DELAY STAGE FOR A CLOCK GENERATOR
TECHNICAL FIELD
This invention relates to MOS integrated circuits, and more particularly relates to a clock generator and delay stage utilizing a Schmitt trigger release with a push-pull buffered output.
• tΛ
Figure imgf000003_0001
BACKGROUND ART
In the design of digital logic circuits, large scale integration techniques have brought about the construction of large numbers of components being fabricated on a single chip of silicon. In such circuitry, utilizing metal-oxide-semiconductor MOS techniques, random access memory devices have been fabricated. Such memories as well as other semiconductor circuitry utilize numerous clock signals generated by clock generators. Clock generators for use with semiconductor data processing circuits are shown in U.S. Patent No. 3,898,479 issued to Proebsting on August 5, 1975 and entitled "Low Power, High Speed, High Output Voltage FET Delay-Inverter Stage" and U.S. Patent No. 4,061,933 issued to Schroeder et al. on December 6, 1977 and entitled "Clock Generator and Delay Stage". Such previous developed clock generators utilize a precharge input clock which necessitates an additional input to the clock generator circuit resulting in increased complexity as well as decreased performance and versatility.
With improved fabrication techniques, integrated circuits are- made smaller in geometry of size; however, as the size of such circuits becomes smaller, the associate capacitance between circuit components does not similarly decrease. Overlap capacitance or Miller capacitance of transistor devices in such integrated circuits creates a substantial problem in affecting the response time of clock generators. The response time, in turn, determines, in part, how pattern insensitive the clock generator becomes to a quickly changing input voltage. Previously developed clock generators suffer in that with reduced geometries, Miller capacitance prevents the operation of such clock generators at desirable response times to operate independent of input voltage patterns. Furthermore, clock generators must operate independent of the rise time or slew rate of the input voltage signal. A need has thus arisen for a clock generator for use in semiconductor circuitry which does not require a precharge input clock. Further, a need has arisen for a clock generator that operates independent of and is insensitive to input slew rates and input voltage patterns. Additionally, a need has arisen for a clock generator that has improved response times and fast reset times.
;. , DISCLOSURE OF THE INVENTION
In accordance with the present invention, a clock generator is provided for random logic applications using MOS technology to substantially eliminate the problems heretofore associated with clock generators and which offers the advantages of insensitivity to input slew rates and voltage patterns without the need for a precharge input clock.
In accordance with the present invention, a delay stage for a clock generator circuit for providing clocking signals and which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals is provided. A detector circuit is connected between the first and second power terminals and is connected to the input terminal for receiving the input signal. The detector circuit generates a detection signal upon detecting a predetermined level of the input signal. A buffer circuit is connected between the first power terminal and the detection circuit for receiving the detection signal and for generating the output signal at the output terminal.
In accordance with another aspect of the present invention, a clock generator circuit for producing clocking signals and which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals is provided. First, second and third transistors, each having drain, source and gate terminals are connected in series between the first power terminal and the second power terminal. A first node is formed between the first and second transistors, and a second node is formed between the second and third transistors. A fourth transistor having drain, source and gate terminals is connected between the first power terminal and the second node. The gate terminal of the fourth transistor is connected to the first node. Fifth and sixth transistors are further provided, each having drain, source and gate terminals. The fifth and sixth transistors are connected in series between the first power terminal and the second node. The fifth and sixth transistors form a third node therebetween forming the output terminal. The gate terminal of the fifth transistor is connected to the first node. The gate terminal of the second transistor, the gate terminal of the third transistor and the gate terminal of the sixth transistor are connected to the input terminal. In accordance with yet another aspect of the present invention, a clock generator circuit for providing clocking signals and which receives an input signal at an input terminal and which is powered through first and second power terminals is provided. A first transistor having drain, source and gate terminals is. provided wherein the drain terminal is connected to the first power terminal. The circuit includes a second transistor having drain, source and gate terminals wherein the drain terminal is connected to the source terminal and gate terminal of the first transistor thereby forming a first node. The gate terminal of the second transistor is connected to the input terminal. A third transistor having drain, source and gate terminals is provided in the clock generator. The drain terminal of the third transistor is connected to the source terminal of the second transistor thereby forming a second node. The gate terminal of the third transistor is connected to the input terminal and the source terminal thereof is connected to the second power terminal. A fourth transistor is provided having drain, source and gate
Figure imgf000007_0001
O.V. terminals. The drain terminal of the fourth transistor is connected to the first power terminal, the gate terminal thereof is connected to the first node, and the source terminal thereof is connected to the second node. A fifth transistor is further provided having drain, source and gate terminals. The drain terminal of the fifth transistor is connected to the first power terminal and the gate terminal thereof is connected to the first node. A sixth transistor having drain, source and gate terminals is provided. The drain terminal of the sixth transistor is connected to the source terminal of the fifth transistor, the gate terminal thereof is connected to the input terminal and the source terminal of the sixth transistor is connected to the second node.
BRIEF DESCRIPTION OF DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference will now be had to the following Detailed Description taken in conjunction with the accompanying Drawings in which: FIGURE 1 is a schematic circuit diagram of the clock generator of the present invention;
FIGURE 2 illustrates signal waveforms illustrating the operation of the present clock generator; and
FIGURE 3 illustrates signal waveforms illustrating the operation of the present clock generator.
i DETAILED DESCRIPTION
Referring to FIGURE 1, the clock generator of the present invention is illustrated and is generally identified by the numeral 10. Clock generator 10 is supplied with power through a power supply terminal 12 and a power supply terminal 14. Power supply terminal 12 is designated as Vv_»C and is typically, for example,
5.0 volts. Power terminal 14 is designated as V and is typically, for example, 0.0 volts. Input signals are applied to clock generator 10 via an input terminal 16 to a node 18.
Interconnected in series between power terminal 12 and power terminal 14 are transistors 20, 22 and 24. The drain terminal of transistor 20 is connected to power terminal 12. The gate and source terminals of transistor 20 are interconnected to form a node 26. Node 26 is interconnected to the drain of transistor 22. The gate of transistor 22 is interconnected to node 18 to receive the input to clock generator 10. The source of transistor 22 and drain of transistor 24 are interconnected to form a node 28. The gate of transistor 24 is interconnected to node 18. The source of transistor 24 is interconnected to power terminal 14. Node 26 is interconnected to the gate of a transistor 40. The drain σf transistor 40 is interconnected to pov/er terminal 12, and the source of transistor 40 is interconnected to node 28.
Transistors 20, 22, 24 and 40 comprise a Schmitt trigger generally identified by the numeral 30 which functions as a level detector to detect changes in the level of the input to clock generator 10. Transistor 20 may comprise, for example, as shown, a depletion type MOSFET wherein V is minus three volts or alternatively, a saturated enhancement type MOSFET in which case the gate thereof is connected to pov/er terminal 12. Transistors 22, 24 and 40 may comprise, for example, an enhancement MOSFET wherein is one volt. Connected in series between power terminal 12 and node 28 are transistors 42 and 44. The drain of transistor 42 is connected to power terminal 12 and the gate thereof is connected to node 26. The source terminal of transistor 42 is interconnected to the drain terminal of transistor 44 thereby forming a node 46. The gate terminal of transistor 44 is interconnected to node 18 to receive the input signal to clock generator 10. The source terminal of transistor 44 is - interconnected to node 28.
Transistors 42 and 44 comprise a push-pull buffer circuit generally, identified by the numeral 50, for receiving the output of Schmitt trigger 30 for application to the remaining portion of clock generator 10 to be subsequently described and for buffering Schmitt trigger 30 from the capacitance present in clock generator 10. Transistor 44 may comprise, for example, enhancement type MOSFETs.' Transistor 42 may comprise, for example, a natural type MOSFET of low enhancement where " τ equals zero volts.'
Node 18 is interconnected to the drain of a transistor 54. The gate of transistor 54 is inter¬ connected to the drain of a transistor 56 forming a node 58 therebetween. The source of transistor 56 is connected to node 46, and the gate of transistor 56 is connected to power terminal 12. Clock generator 10 further includes transistors 60 and 62 interconnected in series between power terminal 12 and power terminal 14. The drain of transistor 60 is connected to power terminal 12. The gate of transistor 60 is connected to the source of transistor 54, forming a node 64. The source of transistor 60 is connected to the drain of transistor 62 thereby forming a node 66. The gate of transistor 62 is connected to node 46, and the source of transistor 62 is connected to power terminal 14.
Interconnected between nodes 64 and 66 is a MOS capacitor 68 wherein the gate is connected to node 64 and the source
Figure imgf000011_0001
and drain terminals of capacitor 68 are connected to node 66. Transistors 60 and 62 comprise enhancement type MOSFETs. MOS capacitor 68 may be utilized, for example, with a depletion implant wherein Vτ equals minus three volts.
Interconnected in series between power terminal 12 and power terminal 14 are transistors 70 and 72 forming a node 74 therebetween. The gate of transistor 70 is connected to power terminal 12, and the drain of transistor 70 is connected to node 64. The source of transistor 72 is connected to power terminal 14. The gate of transistor 72 is connected to receive via a node 75 a reset signal from a reset terminal 76. Also interconnected between power terminal 12 and pov/er terminal 14 are transistors 78 and 80- forming a node 82 therebetween. The gate of transistors 78 is connected to node 64. The drain of transistor 78 is connected to power terminal 12. The gate of transistor 80 is connected to node 46. The source terminal of transistor 80 is connected to power terminal 14. The output signal of clock generator 10 is produced at node 82 for application to an output terminal 86. Transistors 70, 72, 78 and 80 may comprise, for example, enhancement type MOSFETs.
The reset signal from terminal 76 is also applied via node 75 to the gate of a transistor 88. The drain of transistor 88 is connected to node 82. The source of transistor 88 is connected to power terminal 14. Transistor 88 may comprise, for example, an enhancement type MOSFET. Transistors 70, 72 and 88 are not a necessary part of clock generator 10, but are utilized if it is desired that clock generator 10 be reset at a time different than the reset of the input to clock generator 10 as will subsequently be described. The operation of clock generator 10 may best be understood by referring simultaneously to FIGURES 1 and 2. FIGURE 2 illustrates the voltage levels of the input signal, node 18, (FIGURE 2a), the output signal, node 82, 5 (FIGURE 2d), the voltage level of node 64 (FIGURE 2b) and the voltage level of node 46 (FIGURE 2c). Clock generator 10 provides a delay and buffer, such that as the input to clock generator 10 goes high, after a predetermined amount of delay, the output of clock generator 10 at node 82 will 10 go high. As the input to clock generator 10 goes high at node 18, node 64 is precharged through transistor 54. Simultaneously, Schmitt trigger 30 guarantees that a high level has been achieved on node 64 (reference numeral 90, FIGURE 2b) and after a delay forces node 46 low
15 (reference numeral 92, FIGURE 2c) allowing the voltage at nodes 82 and 66 to begin rising. Thereafter node 64 is bootstrapped by the action of capacitor 68 to a level above the input voltage (reference numeral 93, FIGURE 2b), for example, if an 80 percent bootstrap was utilized,
20 and the input voltage was fiv.e volts, node 64 would increase to nine volts. This voltage at node 64 allows transistor 78 to turn on hard to generate the output at node 82 of five volts.
__ Referring again to FIGURE 1, the operation of Schmitt
25 trigger 30 is such that when the input to clock generator 10 via input terminal 16 is zero, transistors 22 and 24 • are cutoff such that transistor 20 pulls node 26 to the voltage level of Vcc and transistor 40 pulls node 28 to a voltage level of Vcc less one threshold. As the input
30 on input terminal 16 begins to go high, transistor 24 turns on while transistor 22 still remains cutoff. As transistor 24 comes on, a resistor divider network is formed between transistor 40 and 24 to set the voltage at node 28. Since the gate of transistor 40 is at a voltage 5 level of V and the gate of transistor 24 is at the input voltage which is now rising, transistors 40 and 24 set the source voltage of transistor 22 such that Schmitt trigger 30 will not switch until the input voltage rises above the voltage level of node 28 plus one threshold. The switching level is set for Schmitt trigger 30 such that when the rising edge of the input signal to clock generator 10 goes from zero to a high, transistor 22 will switch with the generation of one volt provided by the resistor divider network of transistors 40 and 24.
After transistors 22 and 24 have been pulled to V and are hard on, node 26 is pulled close to zero volts which then causes cutoff of transistor 40, such that node 28 will also be at zero volts. As the input voltage decreases, nodes 26 and 28 are at zero volts and Schmitt trigger 30 will switch at a voltage level of less than a threshold to cutoff transistors 22 and 24 allowing node 26 to go to the level of V and node 28 to follow. The push-pull buffer circuit 50 comprising transistors 42 and 44 does not influence the operation of Schmitt trigger 30 since transistor 44 is always cutoff when transistor 22 is cutoff. Transistor 44 is not turned on until transistor 22 is turned on since their respective gate terminals and source terminals are respectively interconnected. Buffer 50, therefore, does not change the trigger point of Schmitt trigger 30. Buffer 50 allows transistor 20 to be fabricated very small such that a minimal value of current is dissipated when clock generator 10 is active since transistor 20 must only drive transistors 40 and 42.
Clock generator 10 is reset naturally by node 64 discharging through transistor 54 and node 46 going high as illustrated in FIGURES 2b and 2c. The output at node 82 cannot go low until node 46 goes high. As node 46 (FIGURE 2c) goes high, node 58 goes high such that node 64 can go low. Since node 58 must go high before node 64 goes low, there is a delay between node 46 going high and node 64 going low. Clock generator 10 can also be reset without using the natural discharge of node 64 through transistor 54. The waveforms illustrating the operation of clock generator 10 for resetting the output voltage at node 82 for application to output terminal 86 is shown in FIGURE 3. FIGURE 3b illustrates the reset voltage (reference numeral 94) applied at node 75 while the input voltage shown in FIGURE 3a is high. The reset signal is applied to transistors 88 and 72 which causes nodes 64 and 82 to discharge as shown in FIGURES 3c and 3e.
It therefore can be seen that the present clock generator 10 using Schmitt trigger 30 has improved response times while being independent of the input signal slew rate and input voltage patterns. The clock generator of the present invention achieves a fast reset time either by natural discharge or utilizing a reset signal. Furthermore, no precharge clock signal is necessary for the operation of the present clock generator. The use of buffer 50 prevents capacitive loading on Schmitt trigger 30 such that Schmitt trigger 30 can properly trigger, being pattern insensitive to the input voltage applied to clock generator 10. Without- the use of buffer 50, the capacitive loading due to the Miller capacitance of transistors 62 and 80 on Schmitt trigger 30 would not allow Schmitt trigger 30 to trigger in response to a rapidly changing pattern on the input to clock generator 10.
Whereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.

Claims

CLAIMS :
1. A delay stage which receives an input signal at an input terminal, produces an output signal at an output terminal' and is powered through first and second power terminals, comprising: detector means connected between the first and second power terminals and to the input terminal for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal; and buffer means connected between the first power terminal and the detector means for receiving said detection signal and for generating the output signal at the output terminal without capacitively loading said detector means.
2. The delay stage of Claim 1 wherein said detector means comprises Schmitt trigger means.
3. The delay stage of Claim 1 wherein said buffer means comprises push-pull inverter means.
4. The d.elay stage of Claim 2 wherein said Schmitt trigger means comprises: first, second and third trans'istors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors; and a fourth transistor having drain, source and gate terminals connected between the first power terminal and said second node and said gate terminal thereof connected to said first node.
5. The delay stage of Claim 4 wherein said buffer means comprises: fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node and forming a third node therebetween, said gate terminal of said fifth transistor connected to said first node, and said third node forming the output terminal and said gate terminal of said sixth transistor being connected to the input terminal.
6. A delay stage which receives -an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals/ comprising: first, second and third transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors; a fourth transistor having drain, source and gate terminals connected between the first power terminal and said second node, said gate terminal thereof connected to said first node; fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node, and forming a third node therebetv/een, said gate terminal of said fifth transistor connected to said first node, and said third node forming the output terminal; and said gate terminal of said second transistor, said gate terminal of said third transistor and said gate terminal of said sixth transistor being connected to the input terminal.
7. The delay stage of Claim 6 wherein said first transistor comprises a depletion type MOSFET.
8. The delay stage of Claim 6 wherein said first transistor comprises a saturated enhancement type MOSFET said gate terminal thereof being connected to the first power terminal.
9. The delay stage of Claim 6 wherein said second, third, fourth and sixth transistors comprise enhancement type MOSFETs.
10, The delay stage of Claim 6 wherein said fifth transistor comprises a natural type MOSFET.
11. The delay stage of Claim 6 wherein said first, second and third transistors comprise a Schmitt trigger stage and said fifth and sixth transistors comprise a push-pull inverter stage to prevent capacitive loading of said Schmitt trigger stage.
12. A delay stage which receives an input signal at an input terminal and is powered through first and second power terminals, comprising: a first transistor having drain, source and gate terminals, the drain terminal thereof connected to the first power terminal; a second transistor having drain, source and gate terminals, said drain terminal thereof connected to said source terminal thereof and being further connected to said gate terminal of said first transistor thereby forming a first node, said gate terminal thereof connected to the input terminal; a third transistor having drain, source and gate terminals, said drain terminal thereof connected to said source terminal of said second transistor thereby forming a second node, said gate terminal thereof connected to the input terminal, and said source terminal thereof connected to the second power terminal; a fourth transistor having drain, source and gate terminals, said drain terminal thereof connected to the first power terminal, said gate terminal thereof connected to said first node, and said source terminal thereof connected to said second node; a fifth transistor having drain, source and gate terminals, said drain terminal thereof connected to the first pov/er terminal, and said gate terminal thereof connected to said first node; and a sixth transistor having drain, source and gate terminals, said drain terminal thereof connected to said source terminal of said fifth transistor, said gate terminal thereof connected to the input terminal, and said source terminal thereof connected to said second node.
Bt*-'* - '>--~*
13. The delay stage of Claim 12 wherein said first transistor comprises a depletion type MOSFET.
14. The delay stage of Claim 12 wherein said first transistor comprises a saturated enhancement type MOSFET said gate terminal thereof being connected to the first power terminal.
15. The delay stage of Claim 12 wherein said second, third, fourth and sixth transistors comprise enhancement type MOSFETs.
16. The delay stage of Claim 12 wherein said fifth transistor comprises a natural type MOSFET.
17. The delay stage of Claim 12 wherein said first, second and third transistors comprise a Schmitt trigger stage and said fifth and sixth transistors comprise a push-pull inverter stage to prevent capacitive loading of said Schmitt trigger stage.
Figure imgf000021_0001
18. A clock generator circuit for producing clocking signals the circuit receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising: detector means connected between the first and second power terminals and to the input terminal for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal; buffer means connected between the first power terminal and the detector means for receiving said detection signal; a first transistor having drain, source and gate terminals, said drain terminal thereof connected to the input terminal; a second transistor having drain, source and gate terminals, said drain terminal thereof connected to said gate terminal of said first transistor, said gate terminal thereof connected to the first power terminal and said source terminal thereof connected to said buffer means; third and fourth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node therebetween, said gate terminal of said third transistor being connected " to said source terminal of said first transistor and said gate terminal of said fourth transistor being connected to said source terminal of said second transistor; capacitor means connected between said source terminal of said first transistor and said first node; and (Claim 18 Continued)
fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming the output terminal therebetween, said gate terminal of said fifth transistor connected to said gate terminal of said third transistor and said gate terminal of said sixth transistor connected to said gate terminal of said fourth transistor.
19. The clock generate circuit of Claim 18 wherein said detector means comprises Schmitt trigger means.
20. The clock generator circuit of Claim 18 wherein said buffer means comprises push-pull inverter means.
21. The clock generator circuit of Claim 19 wherein said Schmitt trigger means comprises: seventh, eighth and ninth transistors each having drain, source and gate terminals and being connected in series between the firt power terminal and the second pov/er terminal and forming a second node between said seventh and eighth transistors and a third node between said eighth and ninth transistors; and a tenth transistor having drain, source and gate terminals connected between the first power terminal and said third node and said gate terminal thereof connected to said second node.
22. The clock generator circuit of Claim 21 wherein said buffer means comprises: eleventh and twelfth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said third node and forming a fourth node therebetween, said gate terminal of said eleventh transistor connected to said second node, said gate terminal of said twelfth transistor being connected to the input terminal; and said fourth node being connected to said source terminal of said second transistor and to said gate terminals of said fourth and sixth transistors.
23. A clock generator circuit for producing clocking signals which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising: first, second and third transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors; a fourth transistor having drain, source and gate terminals connected between the first power terminal and said second node, said gate terminal thereof connected to said first node; fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node, and forming a third node therebetween, said gate terminal of said fifth transistor connected to said first node; said gate terminal of said second transistor, said gate terminal of said third transistor and said gate terminal of said sixth transistor being connected to the_input__terminal; a seventh transistor having drain, source and gate terminals, said drain terminal thereof connected to the input terminal; an eighth transistor having drain, source and gate terminals, said drain terminal thereof connected to said gate terminal of said seventh transistor, said gate terminal thereof connected to the first power terminal and said source terminal thereof connected to said third - node; ninth and tenth transistors each having drain, source and gate terminals and being connected in series between (Claim 23 Continued)
the first power terminal and the second power terminal and forming a fourth node therebetween, said gate terminal of said ninth transistor being connected to said source terminal of said seventh transistor and said gate terminal of said tenth transistor being connected to said source terminal of said eighth transistor; capacitor means connected between said source terminal of said seventh transistor and said fourth node; and eleventh and twelfth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming the output terminal therebetween, said gate terminal of said eleventh transistor connected to said gate terminal of said ninth transistor and said gate terminal of said twelfth transistor connected to said gate terminal of said tenth transistor.
24. The clock generator circuit of Claim 23 wherein said first transistor comprises a depletion type MOSFET.
25. The clock generator circuit of Claim 23 wherein said first transistor comprises a saturated enhancement type MOSFET said gate terminal thereof being connected to the first power terminal.
26. The clock generator circuit of Claim 23 wherein said second, third, fourth and sixth transistors comprise enhancement type MOSFETs.
27. The clock generator circuit of Claim 23 wherein said fifth transistor comprises a natural type MOSFET.
28. The clock generator circuit of Claim 23 v/herein said first, second and third transistors comprise a Schmitt trigger stage and said fifth and sixth transistors comprise a push-pull inverter stage to prevent capacitive loading of said Schmitt trigger stage.
29. The clock generator of Claim 23 and further including reset means.
30. The clock generator of Claim 29 wherein said reset means includes: thirteenth and fourteenth transistors each having drain, source and gate terminals, said gate terminal of said thirteenth transistor connected to the first power terminal, said drain terminal of said thirteenth transistor connected to said gate terminal of said ninth transistor, and said gate terminal of said fourteenth transistor forming a reset terminal; and a fifteenth transistor having drain, source and gate terminals, said drain terminal connected to the output terminal, said source terminal thereof connected to the second power terminal and said gate terminal thereof connected to said reset terminal.
PCT/US1980/001163 1980-09-10 1980-09-10 Delay stage for a clock generator WO1982000930A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/261,121 US4379974A (en) 1980-09-10 1980-09-10 Delay stage for a clock generator
WOUS80/01163800910 1980-09-10

Publications (1)

Publication Number Publication Date
WO1982000930A1 true WO1982000930A1 (en) 1982-03-18

Family

ID=22992038

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1980/001163 WO1982000930A1 (en) 1980-09-10 1980-09-10 Delay stage for a clock generator

Country Status (3)

Country Link
US (1) US4379974A (en)
EP (1) EP0060246A1 (en)
WO (1) WO1982000930A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0125257A1 (en) * 1982-11-17 1984-11-21 Motorola, Inc. Schmitt trigger circuit
EP0130587A2 (en) * 1983-06-29 1985-01-09 Siemens Aktiengesellschaft Input level converter for a digital MOS circuit
US4695808A (en) * 1984-02-27 1987-09-22 Ncr Corporation Varying frequency oscillator for the reduction of radiated emissions of electronic equipment
US5488627A (en) * 1993-11-29 1996-01-30 Lexmark International, Inc. Spread spectrum clock generator and associated method
US5872807A (en) * 1993-11-29 1999-02-16 Lexmark International, Inc. Spread spectrum clock generator and associated method

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57106228A (en) * 1980-12-24 1982-07-02 Fujitsu Ltd Semiconductor circuit
JPS57183119A (en) * 1981-05-02 1982-11-11 Sanyo Electric Co Ltd Schmitt circuit
JPS57197911A (en) * 1981-05-29 1982-12-04 Sanyo Electric Co Ltd Schmitt circuit
US4472644A (en) * 1981-12-10 1984-09-18 Mostek Corporation Bootstrapped clock driver including delay means
US4482826A (en) * 1982-02-16 1984-11-13 Lecroy Research Systems Corporation Programmable delay device
JPS595488A (en) * 1982-07-01 1984-01-12 Fujitsu Ltd Semiconductor device
US4508978A (en) * 1982-09-16 1985-04-02 Texas Instruments Incorporated Reduction of gate oxide breakdown for booted nodes in MOS integrated circuits
US4521701A (en) * 1982-09-16 1985-06-04 Texas Instruments Incorporated High-speed low-power delayed clock generator
DE3318564A1 (en) * 1983-05-20 1984-11-22 Siemens AG, 1000 Berlin und 8000 München INTEGRATED DIGITAL MOS SEMICONDUCTOR CIRCUIT
US4553051A (en) * 1983-07-18 1985-11-12 Texas Instruments Incorporated PMOS Input buffer compatible with logic inputs from an NMOS microprocessor
US4514647A (en) * 1983-08-01 1985-04-30 At&T Bell Laboratories Chipset synchronization arrangement
US4578601A (en) * 1983-12-07 1986-03-25 Motorola, Inc. High speed TTL clock input buffer circuit which minimizes power and provides CMOS level translation
JPS60224329A (en) * 1984-04-20 1985-11-08 Sharp Corp Input circuit of mos integrated circuit element
US4642492A (en) * 1984-10-25 1987-02-10 Digital Equipment Corporation Multiple phase clock buffer module with non-saturated pull-up transistor to avoid hot electron effects
US4689505A (en) * 1986-11-13 1987-08-25 Microelectronics And Computer Technology Corporation High speed bootstrapped CMOS driver
US4958088A (en) * 1989-06-19 1990-09-18 Micron Technology, Inc. Low power three-stage CMOS input buffer with controlled switching
DE4321315C1 (en) * 1993-06-26 1995-01-05 Itt Ind Gmbh Deutsche Clock generating circuit for clock-controlled logic circuits
JP5665299B2 (en) 2008-10-31 2015-02-04 三菱電機株式会社 Shift register circuit
JP5188382B2 (en) * 2008-12-25 2013-04-24 三菱電機株式会社 Shift register circuit

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3898479A (en) * 1973-03-01 1975-08-05 Mostek Corp Low power, high speed, high output voltage fet delay-inverter stage
US3984703A (en) * 1975-06-02 1976-10-05 National Semiconductor Corporation CMOS Schmitt trigger
US4061933A (en) * 1975-12-29 1977-12-06 Mostek Corporation Clock generator and delay stage
US4090096A (en) * 1976-03-31 1978-05-16 Nippon Electric Co., Ltd. Timing signal generator circuit
US4122361A (en) * 1975-11-28 1978-10-24 International Business Machines Corporation Delay circuit with field effect transistors
JPS54144833A (en) * 1978-05-04 1979-11-12 Nippon Telegr & Teleph Corp <Ntt> Readout circuit of semiconductor
US4242604A (en) * 1978-08-10 1980-12-30 National Semiconductor Corporation MOS Input circuit with selectable stabilized trip voltage
US4250408A (en) * 1979-02-28 1981-02-10 Rockwell International Corporation Clock pulse amplifier and clipper

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001722A (en) * 1975-05-19 1977-01-04 National Semiconductor Corporation Integrated circuit relaxation oscillator

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3898479A (en) * 1973-03-01 1975-08-05 Mostek Corp Low power, high speed, high output voltage fet delay-inverter stage
US3984703A (en) * 1975-06-02 1976-10-05 National Semiconductor Corporation CMOS Schmitt trigger
US4122361A (en) * 1975-11-28 1978-10-24 International Business Machines Corporation Delay circuit with field effect transistors
US4061933A (en) * 1975-12-29 1977-12-06 Mostek Corporation Clock generator and delay stage
US4090096A (en) * 1976-03-31 1978-05-16 Nippon Electric Co., Ltd. Timing signal generator circuit
JPS54144833A (en) * 1978-05-04 1979-11-12 Nippon Telegr & Teleph Corp <Ntt> Readout circuit of semiconductor
US4242604A (en) * 1978-08-10 1980-12-30 National Semiconductor Corporation MOS Input circuit with selectable stabilized trip voltage
US4250408A (en) * 1979-02-28 1981-02-10 Rockwell International Corporation Clock pulse amplifier and clipper

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0125257A1 (en) * 1982-11-17 1984-11-21 Motorola, Inc. Schmitt trigger circuit
EP0125257A4 (en) * 1982-11-17 1987-03-03 Motorola Inc Schmitt trigger circuit.
EP0130587A2 (en) * 1983-06-29 1985-01-09 Siemens Aktiengesellschaft Input level converter for a digital MOS circuit
EP0130587A3 (en) * 1983-06-29 1987-11-11 Siemens Aktiengesellschaft Berlin Und Munchen Input level converter for a digital mos circuit
US4695808A (en) * 1984-02-27 1987-09-22 Ncr Corporation Varying frequency oscillator for the reduction of radiated emissions of electronic equipment
US5488627A (en) * 1993-11-29 1996-01-30 Lexmark International, Inc. Spread spectrum clock generator and associated method
US5867524A (en) * 1993-11-29 1999-02-02 Lexmark International Inc. Spread spectrum clock generator and associated method
US5872807A (en) * 1993-11-29 1999-02-16 Lexmark International, Inc. Spread spectrum clock generator and associated method

Also Published As

Publication number Publication date
US4379974A (en) 1983-04-12
EP0060246A1 (en) 1982-09-22

Similar Documents

Publication Publication Date Title
US4379974A (en) Delay stage for a clock generator
US4090096A (en) Timing signal generator circuit
US4902910A (en) Power supply voltage level sensing circuit
KR0130037B1 (en) Semiconductor integrated circuit input buffer
GB2184622A (en) Output buffer having limited rate-of-change of output current
US5087835A (en) Positive edge triggered synchronized pulse generator
EP0130910B1 (en) A sense amplifier
US6486719B2 (en) Flip-flop circuits having digital-to-time conversion latches therein
US5801569A (en) Output driver for mixed supply voltage systems
US4894559A (en) Buffer circuit operable with reduced power consumption
US5157284A (en) Integrated circuit including an input buffer circuit having nand and nor gates
US4625126A (en) Clock generator for providing non-overlapping clock signals
US4239991A (en) Clock voltage generator for semiconductor memory
US4521701A (en) High-speed low-power delayed clock generator
US5489859A (en) CMOS output circuit with high speed high impedance mode
US6710627B2 (en) Dynamic CMOS circuits with individually adjustable noise immunity
US5160860A (en) Input transition responsive CMOS self-boost circuit
US4239990A (en) Clock voltage generator for semiconductor memory with reduced power dissipation
JPH03283182A (en) Semiconductor boosting circuit
US3965460A (en) MOS speed-up circuit
EP0244587B1 (en) Complementary input circuit
EP0125257A4 (en) Schmitt trigger circuit.
US5254890A (en) Ground bouncing reducing circuit and method
KR960006376B1 (en) Address transition detecting circuit
KR890004763B1 (en) The address transition detection circuit

Legal Events

Date Code Title Description
AK Designated states

Designated state(s): US

AL Designated countries for regional patents

Designated state(s): AT CH DE FR GB LU NL SE