WO1985002076A1

WO1985002076A1 - Integrated circuit timing apparatus

Info

Publication number: WO1985002076A1
Application number: PCT/GB1984/000375
Authority: WO
Inventors: Gerald Robert Talbot
Original assignee: Inmos Limited
Priority date: 1983-11-04
Filing date: 1984-11-02
Publication date: 1985-05-09
Also published as: EP0144158B2; JPS61500402A; GB8329511D0; EP0144158A1; EP0144158B1; US4689581A; DE3470987D1

Abstract

An integrated circuit device includes a timing apparatus arranged to produce timing signals whose frequency is a multiple of that of a clock signal. The timing apparatus, which includes a phase locked loop, is formed on a single chip and no external components are necessary. The phase locked loop includes a convertor and filter circuit (11), the convector (14) including two transistor current sources (19, 24) whose current magnitude is determined by a current reference circuit (13) including current mirror transistors (28, 31). The current sources (19, 24) are controlled by increase and decrease output signals from a phase and frequency comparator (7) such that the output of the convertor (14) depends upon the mark space ratio of the comparator output signals. The output of the convertor (14) is filtered and then fed as the control voltage to a voltage controlled oscillator (12). The oscillator output is fed by way of a divider to the phase comparator (7) and also provides the high frequency input timing signal for a logic device, such as a microcomputer (2). As the timing apparatus is fabricated using MOS technology, it is not possible to forecast its performance accurately. Surprisingly, it has been found that the timing apparatus of the invention is capable of exhibiting closed loop stability without further trimming. However, to ensure that such closed loop stability can always be obtained, additional components, for varying the parameters of the circuits may be provided, said components being connectible into the circuit by programmable switches, such as laser fuses (as 33, 42).

Description

INTEGRATED CIRCUIT TIMING APPARATUS

The present invention relates to a timing apparatus for gen erati ng timi ng pul ses.

For exampl e, the timing pul ses generated may be used for a microcomputer of the type described in our co-pending UK patent appl ication No. 8233733 or of the type described i n our co-pending European patent appl ication No. 83307078.2

The MOS technology processes used to manufacture microprocessors result in devices which are similar, but of varying performance. It is normal practice to measure the maximum operating speed of such devices after they have been manufactured, and it is found that the operating speed of the devices differ. The fast devices should be used with high frequency clock signals such that full advantage is taken of their potential to operate at high speeds, but the slower devices require a low frequency clock input. Thus, if the clock signals are to be matched to the operating speed of the , manufactured devices it is currently necessary to provide an external clock of suitable speed once the performance of the microprocessor has been determined.

Furthermore, it is difficult to generate and distribute high frequency clock signals, and presently this imposes a real and practical limitation to'the operating speed of current microprocessors and microcomputers.

Phase locked loops have been used for many years to construct frequency multipliers, and in recent times integrated circuit phase locked loops have been provided. However, the components - 2 -

of a phase locked loop are not easy to manufacture by existing integrated circuit manufacturing techniques such that existing integrated circuit phase locked loops require additional components external to the integrated circuit.

According to the present invention there is provided a timing apparatus including a control loop circuit and arranged upon receipt of a clock signal to produce a timing signal whose frequency is a multiple of that of said clock signal , said timing apparatus being formed on a single chip.

The present invention al so extends to an integrated circuit timing apparatus comprising a phase locked loop arranged to produce an output timi ng si gnal whose frequency is a multi ple of that of an input cl ock signal , wherein said phase locked l oop comprises a voltage controlled oscillator and means for generating a voltage signal for controlling sai oscillator, said generating means comprising one or more current sources.

According to a further aspect of the invention there is provided an integrated circuit device comprising a logic device connected to input and output pins, and a timing apparatus as defined above, an input of the timing apparatus being connected to one of the input pins for receipt of the clock signal , and an output of sai d timing apparatus being connected to said logic device to supply timing signal s thereto.

Preferably, said logic device is a microcomputer.

The present invention al so extends to a method of supplying tim ng signal s to an i ntegrated circuit logic device compri sing applying a low frequency clock signal to an input of said integrated circuit, including in said integrated circuit a timing apparatus for receiving said clock signal and producing a

CfcSPT iYATlθ timing signal having a frequency which is a multiple of that of said clock signal, and applying said high frequency timing frequency to said logic device.

5 Preferably, the operating speed of said logic device is determined and the frequency of the timing signal is matched to * said operating speed.

The present invention also provides timing apparatus arranged to 10 produce clock pulses, which timing apparatus includes a loop circuit incorporating a voltage oscillator, the output signal being a multiple of the frequency of the input signal, said voltage oscillator being responsive to the operation of one or more current sources, the operation of the current sources being 15 adjustable to modify the output frequency.

The aforesaid modification of the current sources may be achieved by laser fusing techniques.

0 The aforesaid current sources may include integrated circuits and the modification of the current sources may be effected by a variety of techniques which make or break connections in said integrated circuits. These may incorporate laser fuses, electrically blown fuses, non-volatile storage elements or laser 5 anti -fuses.

The invention includes a computer device, which may for example consist of a microcomputer, in combination with timing apparatus as aforesaid for generating clock pulses for use by the 0 computing apparatus.

The invention also includes a network of computer devices in which clock pulses are produced by timing apparatus as aforesaid. Embodiments of the present invention will hereinafter be described, by way of exampl e, with reference to the accompanying drawings, in which:

Figure 1 shows schematically an integrated circuit device including timi ng apparatus of the present invention;

Figure 2 shows an embodiment of a convertor and filter circuit of the timi ng apparatus of Figure 1 ,

Figure 3 shows a circuit diagram of one embodiment of a voltage controlled oscillator circuit of the timing apparatus of Figure 1 , and

Figure 4 shows a further embodiment of a vol tage control led oscillator ci rcuit of the timi ng apparatus.

Figure 1 shows an i ntegrated ci rcuit device fabricated using complementary MOS technology on a single sil icon chip 1. The integrated circuit device incl udes a logic device 2 connected to input and output pins 3.

In the embodiment il l ustrated, the logic device 2 is shown to be a microcomputer, and, for example, coul d be a microcomputer of the type described in our co-pending European Patent appl ication No. 83307078.2 which is^' fabricated on a single silicon chip .

However, the logic device 2 can be any circuit capable of performing logic operations which requires timing signal s. Thus, the logic device 2 coul d be a processor, a central processi ng unit, an arithmetic logic unit and the l ike.

The integrated circuit device of Figure 1 al so includes timing apparatus, generally indicated by the reference numeral 4, arranged to receive an external clock signal applied to one of the pins 3' and to generate a timing signal at an output 5 for appl cation to the logic device 2.

The timing apparatus 4 includes a control or closed loop circuit and is arranged to provide at its output 5 a timing signal whose frequency is a multiple of the frequency of the clock signal fed to its input 6 by way of the pin 3'.

As is clear from Figure 1, all of the components of the timing apparatus 4 are on the single silicon chip and the timing apparatus 4 has been designed such that it does not require any components external to the chip 1.

The basic structure of the control loop circuit of the timing apparatus 4 is apparent from Figure 1 and it will be seen that it is constituted by a phase locked loop. The clock signal applied to the pin 3' is connected by way of the input 6 to a digital phase and frequency comparator 7 which is arranged to compare the input clock signal with a further signal fed back from the output 5 by way of a divider 8.

If the phase or frequency of the signal fed by the divider 8 to the comparator 7 differs from the input clock signal the comparator 7 is arranged to produce appropriate output signals. In this respect, if the frequency of the input signal from the divider 8 is lower than that of the clock signal the comparator 7 will produce an increase output signal on its output 9 to indicate that the frequency is to be increased. Similarly, if the frequency of the signal fed by the divider 8 to the comparator 7 is higher than that of the clock signal the comparator will produce a decrease output signal at its output 10 to signify that the frequency of the output signal has to be decreased. The output signals from the comparator 7 on the outputs 9 and 10 are a series of pulses which are fed to a convertor and filter circuit 11 which is arranged to convert the output pulses from the comparator 7 into a voltage signal for controll ng the

5 frequency of oscillation of a voltage controlled oscillator circuit 12. In this respect, it is the amplitude of the voltage signal applied to the oscillator circuit 12 which determines the * frequency of the oscillations and hence the frequency of the signal appearing at the output 5 of the timing apparatus 4.

10

As described above, the high frequency output signal appearing at the output of the voltage controlled oscillator 12 is fed back by way of the divider 8 to the phase comparator 7. The divider 8 is arranged to divide the frequency of the signal at

15 its input by a predetermined integer N. It will thus be apparent that the phase locked loop will function to produce at its output 5 a signal whose frequency is N times the frequency of the clock signal applied to its input 6.

20 Generally, the comparator 7 will compare the frequency of its two input signals. However, when the phase locked loop has operated to make these frequencies substantially identical, the comparator 7 will compare the phases of the two input signals to accurately lock the loop.

25

Preferably, the divider 8 is programmable such that the value of the divider integer N may be varied as required. This can be done, for example, by providing connections in the divider circuit which can be made or broke as required. Thus, laser

30 fuses, electrically blown fuses, non-volatile storage elements and/or laser anti-fuses could be provided in the divider circuit 8.

It is known to use a phase locked loop to construct a frequency 35 multiplier in which the frequency of the output signal is a multipl e of the frequency of the input si gnal and in thi s respect, the basic operation of the phase l ocked l oop shown in Figure 1 wil l be clear to anyone skilled in the art and i s not further described herein.

For closed l oop stabil ity it can be shown that the Bode pl ot of the frequency response of the open loop shoul d have a positi ve phase margin when the logarithm of the gain is zero. The frequency response of the open loop is dependent upon both the centre frequency of the voltage control led oscillator circuit 12 • and the transfer function of the convertor and fi l ter circuit 1 1.

MOS manufacturing processes do not permit the physical properties of components of the integrated circuit to be sufficiently accurately control l ed and thus using MOS technology i t i s not possibl e to determine in advance the centre frequency of the oscil lations and the transfer function of the fil ter circuit. Thus, existing integrated circuit phase locked loops are provided with additional components external to the i ntegrated circuit. Generally, these external components incl ude fil tering circuits and circuits for determining the centre frequency of the oscil lator, these circui ts being chosen to have characteristics which correspond to the measured responses of the integrated circuit once it has been fabricated.

The integrated circuit phase locked loop of the present invention has been designed such that al l of its components can be manufactured using an MOS manufacturing process and such that external components are not required to provide closed loop stabil ity.

Originally, the inventors designed the phase locked loop to include optional and alternati ve components connectible into the loop by way of fuses such that manufacturing variations coul d be compensated. Surprisingly, they found that the desi gn of the convertor and filter circuit and of the voltage controlled oscillator meant that in many cases trimming of the phase locked loop was not necessary. Accordingly, in many practical cases, it is only necessary to provide for variation of the divider integer N of the divider 8 such that the frequency of the output signal can be chosen as is required.

The convertor and filter circuit 11 of the phase locked loop is shown in Figure 2 and is connected to receive both the increase output signal 9 and the decrease output signal 10 from the comparator 7. In this respect, each of the output signals from the comparator consists of a stream of pulses whose mark space ratio is proportional to the difference in frequency or phase identified by the comparator 7. The circuit 11 has the function of converting these streams of pulses into a DC voltage whose amplitude controls the voltage controlled oscillator 12. In addition, it is this circuit 11 which ensures the stability of the phase locked loop in that its transfer function is arranged to ensure that the loop has a positive phase margin at zero gain.

The circuit shown in Figure 2 comprises a programmable current reference circuit 13, a pulse^" to voltage convertor circuit 14, a filter circuit 15, and an output buffer 16 for feeding the output signal to the voltage controlled oscillator circuit 12.

The increase signal from output 9 is fed to a first input 17 of the convertor 14 and is' applied by way of a P channel transistor 18 to the gate of a further P channel transistor 19 which acts as a current source and whose source is connected to the voltage supply Vcc. The increase signal is also fed by way of an inverter 20 and a further P channel transistor 21 to the gate of the current source transistor 19. It will be appreciated that when negative going pulses of the increase signal are applied to the gate of the transistor 18, this transistor 18 will conduct and render the current source transistor 19 non-conductive. Positive going pulses of the increase signal when inverted by the inverter 20 and applied to the gate of the transistor 21 will cause the transistor 21 to conduct and apply negative pulses to the gate of the transistor 19 which will thus be rendered conductive. The magnitude of the current flow from the current source transistor 19 will be determined by the magnitude of the voltage applied to its gate and thus by the current reference circuit 13 as is described below.

The decrease output signal from comparator output 10 is applied to an input terminal 22 of the convertor circuit 14 and then to the gate of an N channel transistor 23 whose source-drain path is connected to the gate of an N channel transistor 24 which is also arranged to act as a current source, and whose source is connected to ground. The gate of the current source transistor 24 is also connected to the source-drain path of a further N channel transistor 25 whose gate is connected by way of an inverter 26 to the input terminal 22.

Negative going pulses applied to the input terminal 22 are inverted by inverter 26 such that the positive pulses applied to the gate of the transistor 25 render this transistor conductive and hence the current source transistor 24 non-conductive. The positive going pulses of the decrease signal will be effective to render the transistor 23 and hence the current source transistor 24 conductive and again the magnitude of the current flow will be determined by the voltage applied to the gate of the transistor 24.

The current source transistor 19 will thus be controlled by the increase signal to produce positive sense current pulses at an output 27 whilst the current source transistor 24 will be controlled by the decrease signal to produce negative sense current pulses at the output 27. It is required that the

O PI magnitude of the current produced at the output 27 by the transistor 19 in response to the application of a voltage of a predetermined magnitude at its gate be identical to that produced by the transistor 24 in response to the application of a voltage of the same predetermined magnitude at its gate. The magnitude of the current produced by each of the transistor current sources 19 and 24 is determined by way of the programmable current reference circuit 13 which utilizes current mirrors.

The programmable current reference circuit 13 incl udes_r an N channel current mirror provided by a transi stor 28 whose width to length ratio is substantial ly the same as that of the current source transistor 24. The gates of the transi stors 24 and 28 are connected together. The gate 34 of the current mirror transistor 28 is al so connected to its drain and by way of a further N channel transistor 29 to the vol tage supply Vcc. The resistance of the transistor 29 determines the source-drain current of the transistor 28 and hence the vol tage which appears on its gate 34. The gate voltage of the current mirror transistor 28 acts as a reference voltage which is appl ied to the gate of the transistor 24 to determine the current flowing therethrough . In thi s instance, as the transi stors 24 and 28 have the same width to length ratio , the currents flowing through the transi stors 24 and 28 wil l be the same.

The reference voltage appearing at the gate 34 of the transistor 28 and determining the current through the current source transistor 24 is al so applied to the gate of a further N channel transistor 30 whose source-drain path is connected by way of a P channel transistor 31 to the voltage source Vcc. The wi dth to l ength ratio of the transistors 28 and 30 is the same such that the current flowing through the transi stors 30 and 31 wil l be the same as that flowing in the transistor 24.

OM. I __ - 11 -

The P channel transi stor 31 i s in fact a current mirror for the P channel current source transi stor 19 of the convertor circuit 14. It wil l be seen that the gate of the P channel transistor 31 is connected to its drain such that the flow of current

5 through the transistor 31 puts a voltage on its gate which is al so appl ed to the gate of the transistor 19, and as the width to l ength ratios of the transistors 19 and 31 are the same, the

* current flowing through the transistor 19 wil l have the same magnitude as that flowing through transistor 31. Hence, i t will

10 be apparent that the reference circui t 13 i s operative to generate a predetermined reference voltage which is arranged to ensure that both of the current source transistors 19 and 24 provi de a current of equal magnitude.

Of course, the transistors 1 9 and 24, acting as current sources, 5 are control led by the appl ication of the increase and decrease signal pul ses appl ied to the i nput terminal s 17 and 22.

The magnitude of the current output from the current source transistors 19 and 24 i s determined by the val ue of the 0 reference vol tage and thi s in turn depends upon the wi dth to length ratios of the transistors 28 and 29. Clearly, the gains of the transistors 28 and 29 can be chosen as required and means can be provi ded for al tering the gain i f the CMOS ci rcui t as manufactured does not provide the required circuit parameters. 5

Thrus, i n the embodiment ^'il l ustrated in Figure 2, a further N channel transistor 32 is shown and its source-drai n path i s connected, by way of a programmabl e swi tch 33, in series with the source-drain path of the transistor 29. In the embodiment 0 shown, thi s programmable switch is a normal ly closed. fuse 33 which can be blown , for exampl e, by l aser. In the embodiment illustrated, with the fuse 33 normally closed, the gain exhibited by the transistor 28 is determined both by its width to length ratio and by that of the transistor 32. Thus, the 5 value of the reference voltage at gate 34 can be changed by blowing the fuse 33 to form an open circuit. If required, further transistors as 32 with appropriate fuse links as 33 can be provided.

The voltage convertor circuit 14 provides at its output 27 a plurality of positive and negative going current pulses whose magnitude is determined by the current reference circuit 13 but whose presence and frequency are controlled by the incoming increase signal pulses at input 17 and decrease signal pulses at input 22. The convertor and filter circuit 11 incorporates the filter 15 at whose output a voltage signal for controlling the voltage controlled oscillator circuit 12 is provided.

The filter circuit 15 is a low pass lead/lag filter also incorporated by CMOS techniques in the integrated circuit. It will be seen that this filter circuit 15 includes a MOS capacitor 35 which is connected between the output 27 of the convertor and ground by way of a capacitor 36. In addition, the MOS capacitor 35 is connected to ground by way of the source-drain path of a transistor 37. The transistor 37 is an N channel transistor biased by way of the control voltage appearing on its gate 38 to operate as a resistor and thereby form with the MOS capacitor 35 an RC filter. The control voltage at the gate 38 is determined by way of a current mirror incorporating an N channel transistor 39 connected to Vcc by way of a further N channel transistor 40. The control voltage at the gate 38 which determines that the transistor 37 functions as a resistor depends upon the width to length ratios of the transistors 39 and 40.

Cl early, the characteristics of the fi lter circuit 15 can be altered as required by altering the gains of the transistors 39 and 40. For exampl e, and as illustrated, a further N channel transistor 41 can have its source-drai n path connected by way of a programmabl e switch such as a fuse 42, to the source-drain

O PI path of the transistor 40. It woul d be intended that the fuse 42 be normal ly closed upon manufacture such that the gain exhibited by the transi stor 39 woul d be determined both by its width to length ratio and by that of the transistor 41. Blowing of the fuse 42 woul d render it open circuit and alter the control voltage at gate 38.

The voltage output signal from the fil ter circuit 15 is a DC vol tage whose magnitude i s determined by the mark space ratios of the input signal s fed to the convertor 14 at inputs 17 and

22. Thus, the appl ication of an i ncrease si gnal pul se causes an increase in the vol tage output of the fil ter whereas the appl ication of a decrease signal pul se causes the voltage to be decreased.

The output voltage from the filter circuit 15 is fed by way of a buffer circuit 16 which provides a low impedance drive circuit for the voltage controlled oscillator and also includes a filter to smooth out ripples in the output of the filter circuit 15.

The frequency of oscillation of the frequency controlled oscillator 12 is determined by the magnitude of the voltage signal fed thereto as indicated earlier. A first embodiment of the voltage controlled oscillator circuit 12 is illustrated in Figure 3.

The voltage-output from the buffer 16 is fed to an input terminal 43 of the voltage controlled oscillator circuit and is arranged to control the current flowing through an N channel transistor 44 acting as a current source and a P channel transistor 45 which also acts as a current source. The control voltage at input 43 is connected directly to the gate of the N channel transistor 44 such that it directly determines the current flowing through this transistor 44. The same current is arranged to be generated in the P channel transistor 45 by the use of current mirrors. Thus, the control voltage at input terminal 43 i s al so appl ied to the gate of a further N channel transistor 46 having the same width to length ratio as the transistor 44 such that the same current i s arranged to flow in

5 both transistors 44 and 46. The source-drain path of the transistor 46 is connected in series with the source-drain path of a P channel transistor 47 whose drain i s connected to its " gate. The gate vol tage of the P channel transi stor 47 is appl ied to the gate of the current source transistor 45 to

10 induce a current therein. It wil l be appreciated that when a predetermined voltage is appl ied to the input 43, both current source transi stors 44 and 45 will produce a current of the same magnitude.

15 The P channel transi stor 45 is connected by way of a further P channel transistor 48 to a node 53 connected to one terminal of a MOS capacitor 50. Sim larly, the current source transistor 44 is connected to the node 53 by way of an N channel transi stor 49. The transistors 48 and 49 are arranged to act as switches.

20

The gates of the two switching transi stors 48 and 49 are each connected by way of an inverter 51 to the output of a Schmitt trigger 52. The input of the Schmitt trigger 52 is al so connected to t e node 53.

25

Let us assume initially that the transi stor switch 48 i s ON such that the current supplied by the transistor current source 45, and determined by the magnitude of the vol tage at input 43, fl ows to charge the MOS capacitor 50. The vol tage on the gate

30 of the switch 48 from the inverter 51 will be low and able to maintain the transistor 48 ON and at the same time wil l hol d the transistor 49 OFF. The output from the Schmitt trigger 52 will be high and initial ly the i nput to the Schmitt trigger 52 will be low. However, the current fl owing into the capacitor 50 from

35 the current source 45 will increase the voltage at the node 53 and eventually will attain a trigger voltage for the Schmitt trigger 52 such that the output state of the Schmitt trigger 52 will change from high to low. A higg level voltage will then be applied by the inverter 51 to the gates of the transistors 49

5 and 48 switching the transistor 48 OFF and thereby curtailing the charging of the capacitor 50. The transistor switch 49 will be swiched ON such that the transistor 49 and the current source

► transistor 44 will provide a discharge path for the capacitor

50. The magnitude of the discharge current through the

10 transistor 44 will be determined by the magnitude of the voltage at the input terminal 43. Of course, as the capacitor 50 discharges the voltage at the node 53 will fall and when it reaches the other trigger value for the Schmitt trigger 52, the output of the Schmitt trigger will again change state. Thus, an

15 . oscillating output signal will be provided at the output 56 of the voltage controlled oscillator circuit and the oscillation will be sustained.

The frequency of the oscillation will depend upon the 20 capacitance of the MOS capacitor 50 and upon the value of the current flowing through the current sources 44 and 45 which is of course dependent upon the magnitude of the input voltage at input 43. As the input voltage increases so does the magnitude of the current flow and hence the speed with which the capacitor 5 is charged and discharged.

To make it possible for' the oscillator circuit 12 to have the required centre frequency to meet the needs of the overall phase locked loop, one or more additional MOS capacitors as 54 may be 0 provided as shown and connected to the node 53 by way of a respective programmable switch, such as a fuse 55. Initially, the or each fuse 55 would be closed, but if trimming of the circuit was necessary one or more of the fuses could be blown to provide an open circuit and thereby disconnect the respective 5 capacitor 54 from the node 53. Clearly, this would vary the

^ time constant of the capacitive circuit and hence vary the frequency of oscillations. Additionally, to enable variation of the current levels in the current sources 44 and 45, it would be possible to arrange connect additional transistors (not shown) in parallel with the current sources 44 and 45 such that the effective gains of these transistors could be varied. It is envisaged that any such transistors would be connected in circuit by way of programmable switches, such as fuses.

It is intended that the output of the oscillator circuit shown in Figure 3 be used as a high frequency clock signal, for example for a processor or microcomputer. In these circumstances it is generally necessary to provide at least two clock signals of complementary phase which do not overlap. Thus, the output of the oscillator circuit shown in Figure 3 could be applied by way of a two phase clock generator (not shown) to the microcomputer 2 (Fig.l).

Figure 4 shows an alternative embodiment of a voltage controlled oscillator circuit 12' which provides two oscillating output signals which are complementary in phase and which require only a minimum shaping before they can be applied to the microcomputer.

The voltage controlled oscillator circuit 12' shown in Figure 4 has an input terminal 70 to which the voltage output from the buffer 16 is applied, the circuit 12' includes a voltage controlled current source in the form of an N channel transistor 57 whose gate is connected to the input terminal 70. Thus, the current flowing in the transistor 57 is determined by the magnitude of the voltage applied to the input terminal 70. The source-drain path of the transistor 57 is connected in series with a first series connection of a P channel transistor 58 and

W ^'WIPO ^~ ,Λ* an N channel transistor 59 and with a second series connection of a P channel transistor 60 and an N channel transistor 61. It will be appreciated that the current flowing through each pair of transistors 58, 59, and 60, 61 will be determined by that 5 flowing through the N channel current source transistor 57.

The gates of the first pair of transistors 58 and 59 are " connected together and to the output of a NAND gate 62.

Similarly, the gates of the second pair of transistors 60 and 61 10 are connected together and to the output of a further NAND gate 63. A first input of each NAND gate is connected to a respective MOS capacitor. Thus, the first input of NAND gate 63 is connected to a node 65 connecting the drain of transistor 58 to the source of transistor 59, the node 65 also being connected 15 to a MOS capacitor 64. The second input of the NAND gate 63 is connected to the output of the NAND gate 62.

Similarly, a first input to the NAND gate 62 is connected to a node 67 at which the transistors 60 and 61 are connected, the

20 node 67 also being connected to a MOS capacitor 66. The second input to the NAND gate 62 is connected to the output of the NAND gate 63. It will also be seen that the output of the NAND gate 63 is connected to a first output terminal 68 whilst the output of the NAND gate 62 is connected to a second output terminal 69. 5

Consider initially that there i s a low l evel voltage at the output of the NAND gate' 62 which i s appl ied to the second i nput . of the NAND gate 63 and by way of the output 69 to the gates of the transistors 58 and 59. The P-channel transistor 58 wil l 0 therefore conduct and begin to charge the capacitor 64.

Initial ly there wil l be a low level vol tage on the first i nput to the NAND gate 63. The high level output of the NAND gate 63 is applied to the second input of the NAND gate 62 and by way of the output 68 to the transistors 60 and 61.

As the capacitor 64 is charged the first input to the NAND gate 63 will become high but the output of the NAND gate 63 will remain high.

The high output at the terminal 68 switches on the N channel transistor 61 and switches OFF the P channel transistor 60 such that the capacitor 66 is discharged by way of the transistor 61 and the current source transistor 57. A low going voltage is therefore applied to the first inpuτ to the NAND gate 62 whilst the high voltage is already applied to the second input. As the first input of NAND gate 62 goes from high to low its output switches from low to high such that the transistor 58 is switched OFF and the transistor 59 is switched ON such that discharging of the capacitor 64 is commenced by way of the current source transistor 57.

The high level output of the NAND gate 62 is fed to the second input of the NAND gate 63. As thi s NAND gate 63 also has a high appl ied to its first input, i ts output wil l go from hi gh to low. The P channel transistor 60 wil l thereby be switched ON and the N channel transistor 61 wil l be rendered non-conductive such that charging of the capacitor 66 wil l be commenced. Of course, once the discharge of the capacitor 64 puts a low on the first i nput of the NAND gate 63 the output state thereof will change and the state of the NAND gate 62 will similarly be changed.

It will be seen that an oscillating signal will be generated on each of the outputs 68 and 69. The speed of the discharge of the capacitors 64 and 66 is determined by the magnitude of the current flow through the current source transi stor 57 and hence upon the magnitude of the i nput vol tage at i nput 70. Thus, the frequency of the oscillations at each output terminal 68 and 69 i s determined by the magnitude of the i nput vol tage.

The capacitor 64 is generally being charged as the capacitor 66 is being discharged and vice versa. Thus, the output signals at terminals 68 and 69 are substantially 180° out of phase. There may be some overlap between the leading edge of one output signal and the trailing edge of the other, but this can be removed if required by shaping one or both of the output waveforms.

The centre frequency of the oscillator 12' can be changed as previously by connecting one or more transistors, as 71 into the circuit by way of respective fuses, as 72.

It will be appreciated that initialisation of the oscillators 12 and 12' shown in Figs. 3 and 4 may well be necessary. However, as initialisation techniques are well known, details thereof will not be described.

It will be seen from the description given above that the timing apparatus described including the phase locked loop is able to provide high frequency timing signals upon the application of a low frequency clock to the input thereof.

It thus becomes possible to supply a microcomputer incorporating apparatus on the same chip the timing as shown in Fig. 1. The user then needs only to connect the clock input pin 3' to a standard low frequency clock signal, at say 5MHZ, to obtain operation of the microcomputer at high operating speeds. Thus, it would be envisaged that the timing apparatus would generate timing signals having a frequency, eg, of the order of - 20 -

40-100MHZ. Furthermore, the user coul d use the same low frequency standard clock for a number of or a network of such microcomputers, the individual timing apparatus associated with each microcomputer providing suitabl e high frequency timing signal s for its microcomputer.

Of course, the timing apparatus of the invention i s not l imited to use with microcomputers, but can be used to provide timing signals for any logic device.

Claims

CLAIMS:

1. A timing apparatus including a control loop circuit and arranged upon receipt of a clock signal to produce a timing signal whose frequency is a multiple of that of said clock signal, said timing apparatus being formed on a single chip. 5

* 2. A timing apparatus as claimed in Claim 1, wherein said loop circuit is a phase locked loop including a voltage controlled oscillator.

10 3. An integrated circuit timing apparatus comprising a phase locked loop arranged to produce an output timing signal whose frequency is a multiple of that of an input clock signal, wherein said phase locked loop comprises a voltage controlled oscillator and means for generating a voltage signal for

15 controlling said oscillator, said generating means comprising one or more current sources.

4. A timing apparatus as claimed in Claim 3, wherein said phase locked loop further comprises means for comparing the output

20 timing signal and the input clock signal and providing comparison signals, said comparison signals being arranged to control said one or more current sources.

5. A timing apparatus as claimed in Claim 4, wherein said means 25 for comparing comprises' a frequency comparator having a first input to which said input clock signal is applied, and a second input connected to the output of a divider arranged to divide the frequency of the output timing signal by a predetermined integer. 6. A timing apparatus as claimed in Cl aim 5, wherein said comparator i s a phase and frequency comparator and is arranged to produce comparison output signal s indicating a di fference in either phase or frequency between the input clock si gnal and the 5 divi ded output timing signal and the direction of thi s d fference.

*^• 7. A timing apparatus as claimed in any of Cl aims 3 to 6, wherein the magnitude of the current produced by said one or

10 more current sources i s determined by a current reference circuit.

8. A timing apparatus as cl aimed in Cl aim 7, wherein the or each current source compri ses a transi stor, and wherein sai d

15 current reference circuit incl udes a current mirror transistor corresponding to each of sai d current source transistors, each current mirror transistor being arranged to determine the magnitude of the current produced by the corresponding current source transistor.

20

9. A timing apparatus as claimed in Claim 8, wherein said current reference circuit is arranged to generate a reference voltage for determining the current flowing in each of the current mirrors and hence in each of the current source

25 transistors.

10. A' ti ing apparatus^' as claimed in Cl aim 9, wherein all of sai d current mirror transistors are arranged in series so that said predetermined reference voltage determines that each

30 current source transistor produces current of the same magnitude.

11. A timing apparatus as claimed in Cl aim 9 or 10, wherein said current reference circuit includes means for varying said predetermined reference voltage.

12. A timing apparatus as claimed in Cl aim 11 , wherein sai d predetermined reference voltage is generated at a node connectibl e to the vol tage supply by way of a circuit for determining sai d predetermined reference voltage, said circuit incl uding a pl ural ity of components connectibl e by programmable switches.

>

13. A timing apparatus as cl aimed in Cl aim 12, wherein sai d programmable switches are fuses.

14. A timing apparatus as claimed in any of Claims 3 to 13, wherein said means for generating a voltage signal includes filtering means.

15. A timing apparatus as claimed in Claim 14, wherein said filtering means includes a capacitance coupled to a resistance, and wherein means are provided for varying the parameters of said filtering means.

16. A timing apparatus as claimed in Claim 15, wherein said means for varying the parameters of said filtering means includes one or more transistor means connectible by way of programmable switches.

17. A timing apparatus as claimed in Claim 16, wherein said programmable switches are fuses-.

18. A timing apparatus as claimed in any of Claims 3 to 17, wherein said voltage controlled oscillator includes means for varying its centre frequency.

19. A timing apparatus as claimed in Claim 18, wherein said voltage controlled oscillator includes at least one capacitive circuit and said means for varying the centre frequency includes ^' means for varying the time constant of said capacitive circuit.

«_» -*2H£T ' - 24 -

20. A timing apparatus as claimed in Claim 19, wherein said capacitive circuit includes a first capacitor and wherein said means for varying the time constant of the capacitive circuit includes at least one further capacitor connectible in parallel with said first capacitor by way of programmable switches.

21. A timing apparatus as claimed in Claim 19 or 20, wherein _> said means for varying the time constant of the capacitive circuit includes one or more transistor means connectible into said capacitive circuit by programmable switches.

22. A timing apparatus as claimed in Claim 20 or Claim 21 , wherein said programmable switches are fuses.

23. An integrated circuit device comprising a logic device connected to input and output pins, and a timing apparatus as claimed in any preceding claim, an i nput of sai d timing apparatus being connected to one of the input pins for receipt of the clock signal , and an output of sai d timing apparatus being connected to said logic device to supply timing signals thereto.

24. An integrated circuit device as claimed in Claim 23, wherein sai d logic device is a microcomputer.

25. A method of supplying timing signals to an integrated circuit logic device comprising applying a low frequency clock signal to an input of said integrated circuit, including in said integrated circuit a timing apparatus for receiving said clock signal and producing a timing signal having a frequency which is a multiple of that of said clock signal, and applying said high frequency timing frequency to said logic device.

26. A method as claimed in Claim 25, further comprising determining the operating speed of said logic device and matching the frequency of said timing signal to said operating speed.

OMPI