WO1985004487A1

WO1985004487A1 - Counting apparatus and method for frequency sampling

Info

Publication number: WO1985004487A1
Application number: PCT/US1985/000445
Authority: WO
Inventors: Charles K. Lee; Rex B. Peters; Aleksander M. Gogic
Original assignee: Sundstrand Data Control, Inc.
Priority date: 1984-03-23
Filing date: 1985-03-18
Publication date: 1985-10-10
Also published as: EP0177557A4; US4541105A; IT1181615B; NO854672L; BR8506054A; HK64687A; IT8547845A1; GB2166016B; IL74250A0; JPS61501528A; GB2166016A; IL74250A; EP0177557B1; CA1223454A; AU4112285A; EP0177557A1; GB8528018D0; IT8547845A0; JPH0720576U; DE3590124T1

Abstract

Prior techniques for determining frequency by counting the cycles of an input signal suffer from the limitation that counts are frequently lost between sampling intervals. This limitation is overcome by the present invention that provides an apparatus and method for counting the number of cycles of a sensor signal (FS) and of a reference signal (FR) that occur during respective sensor and reference intervals associate with a sampling interval defined by a sample signal (SAMPLE). The sensor, reference and sample signals are received by gating circuit (30) that generates a sensor gate signal (GATES) and a reference gate signal (GATER), the sensor and reference gate signals respectively defining the sensor and reference intervals. The sensor interval begins and ends synchronously with respect to the sensor signal, and the reference interval begins and ends synchronously with respect to the reference signal. The sensor, reference and sampling intervals are approximately co-extensive with one another. The apparatus further comprises a sensor court circuit (32) and a reference count circuit (34). The sensor count circuit counts cycles of the sensor signal that occur during the sensor interval, and the reference count circuit counts cycles of the reference signal that occur during the reference interval.

Description

"COUNTING APPARATUS AND METHOD FOR FREQUENCY SAMPLING "

Technical Field This invention relates to techniques for sampling the frequency of an input signal and for producing corresponding digital output signals. Background of the Invention

A common type of instrument is one in which a sensor produces a signal whose frequency is related in some functional way, often nonlinear, to a physical input variable. In order to use such a sensor in a digital system, the frequency of the sensor signal must be converted into a series of digital samples. The most versatile systems for measuring frequency operate either by counting cycles of the sensor or input signal for a known time interval, or by counting cycles of a reference signal for an interval controlled by the sensor signal. Using either technique, the resolution of such a frequency measurement depends on the number of counts that can be accumulated during the counting or sampling interval. The resolution may therefore be very poor at high sampling rates.

For wideband sensors such as accelerometers, sampling rates must often be much greater than would otherwise be required by system bandwidth requirements, in order to avoid errors due to frequency aliasing and input rectification. However, if resolution cannot be improved by digital low pass filtration, i.e., by averaging, substantial errors may be introduced by using high sample rates. With conventional frequency counting techniques counts are lost between adjacent sampling intervals, because the counters are reset for each sample. Therefore, with conventional frequency sampling methods, averaging several samples usually docs not significantly improve the resolution. Summary of the Invention

The present invention provides a method and apparatus for counting the cycles of a sensor signal and of a reference signal in such a way that no sensor or reference counts are lost. The counting technique of the present invention therefore permits resolution to be improved by averaging counts over a plurality of succesive sampling intervals. A preferred embodiment of an apparatus according to the present invention comprises gating means, sensor count means, and reference count means. A sample signal is provided that is operative to define a sampling interval. The gating means is responsive to the sensor, reference and sample signals to produce a sensor gate signal and a reference gate signal. The sensor gate signal has a characteristic that is operative to define a sensor interval that begins and ends synchronously with respect to the sensor signal. The reference gate signal has a characteristic that is operative to define a reference interval that begins and ends synchronously with respect to the reference signal. The sensor, reference and sample intervals are approximately coextensive with one another. The sensor count means counts the numbers of cycles of the sensor signal that occur during the sensor interval, and the reference count means counts the number of cycles of the reference signal that occur during the reference interval. The relationship of the frequency of the sensor signal to the frequency of the reference signal may thereby be determined.

In a preferred method according to the present invention, a sensor gate signal and a reference gate signal are produced in response to the sample, sensor and reference signals. The sensor and reference gate signals have characteristics that are operative to define the sensor and reference intervals respectively, and the sensor and reference signals are respectively counted during such sensor and reference intervals.

In a further embodiment, the present invention comprises a sensor for producing a sensor signal having a frequency that corresponds to an input variable, means for producing the reference and sample signals, counting means for counting the number of cycles of the sensor and reference signals that occur during respective time intervals associated with the sampling interval and for producing corresponding digital sensor and reference count signals, and processor means for receiving the sensor and reference count signals and determining therefrom the value of the input variable. The processor means may be operative to average values associated with the sensor and reference count signals over successive sampling intervals.

These and other features and advantages of the invention will become apparent in the detailed description and claims to follow, taken in conjunction with the accompanying drawings. Brief Description of the Drawings

FIGURE 1 is a block diagram of a device that includes a counting circuit according to the present invention. FIGURE 2 is a block diagram of a counting circuit according to the present invention.

FIGURE 3 is a circuit diagram of the counting circuit of FIGURE 2. FIGURE 4 is a timing diagram corresponding to the counting circuit of FIGURE 3.

Detailed Description of the Invention Referring initially to FIGURE 1, an instrument or device is shown that includes a counting circuit according to the present invention. The instrument includes sensor 12 that produces an output signal F_S whose frequency is a function of the variable sensed or measured by the sensor. It is desired to sample the value of this variable by converting the frequency of F_S into a series of digital signals usable by a data processing system comprising CPU 20. The conversion is carried out by counting circuit 10 of the present invention. The inputs to counting circuit 10 include sensor signal F_S, a SAMPLE signal, and a reference signal F_R. The SAMPLE signal defines a series of successive sampling intervals. During time periods associated with each sampling interval, counting circuit 10 counts the cycles of sensor signal F_S and of reference signal F_R. At the end of the respective time periods, the accumulated counts are stored. During the next sampling interval, counting circuit 10 outputs digital signals corresponding to the stored counts onto system bus 18. The digital signals are utilized by CPU 20 to determine the value of the variable sensed by sensor 12. As discussed below, CPU 20 may also average values corresponding to successive sampling intervals to improve resolution. Reference signal F_R preferably comprises a periodic signal that has a frequency higher than that of sensor signal F_S. In the embodiment of FIGURE 1, F_R is a comparatively high frequency square wave signal provided by clock 14, and is asynchronous with respect to sensor signal F_S. The SAMPLE signal is a comparatively low frequency signal that operates to define the sampling intervals. In the embodiment shown in FIGURE 1, SAMPLE is derived from F_R by means of Divide by N Circuit 16, such that SAMPLE consists of a comparatively low frequency square wave signal. In the embodiment illustrated herein, each complete cycle of the SAMPLE signal defines one sampling interval, and the end of one sampling interval and the beginning of the next sampling interval correspond to the rising edges of the SAMPLE pulses. Representative waveforms for F_S, F_R and SAMPLE are shown in FIGURE 4. It will be understood that it is not necessary to derive SAMPLE from F_R, and that SAMPLE may in general be asynchronous with respect to both F_S and F_R, and may have a form other than the square wave shown in FIGURE 4.

Referring now to FIGURE 2, a preferred embodiment of counting circuit 10 is shown comprising gating circuit 30, sensor count circuit 32, and reference count circuit 34. The sensor signal F_S is input to gating circuit 30 and to sensor count circuit 32. Similarly, reference signal F_R is input to gating circuit 30 and to reference count circuit 34. Gating circuit 30 also receives the SAMPLE signal Referring again to FIGURE 4, time interval T₁ is defined to be the interval between successive leading edges of the SAMPLE signal. Gating circuit 30 produces output signals GATE_S and GATE_R that operate to define the time intervals during which cycles of F_S and F_R respectively will be counted. In the illustrated embodiment, GATE_S follows SAMPLE on the falling edges of F_S. GATE_S therefore comprises a comparatively low frequency, square wave signal that has a period approximately coextensive with time interval T₁. However, GATE_S is shifted in time with respect to the SAMPLE signal such that GATE_S is synchronous with sensor signal F_S. In a similar fashion, GATE_R follows GATE_S on the falling edges of F_R. GATE_R therefore comprises a comparatively low frequency, square wave signal having a period that is also approximately coextensive with time interval T₁. However, GATE_R is shifted in time with respect to the SAMPLE signal such that GATE_R is synchronous with reference signal F_R. Thus GATE_S defines a time interval T₂ that is approximately coextensive with time interval T₁ , but that is synchronous with sensor signal F_S, and GATE_R defines a time interval T₃ that is approximately coextensive with time intervals T₁ and T₂, but that is synchronous with reference signal F_R. In particular, time intervals T₁ and T₂ are coextensive within ± 1 cycle of F_S, and time intervals T₂ and T₃ are coextensive within ± 1 cycle of F_R.

It is to be understood that GATE_S and GATE_R may each comprise one or more separate signals, and may comprise waveforms other than those shown in FIGURE 4, so long as the total GATE_S and GATE_R signals have characteristics that are operative to define appropriate time intervals T₂ and

^T3^.

Referring again to FIGURE 2, sensor count circuit 32 receives signals F_S and GATE_S, and responds by counting the number of cycles of F_S that occur during the time interval T₂ defined by signal GATE_S. In the particular embodiment illustrated, sensor count circuit 32 counts the number of cycles of F_S that occur during each complete cycle of signal GATE_S. At eaeh rising edge of GATE_S, the current count of F_S cycles is stored, and a new count is commenced. At any convenient time during the succeeding T₂ time interval, an output enable signal on line 36 causes sensor count circuit 32 to output the stored count of F_S cycles from the previous T₂ time interval onto system bus 18. The output enable signal on line 36 may be provided by any convenient means, such as by CPU 20 (FIGURE 1). Reference count circuit 34 operates in a manner similar to sensor count circuit 32. During each time period T₃ defined by signal GATE_R, reference count circuit 34 counts the number of cycles of reference signal F_R. In particular, reference count circuit 34 counts the number of cycles of F_R that occur during each complete cycle of signal GATE_R. At each rising edge of GATE_R, the current count of F_R cycles is stored, and a new count is begun. The stored count may then be retrieved at any time during the next T₃ time interval by providing an output enable signal on line 38. In response to such an output enable signal, reference count circuit 34 places the stored count of F_R cycles from the previous T₃ time interval onto system bus 18. The output enable signals on line 36 and 38 are of course coordinated so that they occur sequentially rather than simultaneously.

Referring now to FIGURE 3, a detailed embodiment of the present invention is illustrated. Gating circuit 30 comprises flip-flop 52, flip-flop 54, and inverters 56 and 58. Each flip-flop 52 and 54 is operative to transfer the signal (high or low) at its D input to its Q output at each rising edge of the signal at its CK input. As may be appreciated by reference to FIGURE 4, the result of the arrangement of flip-flop 52 and inverter 56 is that signal GATE_S, produced at the Q output of flip-flop 52, will tend to follow the SAMPLE signal at the D input of flip-flop 52, but GATE_S will only change to follow SAMPLE at the falling edges of F_S, such changes occurring at the falling rather than the rising edges of F_S due to inverter 56. In a similar manner, flip-flop 54 and inverter 58 will cause GATE_R to follow GATE_S, but GATE_R will only change to follow GATE_S at the falling edges of F_R. The result of this arrangement will therefore be the waveforms shown in FIGURE 4 for SAMPLE, GATE_S and GATE_R. Since F_S is asynchronous with respect to SAMPLE, GATE_S will lag SAMPLE by a variable delay which may range from the response time of flip-flop 52 up to one full cycle of F_S. Similarly, since F_R is asynchronous with respect to F_S, GATE_R will lag GATE_S by a variable delay which may range from the response time of flip-flop 54 up to one full cycle of F_R. Still referring to FIGURE 3, sensor count circuit 32 comprises counter 62, latch 64, initial value circuit 66, NAND gate 68 and flip-flop 70. Sensor signal F_S is input directly to the clock input (CK) of counter 62, and counter 62 responds by incrementing an internally stored count at each rising edge of F_S. As will be described below, the accumulated count in counter 62 is transferred to latch 64 at the beginning of each time interval T₂, and counter 62 is then reinitialized from initial value circuit 66. During the succeeding time interval T₂, an output enable signal on line 36 causes latch 64 to place its stored count for the previous T₂ time interval onto system bus 18.

The two inputs to NAND gate 68 are GATE_S and the signal on line 72 which originates at the

output of flip-flop 70. The D and CK inputs to flip-flop 70 are GATE_S and F_S, respectively. At each rising edge of F_S, output

of flip-flop 70 assumes a state (high or low) opposite to that of signal GATE_S. Referring to FIGURE 4, the result will be that prior to GATE_S going high, signal LOAD_S at the output of NAND gate 68 will be high because one of the NAND inputs (GATE_S) is low. The other input to the NAND gate, the signal on line 72, will be high at this time, because several low-to-high transitions of F_S have occurred since GATE_S went low. When GATE_S then goes high at the beginning of time interval T₂, the signal on line 72 will remain high until the next rising edge of F_S, i.e., for one-half cycle of F_S. During this half cycle, both NAND inputs will be high, and the NAND output signal LOAD_S will therefore be low, as indicated in FIGURE 4. LOAD_S is input into the load input (LD) of counter 62. Counter 62 is a conventional binary or decade counter that is operative to load the values specified by input value circuit 66 when the LD input of the counter goes high. In the embodiment shown in FIGURE 3, initial value circuit 66 connects the low order line of bus 74 to a high voltage through an appropriate resistor, and connects all other lines of bus 74 to a low voltage, thus supplying a initial count of +1. Therefore, one-half cycle (of F_S) after GATE_S goes high, counter 62 will be loaded with the initial value +1. Counter 62 will then proceed to increment its stored count by 1 each subsequent time that F_S goes high. An initial value.of +1 (rather than zero) is supplied to counter 62 because the first low to high transition of F_S occurs one half cycle after GATE_S goes high, at the same time or very slightly before LOAD_S goes high. The first low to high transition of F_S will therefore be missed by counter 62, such missed count being compensated for by the +1 value supplied by initial value circuit 66. At the end of time interval T₂, when GATE_S again goes high, the low-to-high transition at the CK input of latch 64 will cause the latch to store the accumulated count in counter 62. Reference count circuit 34 comprises counter 82, latch 84, initial value circuit 86, NAND gate 88 and flip-flop 90. The operation of the reference count circuit is very similar to that of sensor count circuit 32. Reference signal F_R is input directly to the clock input (CK) of counter 82, and counter 82 responds by incrementing an internally stored count at each rising edge of F_R. As will be described below, the accumulated count in counter 82 is transferred to latch 84 at the beginning of each time interval T₃, and counter 82 is then reinitialized from initial value circuit 86. During the succeeding time interval T₃, an output enable signal on line 38 causes latch 84 to place its stored count for the previous T₃ time interval onto system bus 18.

The two inputs to NAND gate 88 are GATE_R and the signal on line 92 which originates at the

output of flip-flop 90. The D and CK inputs to flip-flop 90 are GATE_R and F_R, respectively. At each rising edge of F_R, output of flip-flip 90 will assume a state (high or low) opposite to that of signal GATE_R. Referring to FIGURE 4, the result will be that prior to GATE_R going high, signal LOAD_R at the output of NAND gate 88 will be high, because one of the NAND inputs (GATE_R) is low. The other input to the NAND gate, the signal on line 92, will be high at this time, because several low-to-high transitions of F_R have occurred since GATE_R went low. When GATE_R then goes high at the beginning of time interval T₃, the signal on line 92 will remain high until the next rising edge of F_R, i.e., for one-half cycle of F_R. During this half cycle, both NAND inputs will be high, and the NAND output signal LOAD_R will therefore be low, as indicated in FIGURE 4. LOAD_R is input into the load input (LD) of counter 82. Counter 82 is a conventional binary or decade counter that is operative to load the values specified by input value circuit 86 when the LD input of the counter goes high. In the embodiment shown in FIGURE 3, initial value circuit 86 connects the low order line of bus 94 to a high voltage through an appropriate resistor, and connects all other lines of bus 94 to a low voltage, thus supplying an initial count of +1. Therefore, one-half cycle (of F_R) after GATE_R goes high, counter 82 will be loaded with the initial value +1. Counter 82 will then proceed to increment its stored count by 1 each subsequent time that F_R goes high. An initial value of +1 (rather than zero) is supplied to counter 82 because the first low to high transition of F_R occurs one-half cycle after GATE_R goes high, at the same time or very slightly before LOAD_R goes high. The first low to high transition of F_R will therefore be missed by counter 82, such missed count being compensated for by the +1 value supplied by initial value circuit 86. At the end of time interval T₃, when GATE_R again goes high, the low-to-high transition at the clock input of latch 84 will cause the latch to store the accumulated count in counter 82.

In an instrument of the general type shown in FIGURE 1 in which a conventional counting circuit is used, the resolution of the system generally cannot be improved by averaging the counts or frequencies over a number of sampling intervals. The reason that averaging does not improve resolution is that in conventional counting circuits, the counters are reset at the end of a fixed sampling interval. Since the sensor and reference signals are asynchronous, the result is that partial counts of either the sensor signal or the reference signal are lost. The present invention provides a technique for avoiding the loss of partial counts, allowing a significant improvement in system resolution through averaging.

The advantages of the present invention can be illustrated by means of the following calculations. Let n and m be the number of sensor and reference pulses respectively accumulated for one sampling interval. If f_s and f_r are the frequencies of signals F_S and F_R respectively, then the measured sensor frequency f_sm is:

Assuming that f_r is larger than f_s , the asynchronous relationship between F_S and

F_R means that for each sampling interval, there is an error or uncertainty Δ m in the value of m, with Δm being in the range -1 to +1. The relationship between f_r and the true sensor frequency f_s is therefor:

By co mbining equations (1) and (2), one obtains:

The k-th moment E {( Δ m)^k} of the error Δ m is given by:

E { ( Δm)^k} = ½ ∫ -⁺ ₁ ¹ (Δm)^k d(Δ m) (4)

since Δm has a uniform probability density in the range -1 to +1. We obtain E { Δ m } - 0 and E{( Δm)² } = 1/3. If sensor 12 is, for example, an accelerometer for measuring acceleration a, and if there is a linear relationship between acceleration a and frequency f_s such that:

a = A₁f_s + A₀ (5)

then the measured acceleration a_m can be written:

a_m = a + Δa (6)

where Δa = A₁ f_s Δm/m is the resolution error due to sampling. Thus the resolution error can be reduced by making m large, i.e., by lengthing the sampling period or by increasing the reference frequency f_r. The resolution can also, however, be improved by averaging over several samples. The reason that averaging can improve resolution is that the counting circuit of the present invention does not lose any counts between sampling intervals, and thus, for example, a partial F_R cycle not counted in one sampling interval will be counted during the next sampling interval. The total count for a succession of sampling intervals will therefore be correct, and resolution can be significantly improved by averaging. In the limit of an infinite number of samples to be averaged, the resolution error for the linear sensor modeled by equation 5 will be zero, since:

and E {Δm} = 0.

For a nonlinear relationship between acceleration and frequency, such as a quadratic relationship of the form:

a = A₁ f_s ² + A₀ (8)

the resolution error Δa in equation (6) becomes:

Since E{ ( Δm)² } = 1/3, the resolution error for the limiting case of an infinite number of samples will be:

For most practical instruments, however, the resolution error indicated by equation (10) will be extremely small.

While the preferred embodiments of the invention have been illustrated and described, it should be understood that variations will become apparent to those skilled in the art. Accordingly, the invention is not to be limited to the specific embodiments illustrated and described, and the true scope and spirit of the invention are to be determined by reference to the following claims.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An apparatus for counting the number of cycles of a sensor signal and of a reference signal that occur during respective time intervals associated with a sampling interval defined by a sample signal, whereby the relationship of the frequency of the sensor signal to the frequency of the reference signal may be determined, the apparatus comprising: gating means responsive to the sample signal and to the sensor and reference signals for producing a sensor gate signal and a reference gate signal, the sensor gate signal having a characteristic thereof that is operative to define a sensor interval that begins and ends synchronously with respect to the sensor signal, the reference gate signal having a characteristic thereof that is operative to define a reference interval that begins and ends synchronously with respect to the reference signal, the sensor, reference and sampling intervals being approximately coextensive with one another; sensor count means for counting the number of cycles of the sensor signal that occur during the sensor interval; and reference count means for counting the number of cycles of the reference signal that occur during the reference interval.

2. The apparatus of Claim 1, wherein the sample signal has a characteristic thereof that is operative to define a plurality of successive fixed length sampling intervals, and wherein the gating means, the sensor count means and the reference count means are operative to perform their respective functions for each of the successive sampling intervals, whereby the cycles of the sensor signal and the cycles of the reference signal are counted during time intervals associated with each successive sampling interval.

3. The apparatus of Claim 2, wherein the successive sampling intervals immediately follow one another, and wherein the gating means produces the sensor and reference gate signals for successive sampling intervals such that the end of the sensor interval associated with one sampling interval coincides with the beginning of the sensor interval associated with the next sampling interval, and the end of the reference interval associated with one sampling interval coincides with the beginning of the reference interval associated with the next sampling interval

4. The apparatus of Claim 1, wherein the gating means is operative to cause the sensor interval to commence at the beginning of the first cycle of the sensor signal that occurs after the beginning of the sampling interval, and to end at the beginning of the first cycle of the sensor signal that occurs after the end of the sampling interval.

5. The apparatus of Claim 1, wherein the gating means is operative to cause the reference interval to commence at the beginning of the first cycle of the reference signal that occurs after the beginning of the sensor interval, and to end at the beginning of the first cycle of the reference signal that occurs after the end of the sensor intervaL

6. A method for counting the number of cycles of a sensor signal and a reference signal that occur during respective time intervals associated with a sampling interval defined by a sample signal, whereby the relationship of the frequency of the sensor signal to the frequency of the reference signal may be determined, the method comprising: producing a sensor gate signal and a reference gate signal in response to the sample signal and to the sensor and reference signals, the sensor gate signal having a characteristic thereof that is operative to define a sensor interval that begins and ends synchronously with respect to the sensor signal, the reference gate signal having a characteristic thereof that is operative to define a reference interval that begins and ends synchronously with respect to the reference signal, the sensor, reference and sampling intervals being approximately coextensive with one another; counting the number of cycles of the sensor signal that occur during the sensor interval; and counting the number of cycles of the reference signal that occur during the reference interval.

7. The method of Claim 6, wherein the sample signal has a characteristic thereof that is operative to define a plurality of successive fixed length sampling intervals, wherein the sensor and reference gate signals are produced for each successive sampling interval to define respective sensor and reference intervals associated with each successive sampling interval, and wherein the cycles of the sensor and reference signals are counted during the respective sensor and reference intervals associated with each successive sampling interval.

8. The method of Claim 7, wherein the successive sampling intervals immediately follow one another, wherein the sensor and reference gate signals are produced such that for successive sampling intervals, the end of the sensor interval associated with one sampling interval coincides with the beginning of the sensor interval associated with the next sampling interval, and the end of the reference interval associated with one sampling interval coincides with the beginning of the reference interval associated with the next sampling interval.

9. The method of Claim 6, wherein the sensor interval commences at the beginning of the first cycle of the sensor signal that occurs after the beginning of the sampling interval, and ends at the beginning of the first cycle of the sensor signal that occurs after the end of the sampling interval.

10. The method of Claim 6, wherein the reference interval commences at the beginning of the first cycle of the reference signal that occurs after the beginning of the sensor interval, and ends at the beginning of the first cycle of the reference signal that occurs after the end of the sensor interval.

11. An apparatus for measuring an input variable comprising:

(a) a sensor for producing a sensor signal, the frequency of the sensor signal corresponding to the value of the input variable;

(b) means for producing a periodic reference signal; (c) means for producing a sample signal that is operative to define a sampling interval;

(d) counting means for counting the number of cycles of the sensor signal and of the reference signal that occur during respective time intervals associated with the sampling interval, the counting means further comprising:

(1) gating means responsive to the sample signal and to the sensor and reference signals for producing a sensor gate signal and a reference gate signal, the sensor gate signal having a characteristic thereof that is operative to define a sensor interval that begins and ends synchronously with respect to the sensor signal, the reference gate signal having a characteristic thereof that is operative to define a reference interval that begins and ends synchronously with respect to the reference signal, the sensor, reference and sampling intervals being approximately coextensive with one another;

(2) sensor count means for counting the number of cycles of the sensor signal that occur during the sensor time interval and for producing a corresponding digital sensor count signal;

(3) reference count means for counting the number of cycles of the reference signal that occur during the reference time interval and for producing a corresponding digital reference count signal; and

(e) processor means for receiving the sensor and reference count signals and determining therefrom the value of the input variable.

12. The apparatus of Claim 11, wherein the sample signal has a characteristic thereof that is operative to define a plurality of successive fixed length sampling intervals, and wherein the gating means, the sensor count means and the reference count means are operative to perform their respective functions for each of the successive sampling intervals, whereby a sensor count signal and a reference count signal are produced for each successive sampling interval.

13. The apparatus of Claim 12, wherein the successive sampling intervals immediately follow one another, wherein the gating means produces the sensor and reference gate signals for successive sampling intervals such that the end of the sensor interval associated with one sampling interval coincides with the beginning of the sensor interval associated with the next sampling interval, and the end of the reference interval associated with one sampling interval coincides with the beginning of the reference interval associated with the next sampling interval.

14. The apparatus of Claim 13, wherein the processor means is operative to average values associated with the sensor and reference count signals for said successive sampling intervals, to thereby determine the value of the input variable over time.

15. The apparatus of Claim 11, wherein the gating means is operative to cause the sensor interval to commence at the beginning of the first cycle of the sensor signal that occurs after the beginning of the sampling interval, and to end at the beginning of the first cycle of the sensor signal that occurs after the end of the sampling interval.

16. The apparatus of Claim 11, wherein the gating means is operative to cause the reference interval to commence at the beginning of the first cycle of the reference signal that occurs after the beginning of the sensor interval, and to end at the beginning of the first cycle of the reference signal that occurs after the end of the sensor interval.