WO1987000967A1 - Dielectric breakdown prevention technique - Google Patents

Dielectric breakdown prevention technique Download PDF

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Publication number
WO1987000967A1
WO1987000967A1 PCT/US1986/001170 US8601170W WO8700967A1 WO 1987000967 A1 WO1987000967 A1 WO 1987000967A1 US 8601170 W US8601170 W US 8601170W WO 8700967 A1 WO8700967 A1 WO 8700967A1
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WO
WIPO (PCT)
Prior art keywords
gates
metal
metal layer
layer
gate
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Application number
PCT/US1986/001170
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French (fr)
Inventor
Dennis Carl Hartman
Shih King Cheng
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Motorola, Inc.
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Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Publication of WO1987000967A1 publication Critical patent/WO1987000967A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Definitions

  • the invention relates to the construction of metal oxide semiconductor (MOS) integrated circuits, and more particularly relates to methods and apparatus for preventing thin gate dielectric breakdown during the ion implantation step in the manufacture of MOS integrated circuits.
  • MOS metal oxide semiconductor
  • a silicon substrate is divided up into areas in which devices are to be built, the areas being separated from each other by dielectric isolation regions.
  • a gate of conductive material is usually electrically isolated from the silicon substrate by a thin layer of dielectric material, generally between 50 and 1000 Angstroms thick.
  • MOS semiconductor device under construction is generally referred to as device 10.
  • MOS semiconductor device 10 is positioned on a monocrystalline silicon substrate 12 between two dielectric isolation regions 14.
  • a thin dielectric layer 16 is present upon silicon substrate 12 between the two isolation regions 14.
  • the portions of the thin dielectric layer 16 not immediately under gate 18 which are between the gate 18 and the isolation regions 14 is etched away.
  • gate 18 is electrically isolated from silicon substrate 12.
  • the gate 18 can be charged up to a very high voltage, and a large potential difference can build up between the gate 18 and the silicon substrate 12. This potential difference can lead to gate dielectric breakdown, which is a catastrophic defect that severely limits circuit yield.
  • Metal layer 20 may be any conductive metal such as aluminum, e.g. Metal layer 20 may be deposited before or after the thin dielectric layer 16 is removed in the future source/drain regions.
  • the metal layer 20 shorts the gate 18 to the silicon substrate 12 or to another grounded surface, such as a clamping ring in the ion implanter and thus helps reduce the charge build-up on the gate 18. This layer 20 can therefore prevent the catastrophic gate dielectric breakdown.
  • the metal layer 20 is subsequently stripped in an etch proces that is selective to silicon and the dielectric material.
  • the dielectric material is silicon dioxide, Si ⁇ 2, often referred to simply as oxide.
  • metal layer 20 to prevent the breakdown of the thin gate dielectric 16 has the disadvantages of requiring an° extra metal deposition and an extra etch step to remove it, of course. Further, to ensure that the gate 18 is shorted to the silicon substrate 12, excellent sidewall step coverage of the aluminum metal layer 20 is necessary. Standard sputter deposition processes suffer from poor sidewall step coverage. Typically, the metal must be deposited in a thicker application than usual in order to achieve good sidwall coverage. In turn, metal layer 20 can cause problems with the ion implantation process; for instance, ion scattering and lack of adequate ion penetration can lead to loss of junction depth and doping distribution coritrol. Further, the ion implantation process can drive unwanted metals, such as the aluminum, into the source, drain and gate regions.
  • Another object of the present invention is to provide a technique for preventing thin gate dielectric breakdown during ion implantation processes that involves the use of metal suicided gates and source/drain regions and the associated advantages of metal silicide layers such as a reduced contact resistance of the interconnect layer to the silicon substrate.
  • Still another object of the present invention is to provide a thin gate dielectric breakdown prevention process which has excellent sidewall step coverage of a thin layer for shorting the gate to the silicon substrate during ion implantation. .
  • Yet another object of the present invention is to provide a technique for preventing the breakdown of thin dielectric gate layers which does not involve the risk of driving unwanted metals into the gate and source/drains during the ion implantation step.
  • a method for preventing thin gate dielectric breakdown during ion implantation in the fabrication of MOS integrated circuits having sili ⁇ ided gates, sources and drains which involves first forming a plurality of dielectric sidewall spacers one each around a plurality of electrically isolated MOS device gates on a silicon substrate and then depositing a layer of metal over the gates, dielectric sidewall spacers and substrate, for shorting the gates to the substrate. Next, the source and drain regions around the gates between the sidewall spacers and the isolation regions are ion implanted through the metal layer.
  • the metal layer in the source, drain and gate regions is reacted with the silicon substrate or the polysilicon of the gate in the presence of heat to form a plurality of metal silicide interconnect layers. Finally, the unreacted portions of the metal layer overlying the dielectric isolation regions and sidewall spacers is stripped off.
  • FIG. 1 is a cross-sectional illustration of a single MOS semiconductor device under construction after the gate has been formed
  • FIG. 2 is a cross-sectional illustration of the MOS - device under construction from FIG. 1 that has had a metal layer deposited over it in accordance with a prior art technique for preventing thin gate dielectric breakdown;
  • FIG. 3 is a cross-sectional.illustration of the MOS device of FIG. 1 under construction that has had a sidewall spacer formed prior to dielectric layer etch;
  • FIG. 4 is a cross-sectional ''illustration of the MOS device of FIG. 3 under construction during an ion implantation process after formation of a thin metal protective layer in accordance with the technique of this invention.
  • FIG. 5 is a cross-sectional illustration of the MOS device from FIG. 4 in essentially finished formed after fabrication in accordance with the method of the invention. Detailed Description of the Invention
  • FIG. 1 Shown in FIG. 1 is a MOS semiconductor device 10 under construction.
  • Dielectric isolation regions 14 surrounding device 10 have already been formed on and in monocrystalline silicon substrate 12.
  • Thin dielectric layer 16 has also been formed and a gate 18 has been formed upon it.
  • the thin dielectric layer is defined as between about 50 and 1000 Angstroms thick.
  • the dielectric material of which isolation regions 14 and thin layer 16 are made may be, but is not limited to, silicon dioxide, Si ⁇ 2-
  • gate 18 may be polycrystalline silicon, but is not limited to that material.
  • FIG. 2 Shown in FIG. 2 is the prior art technique of protecting a semiconductor device 10 under construction, which has already been discussed.
  • FIG. 3 Shown in FIG. 3 is the first new step in the method of this invention, which follows FIG. 1 in sequence.
  • a dielectric material is deposited over the entire wafer surface which is in the condition shown in FIG. 1.
  • the dielectric layer is then anisotropically reactive ion or plasma etched to leave a single, continuous sidewall spacer 22 on the sides of the gate.
  • the spacer 22 is necessary and will be used later to prevent shorting of the gate 18 to the substrate 12 during silicidation.
  • the thickness of this .dielectric material will determine the spacer width and is not critical to successful performance of the invention. The optimum width will depend on the device under consideration.
  • sidewall spacers such as spacer 22
  • the spacers may be made out of any dielectric material that has good sidewall step conformance so that the spacer 22 may be formed. Perfect sidewall step con ⁇ formance is not required, however.
  • One example, which does not limit the invention herein is CVD silicon dioxide.
  • the sidewall spacer 22 is not limited by its shape or method of formation.
  • the thin dielectric layer 16 between the sidewall spacer 22 and the isolation regions 14 is selectively etched away to give the structure shown in FIG. 3. In actual practice, the thin dielectric layer 16 etch and the etch of the material to form sidewall spacer 22 may conducted at the same time.
  • the dielectric material of spacer 22 be the same material as that of thin dielectric layer 16. It is noted that a remaining portion of thin dielectric layer 16 completely underlies gate 18 and sidewall spacers 22.
  • An important feature of the invention is to deposit the metal that will be used to silicide the source, drain and gate regions before the ion implantation process.
  • Suitable metal layers include, but are not limited to chemical vapor deposited (CVD) tungsten, titanium, molybdenum, tantalum and platinum and their equivalents. Although the invention is not limited hereby, the invention will be further described as if CVD tungsten were used.
  • CVD chemical vapor deposited
  • FIG. 4 ' Shown in FIG. 4 ' is the thin CVD tungsten layer or thin gate dielectric breakdown protective layer 24 which has been deposited over the entire surface of the wafer including sidewall spacer 22, gate 18 and isolation regions 14.
  • the thin tungsten metal layer 24 shorts the polysilicon gate 18 to the silicon substrate 12 thereby ⁇ preventing the build-up of charge on gate 18 during the ion implantation process, which is indicated by the downward pointing arrows in FIG. 4. Since the tungsten will eventually be reacted with the silicon in the source, drain and gate regions, the drive-in of tungsten in these regions during the ion implantation step should not be a problem.
  • any suitable masking layer such as photoresist, can be used to prevent implantation of n-channel devices during p-channel implantations and vice versa.
  • This technique is well known in the construction of CMOS integrated circuits, and thus no change in masking requirements is needed.
  • the actual ion implantation steps do not form a part of this invention and it is believed that any ion implantation method would work with this invention.
  • the metal such as tungsten
  • the metal is reacted to selectively form metal silicide, in this hypothetical example, Si2, in the source drain and gate regions.
  • metal silicide in this hypothetical example, Si2
  • this reaction typically occurs at 600 to 900°C.
  • Gate interconnect layer 26 and source/drain region interconnect layers 28 are formed by this silicidation reaction.
  • the sidewall spacer 22 prevent the gate 18 from shorting to the substrate 12.
  • the unreacted tungsten metal is finally stripped off with an appropriate chemical that does not etch Si ⁇ 2 or the metal silicide.
  • hydrogen peroxide would be a suitable etchant.
  • a standard MOS process flow can then be used to complete the fabrication of the circuit.
  • source/drain regions 30 must be activated or driven in at some point in the process.
  • MOS devices that will eventually have metal silicide gate and source/drain interconnections can be effectively protected against catastrophic thin gate dielectric breakdown by the same metal that will be used to silicide the gate and source/drain interconnects. Thus, an additional metal deposition and an additional etch need not be performed.
  • the t metal layer can be thin, as CVD metals conform well around the sidewall spacer 22. Further, the metal silicide layers 26 and

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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A technique for preventing thin gate dielectric layer (16) breakdown by shorting the gate (18) to the silicon substrate (12) by means of a metal layer (24) which will eventually form silicided gate (26) and source/drain (28) interconnections. A sidewall spacer (22) around each gate (18) is necessary to prevent shorting during and after the silicidation process. Suitable metals for the thin metal shorting layer (24) include chemical vapor deposited (CVD) tungsten, titanium, tantalum, molybdenum and platinum. This technique prevents the need for special metal layer deposition or removal steps commonly used in the art to prevent catastrophic gate dielectric (16) breakdown due to high charge build-up on the gate (18).

Description

DIELECTRIC BREAKDOWN PREVENTION TECHNIQUE
Field of the Invention
The invention relates to the construction of metal oxide semiconductor (MOS) integrated circuits, and more particularly relates to methods and apparatus for preventing thin gate dielectric breakdown during the ion implantation step in the manufacture of MOS integrated circuits.
Background of the Invention
In the typical formation of an MOS integrated circuit transistor devices for very large scale integration (VLSI) , a silicon substrate is divided up into areas in which devices are to be built, the areas being separated from each other by dielectric isolation regions. A gate of conductive material is usually electrically isolated from the silicon substrate by a thin layer of dielectric material, generally between 50 and 1000 Angstroms thick.
An example of such a structure is seen in FIG. 1 of the drawings. The MOS semiconductor device under construction is generally referred to as device 10. MOS semiconductor device 10 is positioned on a monocrystalline silicon substrate 12 between two dielectric isolation regions 14. A thin dielectric layer 16 is present upon silicon substrate 12 between the two isolation regions 14. Gate 18, which is typically made out of a conducting material, such as polycrystalline silicon or polysllicon, is positioned on top of the thin dielectric layer 16. Usually, the portions of the thin dielectric layer 16 not immediately under gate 18 which are between the gate 18 and the isolation regions 14 is etched away. As noted earlier, gate 18 is electrically isolated from silicon substrate 12.
During the source/drain ion implantation process, the gate 18 can be charged up to a very high voltage, and a large potential difference can build up between the gate 18 and the silicon substrate 12. This potential difference can lead to gate dielectric breakdown, which is a catastrophic defect that severely limits circuit yield.
One solution to solving this problem involves the deposition of a metal layer 20 as shown in the prior art FIG. 2 in order to minimize the charging of gate 18. Metal layer 20 may be any conductive metal such as aluminum, e.g. Metal layer 20 may be deposited before or after the thin dielectric layer 16 is removed in the future source/drain regions. The metal layer 20 shorts the gate 18 to the silicon substrate 12 or to another grounded surface, such as a clamping ring in the ion implanter and thus helps reduce the charge build-up on the gate 18. This layer 20 can therefore prevent the catastrophic gate dielectric breakdown. The metal layer 20 is subsequently stripped in an etch proces that is selective to silicon and the dielectric material. Typically, the dielectric material is silicon dioxide, Siθ2, often referred to simply as oxide.
Use of a metal layer 20 to prevent the breakdown of the thin gate dielectric 16 has the disadvantages of requiring an° extra metal deposition and an extra etch step to remove it, of course. Further, to ensure that the gate 18 is shorted to the silicon substrate 12, excellent sidewall step coverage of the aluminum metal layer 20 is necessary. Standard sputter deposition processes suffer from poor sidewall step coverage. Typically, the metal must be deposited in a thicker application than usual in order to achieve good sidwall coverage. In turn, metal layer 20 can cause problems with the ion implantation process; for instance, ion scattering and lack of adequate ion penetration can lead to loss of junction depth and doping distribution coritrol. Further, the ion implantation process can drive unwanted metals, such as the aluminum, into the source, drain and gate regions.
Discussions of investigations into the dielectric breakdown problem and the use of an aluminum grounding layer may be found in M. Nakatsuka, et al. "Effects of Thin Conductive Film Mask on Ion Implantation," J. Electrochem. Soc. : Solid-State Science and Technology, Vol. 125, No. 11, Nov. 1978, pp. 1829-1832 and E. B. Spialter, et al. "An Ion Implant Induced Instability Mechanism in CMOS/SOS Device," paper presented at the Reliability Physics Symposium, Las Vegas, April, 1984.
A baseline silicide process conducted after source/drain implants and anneal is described for an NMOS VLSI process by M. E. Alperin, et al. in "Development of the Self-Aligned Titanium Silicide Process for VLSI Applications," IEEE Transactions on Electron Devices, Vol. ED-32, No. 2, February, 1985, pp. 141-149.
Summary of the Invention
Accordingly, it is an object of the present invention to provide a technique for grounding MOS device gates during ion implantation to prevent thin gate dielectric breakdown.
It is an additional object of the invention to provide a thin gate dielectric breakdown prevention method which does not require an extra material deposition or removal step.
Another object of the present invention is to provide a technique for preventing thin gate dielectric breakdown during ion implantation processes that involves the use of metal suicided gates and source/drain regions and the associated advantages of metal silicide layers such as a reduced contact resistance of the interconnect layer to the silicon substrate.
Still another object of the present invention is to provide a thin gate dielectric breakdown prevention process which has excellent sidewall step coverage of a thin layer for shorting the gate to the silicon substrate during ion implantation. .
Yet another object of the present invention is to provide a technique for preventing the breakdown of thin dielectric gate layers which does not involve the risk of driving unwanted metals into the gate and source/drains during the ion implantation step.
In carrying out these and other objects of the present invention, there is provided, in one form, a method for preventing thin gate dielectric breakdown during ion implantation in the fabrication of MOS integrated circuits having siliσided gates, sources and drains, which involves first forming a plurality of dielectric sidewall spacers one each around a plurality of electrically isolated MOS device gates on a silicon substrate and then depositing a layer of metal over the gates, dielectric sidewall spacers and substrate, for shorting the gates to the substrate. Next, the source and drain regions around the gates between the sidewall spacers and the isolation regions are ion implanted through the metal layer. Subsequently, the metal layer in the source, drain and gate regions is reacted with the silicon substrate or the polysilicon of the gate in the presence of heat to form a plurality of metal silicide interconnect layers. Finally, the unreacted portions of the metal layer overlying the dielectric isolation regions and sidewall spacers is stripped off.
Brief Description of the Drawings
FIG. 1 is a cross-sectional illustration of a single MOS semiconductor device under construction after the gate has been formed;
FIG. 2 is a cross-sectional illustration of the MOS - device under construction from FIG. 1 that has had a metal layer deposited over it in accordance with a prior art technique for preventing thin gate dielectric breakdown;
FIG. 3 is a cross-sectional.illustration of the MOS device of FIG. 1 under construction that has had a sidewall spacer formed prior to dielectric layer etch;
FIG. 4 is a cross-sectional ''illustration of the MOS device of FIG. 3 under construction during an ion implantation process after formation of a thin metal protective layer in accordance with the technique of this invention; and
FIG. 5 is a cross-sectional illustration of the MOS device from FIG. 4 in essentially finished formed after fabrication in accordance with the method of the invention. Detailed Description of the Invention
Shown in FIG. 1 is a MOS semiconductor device 10 under construction. Dielectric isolation regions 14 surrounding device 10 have already been formed on and in monocrystalline silicon substrate 12. Thin dielectric layer 16 has also been formed and a gate 18 has been formed upon it. For the purposes of this invention, the thin dielectric layer is defined as between about 50 and 1000 Angstroms thick. As noted before, the dielectric material of which isolation regions 14 and thin layer 16 are made may be, but is not limited to, silicon dioxide, Siθ2- Similarly, gate 18 may be polycrystalline silicon, but is not limited to that material.
Shown in FIG. 2 is the prior art technique of protecting a semiconductor device 10 under construction, which has already been discussed.
Shown in FIG. 3 is the first new step in the method of this invention, which follows FIG. 1 in sequence. A dielectric material is deposited over the entire wafer surface which is in the condition shown in FIG. 1. The dielectric layer is then anisotropically reactive ion or plasma etched to leave a single, continuous sidewall spacer 22 on the sides of the gate. The spacer 22 is necessary and will be used later to prevent shorting of the gate 18 to the substrate 12 during silicidation. The thickness of this .dielectric material will determine the spacer width and is not critical to successful performance of the invention. The optimum width will depend on the device under consideration.
The formation of sidewall spacers such as spacer 22 is well known in the art. The spacers may be made out of any dielectric material that has good sidewall step conformance so that the spacer 22 may be formed. Perfect sidewall step con¬ formance is not required, however. One example, which does not limit the invention herein is CVD silicon dioxide. The sidewall spacer 22 is not limited by its shape or method of formation. Next, the thin dielectric layer 16 between the sidewall spacer 22 and the isolation regions 14 is selectively etched away to give the structure shown in FIG. 3. In actual practice, the thin dielectric layer 16 etch and the etch of the material to form sidewall spacer 22 may conducted at the same time. The combining of these etch steps to reduce the number of process steps suggests that the dielectric material of spacer 22 be the same material as that of thin dielectric layer 16. It is noted that a remaining portion of thin dielectric layer 16 completely underlies gate 18 and sidewall spacers 22.
An important feature of the invention is to deposit the metal that will be used to silicide the source, drain and gate regions before the ion implantation process. Suitable metal layers include, but are not limited to chemical vapor deposited (CVD) tungsten, titanium, molybdenum, tantalum and platinum and their equivalents. Although the invention is not limited hereby, the invention will be further described as if CVD tungsten were used. Although it is known in the art to use metal layers to form source/drain and gate silicide contacts in the presence of sidewall insulators as seen in U.S. Pat. No. 4,384,301, the metal layer has never heretofore been deposited before ion implantation of the source and drain regions and left on as a solid, complete layer for shorting the gate. See also the Alperin article, cited earlier.
Shown in FIG. 4' is the thin CVD tungsten layer or thin gate dielectric breakdown protective layer 24 which has been deposited over the entire surface of the wafer including sidewall spacer 22, gate 18 and isolation regions 14. The thin tungsten metal layer 24 shorts the polysilicon gate 18 to the silicon substrate 12 thereby^ preventing the build-up of charge on gate 18 during the ion implantation process, which is indicated by the downward pointing arrows in FIG. 4. Since the tungsten will eventually be reacted with the silicon in the source, drain and gate regions, the drive-in of tungsten in these regions during the ion implantation step should not be a problem.
If the device is a complementary MOS or CMOS circuit, any suitable masking layer, such as photoresist, can be used to prevent implantation of n-channel devices during p-channel implantations and vice versa. This technique is well known in the construction of CMOS integrated circuits, and thus no change in masking requirements is needed. The actual ion implantation steps do not form a part of this invention and it is believed that any ion implantation method would work with this invention.
After the ion implantation processes are completed, the metal, such as tungsten, is reacted to selectively form metal silicide, in this hypothetical example, Si2, in the source drain and gate regions. As is well known in the art, this reaction typically occurs at 600 to 900°C. Gate interconnect layer 26 and source/drain region interconnect layers 28 are formed by this silicidation reaction. The sidewall spacer 22 prevent the gate 18 from shorting to the substrate 12. The unreacted tungsten metal is finally stripped off with an appropriate chemical that does not etch Siθ2 or the metal silicide. In the case of tungsten, hydrogen peroxide would be a suitable etchant. A standard MOS process flow can then be used to complete the fabrication of the circuit. Of course, source/drain regions 30 must be activated or driven in at some point in the process.
It may be seen from the technique of this invention that
MOS devices that will eventually have metal silicide gate and source/drain interconnections can be effectively protected against catastrophic thin gate dielectric breakdown by the same metal that will be used to silicide the gate and source/drain interconnects. Thus, an additional metal deposition and an additional etch need not be performed. The t metal layer can be thin, as CVD metals conform well around the sidewall spacer 22. Further, the metal silicide layers 26 and
28 are known to be able to reduce the contact resistance of the interconnect layers 26 and 28 to the silicon substrate 12.
This advantage is of particular importance in CMOS circuits and circuits having small contacts or vias. The gate oxide layer 16 integrity will not be degraded with this type of structure.

Claims

Claims
1. A method.for preventing thin gate dielectric breakdown during ion implantation in the fabrication of metal oxide semiconductor (MOS) integrated circuits, comprising: forming a plurality of dielectric sidewall spacers one each around a plurality of electrically isolated MOS device gates on a silicon substrate; depositing a layer of metal over the gates, sidewall spacers and substrate for shorting the gates to the substrate; ion implanting a plurality of source and drain regions around the gates through the metal layer; reacting the metal layer in the source, drain and gate regions with the silicon substrate in the presence of heat to form a plurality of metal silicide layers; and stripping off the unreacted portions of the metal layer.
2. The method of claim 1 in which the metal is selected from the group consisting of tungsten, titanium, tantalum, molybdenum and platinum.
3. The method of claim 1 in which the metal layer is formed by a chemical vapor deposition method.
4. The method of claim 1 in which the metal layer is formed by a sputter deposition method. r
5. In a metal oxide semiconductor (MOS) integrated circuit, devices with silicided gates, sources and drains made by the process comprising: forming a plurality of dielectric sidewall spacers one each around a plurality of electrically isolated MOS device gates on a silicon substrate; depositing a layer of metal over the gates, sidewall spacers and substrate for shorting the gates to the substrate; ion implanting a plurality of source and drain regions around the gates through the metal layer; reacting the metal layer in the source, drain and gate regions with the silicon substrate in the presence of heat to form a plurality of metal silicide layers; and stripping off the unreacted portions of the metal layer.
6. The MOS integrated circuit of claim 5 in which the metal is selected from the group consisting of tungsten, titanium, tantalum, molybdenum and platinum.
7. The MOS integrated circuit of claim 5 in which the metal layer is formed by a chemical vapor deposition method.
8. The MOS integrated circuit of claim 5 in which the metal layer is formed by a sputter deposition method.
9. A method for preventing thin gate dielectric breakdown during ion implantation in the fabrication of metal oxide semiconductor (MOS) integrated circuits, comprising: forming a plurality of silicon device gates upon a thin layer of dielectric material between a plurality of isolation regions of dielectric material formed in an integrated circuit silicon substrate; forming a plurality of dielectric sidewall spacers one each around the device gates; selectively etching away the thin layer of dielectric material between the sidewall spacers and the isolation regions; depositing a layer of metal over the entire surface of the substrate, including gates, sidewall spacers and isolation regions formed thereon; ion implanting a plurality of source and drain regions around the gates between the sidewall spacers and the isolation regions through the metal layer; reacting the metal layer in the source, drain and gate regions with the silicon substrate in the presence of heat to form a plurality of metal silicide interconnect layers; and stripping off the unreacted portions of the metal layer overlying the dielectric isolation regions and sidewall spacers.
10. In a metal oxide semiconductor (MOS) integrated circuit, devices with silicided gates, sources and drains made by the process comprising: forming a plurality of silicon device gates upon a thin layer of dielectric material between a plurality of isolation regions of dielectric material formed in an integrated circuit silicon substrate; forming a plurality of dielectric sidewall spacers one each around the device gates; selectively etching away the thin layer of dielectric material between the sidewall spacers and the isolation regions; depositing a layer of metal over the entire surface of the substrate, including gates, sidewall spacers and isolation regions formed thereon; ion implanting a pluralityOf source and drain regions around the gates between the sidewall spacers and the isolation regions through the metal layer; r reacting the metal layer in the source, drain and gate regions with the silicon substrate in the presence of heat to form a plurality of metal silicide interconnect layers; and stripping off the unreacted portions of the metal layer overlying the dielectric isolation regions and sidewall spacers.
PCT/US1986/001170 1985-08-08 1986-05-30 Dielectric breakdown prevention technique WO1987000967A1 (en)

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Cited By (4)

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US4855247A (en) * 1988-01-19 1989-08-08 Standard Microsystems Corporation Process for fabricating self-aligned silicide lightly doped drain MOS devices
EP0379024A2 (en) * 1989-01-20 1990-07-25 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US5028554A (en) * 1986-07-03 1991-07-02 Oki Electric Industry Co., Ltd. Process of fabricating an MIS FET
US5989964A (en) * 1997-03-17 1999-11-23 Advanced Micro Devices, Inc. Post-spacer LDD implant for shallow LDD transistor

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LAU et al, "Titanium Disilicide self-aligned Source/Drain & Gate Technology" I.E.D.M. Technical Digest, pp 714-717, Dec. 1980 see page 29.5, fifth paragraph *
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028554A (en) * 1986-07-03 1991-07-02 Oki Electric Industry Co., Ltd. Process of fabricating an MIS FET
US4855247A (en) * 1988-01-19 1989-08-08 Standard Microsystems Corporation Process for fabricating self-aligned silicide lightly doped drain MOS devices
EP0379024A2 (en) * 1989-01-20 1990-07-25 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
EP0379024A3 (en) * 1989-01-20 1990-08-29 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US5049514A (en) * 1989-01-20 1991-09-17 Kabushiki Kaisha Toshiba Method of making a MOS device having a polycide gate
US5989964A (en) * 1997-03-17 1999-11-23 Advanced Micro Devices, Inc. Post-spacer LDD implant for shallow LDD transistor

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