WO1987003759A1 - Electronic interface circuit - Google Patents
Electronic interface circuit Download PDFInfo
- Publication number
- WO1987003759A1 WO1987003759A1 PCT/GB1986/000730 GB8600730W WO8703759A1 WO 1987003759 A1 WO1987003759 A1 WO 1987003759A1 GB 8600730 W GB8600730 W GB 8600730W WO 8703759 A1 WO8703759 A1 WO 8703759A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transistor
- circuit
- well
- voltage
- rails
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/003—Changing the DC level
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Definitions
- the present invention concerns electronic interface circuits, in particular interface circuits for coupling electronic devices operating between different supply voltage levels.
- level shift arrangements have been devised to shift logic signal levels so that these signals can be applied to cascoded gates without causing transistor saturation.
- the logic signal is applied to the base of an emitter-follower bipolar transistor and the signal level shifted by means of a diode-resistor levelshift network.
- This level-shift arrangement is connected between standard supply voltage rails and the transistor is not unduly stressed.
- an n-channel 5V CMOS source-follower field-effect transistor and resistor level-shift network can be devised to operate between 0V and +5V voltage supply rails.
- the p-well isolating structure of this transistor would be connected to the more negative rail (0V) and the surrounding n- substrate material would be connected to the more positive rail (+5V).
- the p-well/n- substrate diode interface is at all times reverse biassed. It is a problem, however, that such an arrangement would not operate satisfactorily when connected between the +5V and -5V voltage supply rails of a differential power supply. Disclosure of the Invention The present invention is intended to provide an electronic interface circuit to enable the coupling of electronic devices operating between different supply voltage levels.
- an electronic interface circuit connected between first and second supply voltage rails to enable signal coupling to an electronic device operable between a third supply voltage rail, corresponding to an intermediate voltage, and the second supply voltage rail
- this circuit comprising:- a field-effect transistor, of the type including an isolating well adjacent to the source and drain thereof this well being disposed between these and the transistor substrate, the gate of this transistor to serve as input terminal; and, a level-shift network, a junction thereof to serve as output terminal; wherein, the transistor well and the adjacent transistor substrate are connected in common and to an appropriate one of the supply rails such that when current flow between the source and drain is inhibited, current flows from the well into the level-shift network.
- the level-shift network aforementioned may comprise a resistor voltage divider. Alternatively, it may comprise a resistor and series connected current source.
- the field-effect transistor aforementioned may be of CMOS, NMOS, Schottky MESFET or JFET types. By way of particular example, and to provide coupling between a device operable between OV and +5V supply voltage rails and a device operable between -5V and 0V supply voltage rails, this transistor may be of the n-channel, p-well 5V CMOS type, the p-well and substrate of which are connected to the 0V supply voltage rail.
- Figure 2 is a circuit diagram of an interface circuit, a variant of the circuit of Figure 1 above;
- Figure 3 is a circuit diagram of an interfaced inverter circuit;
- Figure 4 is a cross-section drawing of an integrated circuit implimentation of the circuit of Figure 3 above;
- Figure 5 is a block circuit diagram to show digital to analogue converter input interfacing; and, Figure 6 is a block circuit diagram of an alternative device/interface arrangement for coupling 5V to 3V CMOS devices. Description of Preferred Embodiments
- an interface circuit 1 is shown and is provided to afford coupling between a first electronic device 3 (operable between the first and third rails. V CC and V DD respectively of a voltage supply (not shown)), and, a second electronic device 5 (operable between the third and second rails, V DD and V SS respectively, of the voltage supply).
- the interface circuit 1 is connected between the first and third voltage rails, V CC and V SS respectively and is comprised of a field-effect transistor 7 and a series connected levelshift network 9.
- the transistor 7 is an n-channel, p-well CMOS transistor and the p-well and transistor substrate are connected to the third voltage rail V DD.
- the p-well/source junction is represented by a diode 11 in this figure.
- the transistor drain is connected to the first voltage rail V CC corresponding here to the most positive voltage
- the end of the level-shift network is connected to the second voltage rail V SS, corresponding here to the most negative voltage.
- the gate I/P of the transistor 7 is connected to the output of the first electronic device 3.
- the level-shift network 9 shown comprises a pair of resistors R 1 , R 2 . The output is taken from a junction O/P between these two resistors R 1 , R 2 to the input terminal of the second electronic device 5.
- symbol A represents the input voltage applied to the gate of the transistor 7
- symbol B represents the voltage at the source of the transistor 7
- symbol C represents the output voltage taken from the level-shift network 9.
- V GS is the n-channel gate-source voltage and V BE is the forward bias diode voltage of the p-well and n + source junction of the transistor 7.
- V DD is the 0V ground rail:- CHIGH ⁇ 0. . . . R 1 ⁇ R 2 ( V CC - V GS)/(- V SS) ... Constraint 1.
- the resistance values R 1 , R 2 of the network resistors would be so chosen for maximum noise immunity.
- the threshold voltage V TH would be chosen as follows:-
- V TH 1 ⁇ 2 ( C HIGH + C LOW)
- FIG. 1 A variant of the interface circuit 1 is shown in Figure 2 where the level shift network comprises a resistor R 1 and, a current source 13 in place of the second resistor R 2 .
- the . interface circuit 1 comprises a transistor T 1 (7) as before and series connected resistors R 1 , R 2 .
- the drain of this transistor T 1 is connected to the first rail V CC (+5V) and the end of the second resistor R 2 is connected to the second rail V SS (-5V).
- the inverter circuit 15 comprises a pair of complimentary transistors, a p-channel transistor T2 and an n-channel transistor T 3 .
- the gates of these two transistors T 2 , T 3 are connected to the output junction O/P of the interface circuit 1 and their drains are connected to a common output node 17.
- the sources of the two transistors T 2 , T 3 are connected to the third supply rail V DD (0V) and to the second supply rail V SS (-5V), respectively.
- Figure 4 an n-type silicon substrate integrated circuit implimentation of this circuit ( Figure 3) is shown.
- the source and drain regions of transistors T 1 and T 3 are of n + doped material and are isolated from the n-/n + substrate 19 each by a p-well structure 21, 23.
- the n-/n + substrate 19 and the p-well 21 of the first transistor T 1 have a common connection to the third rail V DD (0V) of the power supply.
- the source of the first transistor T 1 which is operated as a source follower, feeds a pair of resistor R 1 , R 2 connected as in Figure 4 to the second (negative) voltage rail
- V SS (-5V).
- the input to the following circuitry T 2 , T 3 is fed from the junction O/P between these resistors R 1 , R 2 .
- These latter may be polysilicon as shown, or of n + source/drain implants isolated in p-wells as for the transistor T 1 , T 3 .
- the p-well 23 and source of the third transistor T 3 are connected to the second rail V SS, here the most negative rail (-5V), as is conventional practice. It will be recalled that the adjacent substrate 19 is connected to the third rail VSS (0V).
- the device functions as follows. When the input is in the high state, the transistor T 1 is turned on and the upper end of the first resistor R 1 , is pulled up to 5V - V GS, where V GS is the n-channel gate source voltage.
- the resistors R 1 and R 2 act as a voltage divider and so the output voltage is pulled to:- (10V - V GS) R 2 /(R 1 + R 2 ) - 5V
- the source of the first transistor T 1 falls to - V BE, the forward bias diode voltage of the p-well and n + source junction 21 of the first transistor T 1 , and again this voltage is divided down.
Abstract
It is a problem providing coupling between a device (3) that operates between one set of supply voltage levels (say, 0V and +5V) and another device (5) operating between another set of voltage levels, (say, -5V and 0V). In the circuit described (Figure 1) an interface (1) is provided by a source-follower transistor (7) and a series connected level-shift network (9), comprised for example of two resistors (R1, R2). A particular feature of this circuit (1) is that the transistor (7) is of the isolation well type - (e.g. n-channel, p-well CMOS FET), and the well and transistor substrate are connected in common to an appropriate rail (e.g. VDD 0V). When the transistor channel is non-conducting, current is drawn from the well so that source drain stress on the transistor (7) does not become excessive.
Description
ELECTRONIC INTERFACE CIRCUIT Technical Field
The present invention concerns electronic interface circuits, in particular interface circuits for coupling electronic devices operating between different supply voltage levels.
There are applications, such as digital to analogue conversion (DAC), where it would be convenient to operate between differential supply rails eg. ±5 volts. Fieldeffect transistors produced by modern small geometry processes operate typically only up to 5 volts total supply. There is thus a need for an interface circuit that can provide level shift for logic circuitry operating between 0 and 5V and DAC circuitry operating between -5V and 0V, such that no system transistor will operate on more than 5V source drain stress.
Also, as CMOS processes move to even smaller geometries and lower breakdown voltages, it will become desirable to interface chips with a 3 volt maximum supply to 5 volt devices. Background Art
In ECL combinational logic devices, for example, level shift arrangements have been devised to shift logic signal levels so that these signals can be applied to cascoded gates without causing transistor saturation.
In a typical arrangement the logic signal is applied to the base of an emitter-follower bipolar transistor and the signal level shifted by means of a diode-resistor levelshift network. This level-shift arrangement, however, is connected between standard supply voltage rails and the transistor is not unduly stressed.
By analogy, an n-channel 5V CMOS source-follower field-effect transistor and resistor level-shift network can be devised to operate between 0V and +5V voltage supply rails. Conventionally, the p-well isolating structure of this transistor would be connected to the more negative rail (0V) and the surrounding n- substrate material would be connected to the more positive rail (+5V). In this arrangement the p-well/n- substrate diode interface is at all times reverse biassed. It is a problem, however, that such an arrangement would not operate satisfactorily when connected between the +5V and -5V voltage supply rails of a differential power supply. Disclosure of the Invention The present invention is intended to provide an electronic interface circuit to enable the coupling of electronic devices operating between different supply voltage levels.
Accordingly there is provided an electronic interface circuit connected between first and second supply voltage
rails to enable signal coupling to an electronic device operable between a third supply voltage rail, corresponding to an intermediate voltage, and the second supply voltage rail, this circuit comprising:- a field-effect transistor, of the type including an isolating well adjacent to the source and drain thereof this well being disposed between these and the transistor substrate, the gate of this transistor to serve as input terminal; and, a level-shift network, a junction thereof to serve as output terminal; wherein, the transistor well and the adjacent transistor substrate are connected in common and to an appropriate one of the supply rails such that when current flow between the source and drain is inhibited, current flows from the well into the level-shift network.
The level-shift network aforementioned may comprise a resistor voltage divider. Alternatively, it may comprise a resistor and series connected current source. The field-effect transistor aforementioned may be of CMOS, NMOS, Schottky MESFET or JFET types. By way of particular example, and to provide coupling between a device operable between OV and +5V supply voltage rails and a device operable between -5V and 0V supply voltage rails, this transistor may be of the n-channel, p-well
5V CMOS type, the p-well and substrate of which are connected to the 0V supply voltage rail. Brief Introduction of the Drawings
In the drawings accompanying this specification:- Figure 1 is a circuit diagram of an interface circuit, an embodiment of this invention;
Figure 2 is a circuit diagram of an interface circuit, a variant of the circuit of Figure 1 above; Figure 3 is a circuit diagram of an interfaced inverter circuit;
Figure 4 is a cross-section drawing of an integrated circuit implimentation of the circuit of Figure 3 above;
Figure 5 is a block circuit diagram to show digital to analogue converter input interfacing; and, Figure 6 is a block circuit diagram of an alternative device/interface arrangement for coupling 5V to 3V CMOS devices. Description of Preferred Embodiments
So that this invention may be better understood, embodiments will now be described with reference to the accompanying drawings. The description that follows is given by way of example, only.
In Figure 1 an interface circuit 1 is shown and is provided to afford coupling between a first electronic device 3 (operable between the first and third rails.
VCC and VDD respectively of a voltage supply (not shown)), and, a second electronic device 5 (operable between the third and second rails, VDD and VSS respectively, of the voltage supply). The interface circuit 1 is connected between the first and third voltage rails, VCC and VSS respectively and is comprised of a field-effect transistor 7 and a series connected levelshift network 9. In the example illustrated, the transistor 7 is an n-channel, p-well CMOS transistor and the p-well and transistor substrate are connected to the third voltage rail VDD. The p-well/source junction is represented by a diode 11 in this figure. The transistor drain is connected to the first voltage rail VCC corresponding here to the most positive voltage, and the end of the level-shift network is connected to the second voltage rail VSS, corresponding here to the most negative voltage. The gate I/P of the transistor 7 is connected to the output of the first electronic device 3. The level-shift network 9 shown comprises a pair of resistors R1, R2. The output is taken from a junction O/P between these two resistors R1, R2 to the input terminal of the second electronic device 5. In the drawing, symbol A represents the input voltage applied to the gate of the transistor 7, symbol B represents the voltage at the source of the transistor 7 and symbol C
represents the output voltage taken from the level-shift network 9.
In the derivations that follow, VGS is the n-channel gate-source voltage and VBE is the forward bias diode voltage of the p-well and n+ source junction of the transistor 7.
An optimum relationship between values for the resistances R1 , R2 is derived below:-
Consider first, operation of the interface circuit 1 when the applied input signal is at logic high:- A = VCC ... B. = VCC - VGS and CHIGH = VSS + (VCC - VGS - VSS)
ie. CHIGH =
It is requisite that the output voltage CHIGH shall not exceed the intermediate rail voltage VDD:- ie. CHIGH ≤ VDD By way of simplification it is assumed that VDD is the 0V ground rail:- CHIGH ≤ 0. ... R1 ≥ R2 (VCC - VGS)/(-VSS) ... Constraint 1.
Consider now, operation of the interface circuit 1
when the applied input signal is at logic low (VDD = 0V) :- A = 0V :. B = 0V - VBE and CLOW = VSS + (-VBE - VSS) )
ie. CLOW = (R1 VSS - R2 VBE)/(R1 + R2)
The logic swing Δ C in the output signal C is thus given as:-
Thus the maximum swing corresponds to the minimum value of the resistor R1, and this within Constraint 1:-
The resistance values R1, R2 of the network resistors would be so chosen for maximum noise immunity. Where the above described interface 1 is followed by an inverter, the threshold voltage VTH would be chosen as follows:-
VTH = ½ (CHIGH + CLOW)
A variant of the interface circuit 1 is shown in Figure 2 where the level shift network comprises a resistor R1 and, a current source 13 in place of the second resistor R2. With reference now to Figures 3 and 4, an interfaced inverter circuit 15 is shown. In this circuit the . interface circuit 1 comprises a transistor T1 (7) as before and series connected resistors R1, R2. The drain of this transistor T1 is connected to the first rail VCC (+5V) and the end of the second resistor R2 is connected to the second rail VSS (-5V). The inverter circuit 15 comprises a pair of complimentary transistors, a p-channel transistor T2 and an n-channel transistor T3. The gates of these two transistors T2, T3 are connected to the output junction O/P of the interface circuit 1 and their drains are connected to a common output node 17. The sources of the two transistors T2, T3 are connected to the third supply rail VDD (0V) and to the second supply rail VSS (-5V), respectively. In Figure 4 an n-type silicon substrate integrated circuit implimentation of this circuit (Figure 3) is shown. The source and drain regions of transistors T1 and T3 are of n+ doped material and are isolated from the n-/n+ substrate 19 each by a p-well structure 21, 23. The n-/n+ substrate 19 and the p-well 21 of the
first transistor T1 have a common connection to the third rail VDD (0V) of the power supply. The source of the first transistor T1, which is operated as a source follower, feeds a pair of resistor R1, R2 connected as in Figure 4 to the second (negative) voltage rail
VSS (-5V). The input to the following circuitry T2, T3 is fed from the junction O/P between these resistors R1, R2. These latter may be polysilicon as shown, or of n+ source/drain implants isolated in p-wells as for the transistor T1, T3. It is noted that the p-well 23 and source of the third transistor T3 are connected to the second rail VSS, here the most negative rail (-5V), as is conventional practice. It will be recalled that the adjacent substrate 19 is connected to the third rail VSS (0V).
The device functions as follows. When the input is in the high state, the transistor T1 is turned on and the upper end of the first resistor R1, is pulled up to 5V - VGS, where VGS is the n-channel gate source voltage. The resistors R1 and R2 act as a voltage divider and so the output voltage is pulled to:- (10V - VGS) R2/(R1 + R2) - 5V
When on the other hand, the input is in the low state, the source of the first transistor T1 falls to -VBE, the forward bias diode voltage of the p-well and
n+ source junction 21 of the first transistor T1, and again this voltage is divided down.
Proper tolerancing will ensure that the following gate T2/T3 turns on and off satisfactorily. The net effect is that the signal is level shifted without any transistor T1, T2 or T3 being overstressed.
In the foregoing description an n-channel, p-well device was considered. It is noted that the concept is likewise adaptable to p-channel, n-well devices. A particular application is in digital/analogue conversion, where it is advantageous to operate the logic and current switching between 0V and -5V to allow a negative output voltage compliance. This is illustrated in Figure 5. Each input I/P(1), ... I/P(N) to a digital to analogue converter 31, is connected to the output O/P of a corresponding interface circuit 1. For simplification, only one of these interface circuits has been illustrated.
Further applications of this invention are likely to arise for very small geometry processes where the circuit would be operable between, say, OV and 3V but where an interface is needed to accept OV to 5V conventional CMOS inputs. The input structure T1, R1, R2 (Figure 1) or equivalent current source alternatives (Figure 2) will provide an interface without need for process modification
to avoid device overstress. Figure 6 shows just such an application where the interface circuit 1 provides coupling between a standard CMOS device 33 and a low voltage CMOS device 35.
Whilst the invention is most relevant to digital design, it could also handle analogue signal interfacing, However, in this context, it is noted that the dynamic range would be severely restricted.
Claims
1. An electronic interface circuit (1) connected betwee first and second supply voltage rails (VCC, VSS) to enable signal coupling to an electronic device (5; 15; 31; 35) operable between a third supply voltage rail (VDD), corresponding to an intermediate voltage, and the second supply voltage rail (VSS), this circuit comprising:- a field-effect transistor (7), of the type including an isolating well (21) adjacent to the source (s) and drain (d) thereof, this well (21) being disposed between these (s, d) and the transistor substrate (19), the gate (F/P) of this transistor (7) to serve as input terminal (I/P); and, a level-shift network (9), a junction thereof to serve as output terminal (O/P), wherein, the transistor well (21) and the adjacent transistor substrate (19) are connected in common and to an appropriate one of the supply rails (eg. VDD) such that when current flow between the source (s) and drain (d) is impeded, current flows from the well (21) into the level-shift network (9).
2. A circuit (fig. 1) as claimed in claim 1 wherein the level- shift network (9) comprises a resistor voltage divider (R1, R2).
3. A circuit (fig. 2) as claimed in claim 1 wherein the level- shift network (9) comprises a resistor (R1) and a current source (13).
4. A circuit (fig. 3 and fig. 4) as claimed in any one of the preceding claims wherein the first, second and third rails (VCC , VSS, VDD) are rails for positive, negative and intermediate voltage, the transistor (7) is an n-channel, p-well transistor (fig. 4) and, the p-well (21) and substrate (19) are connected in common to the third voltage rail (VDD).
5. A circuit as claimed in claim 4 wherein the transistor (7) is a MOSFET n-channel p-well transistor (fig. 4).
6. A circuit (fig. 5), as claimed in any one of the preceding claims, when used as interface (1) to a digital to analogue converter (31).
7. A digital to analogue converter (fig. 5) including a plurality of input interface circuits (1), each as claimed in claim 1 preceding.
8. A circuit (fig. 6), as claimed in any one of the preceding claims 1 to 3, when used as interface (1) between CMOS devices (33, 35) produced by different geometry CMOS processes.
9. A circuit, as claimed in claim 8, wherein the CMOS devices (33, 35) are of 5v, and 3v process geometry and are connected between 0v and + 5v, 0v and + 3v voltage rails, respectively.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08529893A GB2185648A (en) | 1985-12-04 | 1985-12-04 | Electronic interface circuit |
GB8529893 | 1985-12-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1987003759A1 true WO1987003759A1 (en) | 1987-06-18 |
Family
ID=10589246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB1986/000730 WO1987003759A1 (en) | 1985-12-04 | 1986-12-01 | Electronic interface circuit |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0248834A1 (en) |
JP (1) | JPS63501757A (en) |
GB (1) | GB2185648A (en) |
WO (1) | WO1987003759A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2258964A (en) * | 1991-06-28 | 1993-02-24 | Digital Equipment Corp | A cmos amplifier for logic of a certain voltage which can process logic of a higher voltage |
US6404231B1 (en) * | 1999-02-16 | 2002-06-11 | Ericsson Inc. | Method and apparatus for electrically coupling digital devices |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5132564A (en) * | 1990-07-27 | 1992-07-21 | North American Philips Corp. | Bus driver circuit with low on-chip dissipation and/or pre-biasing of output terminal during live insertion |
ATE322105T1 (en) * | 2000-09-27 | 2006-04-15 | Koninkl Philips Electronics Nv | DIGITAL TO ANALOG CONVERTER |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1300407A (en) * | 1960-07-22 | 1972-12-20 | Ferranti Ltd | Improvements relating to circuit arrangements including insulated-gate field effect transistors |
DE2524001A1 (en) * | 1975-05-30 | 1976-12-02 | Licentia Gmbh | Integrated circuit with MOSTS - has two MOSTS which are connected to common reference voltage wire and to two supply voltage wires |
US4450369A (en) * | 1981-05-07 | 1984-05-22 | Schuermeyer Fritz L | Dynamic MESFET logic with voltage level shift circuit |
US4490632A (en) * | 1981-11-23 | 1984-12-25 | Texas Instruments Incorporated | Noninverting amplifier circuit for one propagation delay complex logic gates |
-
1985
- 1985-12-04 GB GB08529893A patent/GB2185648A/en not_active Withdrawn
-
1986
- 1986-12-01 JP JP50637686A patent/JPS63501757A/en active Pending
- 1986-12-01 WO PCT/GB1986/000730 patent/WO1987003759A1/en not_active Application Discontinuation
- 1986-12-01 EP EP19860906903 patent/EP0248834A1/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1300407A (en) * | 1960-07-22 | 1972-12-20 | Ferranti Ltd | Improvements relating to circuit arrangements including insulated-gate field effect transistors |
DE2524001A1 (en) * | 1975-05-30 | 1976-12-02 | Licentia Gmbh | Integrated circuit with MOSTS - has two MOSTS which are connected to common reference voltage wire and to two supply voltage wires |
US4450369A (en) * | 1981-05-07 | 1984-05-22 | Schuermeyer Fritz L | Dynamic MESFET logic with voltage level shift circuit |
US4490632A (en) * | 1981-11-23 | 1984-12-25 | Texas Instruments Incorporated | Noninverting amplifier circuit for one propagation delay complex logic gates |
Non-Patent Citations (1)
Title |
---|
Electronic Design, Volume 18, No. 12, 7 June 1970, (Rochelle Park, US), SHERWIN: "Build Better Source Followers 10 Ways", see pages 80-84 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2258964A (en) * | 1991-06-28 | 1993-02-24 | Digital Equipment Corp | A cmos amplifier for logic of a certain voltage which can process logic of a higher voltage |
GB2258964B (en) * | 1991-06-28 | 1995-07-05 | Digital Equipment Corp | 5-volt tolerant differential receiver |
US6404231B1 (en) * | 1999-02-16 | 2002-06-11 | Ericsson Inc. | Method and apparatus for electrically coupling digital devices |
Also Published As
Publication number | Publication date |
---|---|
GB8529893D0 (en) | 1986-01-15 |
EP0248834A1 (en) | 1987-12-16 |
JPS63501757A (en) | 1988-07-14 |
GB2185648A (en) | 1987-07-22 |
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