WO1990014629A3 - Parallel multithreaded data processing system - Google Patents

Parallel multithreaded data processing system Download PDF

Info

Publication number
WO1990014629A3
WO1990014629A3 PCT/US1990/002958 US9002958W WO9014629A3 WO 1990014629 A3 WO1990014629 A3 WO 1990014629A3 US 9002958 W US9002958 W US 9002958W WO 9014629 A3 WO9014629 A3 WO 9014629A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
thread
threads
processing system
data processing
Prior art date
Application number
PCT/US1990/002958
Other languages
French (fr)
Other versions
WO1990014629A2 (en
Inventor
Rishiyur S Nikhil
Arvind
Original Assignee
Massachusetts Inst Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/527,122 external-priority patent/US5353418A/en
Application filed by Massachusetts Inst Technology filed Critical Massachusetts Inst Technology
Publication of WO1990014629A2 publication Critical patent/WO1990014629A2/en
Publication of WO1990014629A3 publication Critical patent/WO1990014629A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/448Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4494Execution paradigms, e.g. implementations of programming paradigms data driven

Abstract

A multithreaded parallel data processing system has at least one processing element for processing multiple threads of computation. Threads are described by thread descriptors which are stored while waiting to be processed in a thread descriptor storage. Thread descriptors are comprised of an instruction pointer and a frame pointer. The instruction pointer points to the next instruction to be executed, and the frame pointer points to a frame of memory locations that the next instruction will operate on. Included within the instruction set of the at least one processing element is a load instruction that loads global data into local processing element memory that is performed to two phases: a request phase and a response phase. Also included are instructions to fork a thread into two threads and to join two threads into a single thread.
PCT/US1990/002958 1989-05-26 1990-05-25 Parallel multithreaded data processing system WO1990014629A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US35893789A 1989-05-26 1989-05-26
US358,937 1989-05-26
US07/527,122 US5353418A (en) 1989-05-26 1990-05-21 System storing thread descriptor identifying one of plural threads of computation in storage only when all data for operating on thread is ready and independently of resultant imperative processing of thread
US527,122 1990-05-21

Publications (2)

Publication Number Publication Date
WO1990014629A2 WO1990014629A2 (en) 1990-11-29
WO1990014629A3 true WO1990014629A3 (en) 1991-02-07

Family

ID=27000260

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/002958 WO1990014629A2 (en) 1989-05-26 1990-05-25 Parallel multithreaded data processing system

Country Status (3)

Country Link
US (1) US5499349A (en)
EP (1) EP0473714A1 (en)
WO (1) WO1990014629A2 (en)

Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5812811A (en) * 1995-02-03 1998-09-22 International Business Machines Corporation Executing speculative parallel instructions threads with forking and inter-thread communication
US5710923A (en) * 1995-04-25 1998-01-20 Unisys Corporation Methods and apparatus for exchanging active messages in a parallel processing computer system
US6343309B1 (en) * 1996-09-30 2002-01-29 International Business Machines Corporaton Method and apparatus for parallelizing a graphics pipeline
US5842003A (en) * 1997-03-26 1998-11-24 Unisys Corporation Auxiliary message arbitrator for digital message transfer system in network of hardware modules
US6064818A (en) * 1997-04-10 2000-05-16 International Business Machines Corporation Straight path optimization for compilers
US6182177B1 (en) * 1997-06-13 2001-01-30 Intel Corporation Method and apparatus for maintaining one or more queues of elements such as commands using one or more token queues
US6092155A (en) 1997-07-10 2000-07-18 International Business Machines Corporation Cache coherent network adapter for scalable shared memory processing systems
US6044438A (en) * 1997-07-10 2000-03-28 International Business Machiness Corporation Memory controller for controlling memory accesses across networks in distributed shared memory processing systems
US6105051A (en) * 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6697935B1 (en) * 1997-10-23 2004-02-24 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US6567839B1 (en) 1997-10-23 2003-05-20 International Business Machines Corporation Thread switch control in a multithreaded processor system
US6076157A (en) * 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6061710A (en) * 1997-10-29 2000-05-09 International Business Machines Corporation Multithreaded processor incorporating a thread latch register for interrupt service new pending threads
US6256775B1 (en) 1997-12-11 2001-07-03 International Business Machines Corporation Facilities for detailed software performance analysis in a multithreaded processor
US6018759A (en) * 1997-12-22 2000-01-25 International Business Machines Corporation Thread switch tuning tool for optimal performance in a computer processor
US6434714B1 (en) 1999-02-04 2002-08-13 Sun Microsystems, Inc. Methods, systems, and articles of manufacture for analyzing performance of application programs
US6341338B1 (en) * 1999-02-04 2002-01-22 Sun Microsystems, Inc. Protocol for coordinating the distribution of shared memory
US6378066B1 (en) 1999-02-04 2002-04-23 Sun Microsystems, Inc. Method, apparatus, and article of manufacture for developing and executing data flow programs, and optimizing user input specifications
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6542921B1 (en) * 1999-07-08 2003-04-01 Intel Corporation Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor
US6629236B1 (en) * 1999-11-12 2003-09-30 International Business Machines Corporation Master-slave latch circuit for multithreaded processing
US6889319B1 (en) 1999-12-09 2005-05-03 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
US6496925B1 (en) 1999-12-09 2002-12-17 Intel Corporation Method and apparatus for processing an event occurrence within a multithreaded processor
US6357016B1 (en) 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
US7051329B1 (en) 1999-12-28 2006-05-23 Intel Corporation Method and apparatus for managing resources in a multithreaded processor
US7035989B1 (en) 2000-02-16 2006-04-25 Sun Microsystems, Inc. Adaptive memory allocation
US6732363B1 (en) * 2000-02-28 2004-05-04 Sun Microsystems, Inc. Supporting inter-process communication through a conditional trap instruction
US7856633B1 (en) 2000-03-24 2010-12-21 Intel Corporation LRU cache replacement for a partitioned set associative cache
US7093109B1 (en) * 2000-04-04 2006-08-15 International Business Machines Corporation Network processor which makes thread execution control decisions based on latency event lengths
US6546359B1 (en) 2000-04-24 2003-04-08 Sun Microsystems, Inc. Method and apparatus for multiplexing hardware performance indicators
US6802057B1 (en) 2000-05-03 2004-10-05 Sun Microsystems, Inc. Automatic generation of fortran 90 interfaces to fortran 77 code
US6647546B1 (en) 2000-05-03 2003-11-11 Sun Microsystems, Inc. Avoiding gather and scatter when calling Fortran 77 code from Fortran 90 code
US6986130B1 (en) 2000-07-28 2006-01-10 Sun Microsystems, Inc. Methods and apparatus for compiling computer programs using partial function inlining
US6910107B1 (en) 2000-08-23 2005-06-21 Sun Microsystems, Inc. Method and apparatus for invalidation of data in computer systems
US6957208B1 (en) 2000-10-31 2005-10-18 Sun Microsystems, Inc. Method, apparatus, and article of manufacture for performance analysis using semantic knowledge
US7320065B2 (en) 2001-04-26 2008-01-15 Eleven Engineering Incorporated Multithread embedded processor with input/output capability
US7047395B2 (en) * 2001-11-13 2006-05-16 Intel Corporation Reordering serial data in a system with parallel processing flows
CN1212567C (en) * 2002-03-28 2005-07-27 徐肇昌 Structure and method for software simulation of N+1 parallel program in sequence network
US7200738B2 (en) 2002-04-18 2007-04-03 Micron Technology, Inc. Reducing data hazards in pipelined processors to provide high processor utilization
US8024735B2 (en) * 2002-06-14 2011-09-20 Intel Corporation Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution
US7870553B2 (en) * 2003-08-28 2011-01-11 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
WO2005022384A1 (en) * 2003-08-28 2005-03-10 Mips Technologies, Inc. Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor
US7849297B2 (en) 2003-08-28 2010-12-07 Mips Technologies, Inc. Software emulation of directed exceptions in a multithreading processor
US9032404B2 (en) * 2003-08-28 2015-05-12 Mips Technologies, Inc. Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor
US7836450B2 (en) 2003-08-28 2010-11-16 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US7418585B2 (en) * 2003-08-28 2008-08-26 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US7594089B2 (en) * 2003-08-28 2009-09-22 Mips Technologies, Inc. Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
US7376954B2 (en) * 2003-08-28 2008-05-20 Mips Technologies, Inc. Mechanisms for assuring quality of service for programs executing on a multithreaded processor
US7711931B2 (en) * 2003-08-28 2010-05-04 Mips Technologies, Inc. Synchronized storage providing multiple synchronization semantics
EP1660993B1 (en) * 2003-08-28 2008-11-19 MIPS Technologies, Inc. Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US20050050305A1 (en) * 2003-08-28 2005-03-03 Kissell Kevin D. Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US7840949B2 (en) * 2003-11-03 2010-11-23 Ramal Acquisition Corp. System and method for data transformation using dataflow graphs
US8230423B2 (en) * 2005-04-07 2012-07-24 International Business Machines Corporation Multithreaded processor architecture with operational latency hiding
US20060230409A1 (en) * 2005-04-07 2006-10-12 Matteo Frigo Multithreaded processor architecture with implicit granularity adaptation
EP1783604A3 (en) * 2005-11-07 2007-10-03 Slawomir Adam Janczewski Object-oriented, parallel language, method of programming and multi-processor computer
GB2474521B (en) * 2009-10-19 2014-10-15 Ublox Ag Program flow control
US8230410B2 (en) 2009-10-26 2012-07-24 International Business Machines Corporation Utilizing a bidding model in a microparallel processor architecture to allocate additional registers and execution units for short to intermediate stretches of code identified as opportunities for microparallelization
US9672132B2 (en) * 2009-11-19 2017-06-06 Qualcomm Incorporated Methods and apparatus for measuring performance of a multi-thread processor
US9558048B2 (en) 2011-09-30 2017-01-31 Oracle International Corporation System and method for managing message queues for multinode applications in a transactional middleware machine environment
US9195516B2 (en) 2011-12-01 2015-11-24 International Business Machines Corporation Determining collective barrier operation skew in a parallel computer
US8924763B2 (en) * 2011-12-15 2014-12-30 International Business Machines Corporation Synchronizing compute node time bases in a parallel computer
US9747108B2 (en) * 2015-03-27 2017-08-29 Intel Corporation User-level fork and join processors, methods, systems, and instructions
US20160381050A1 (en) 2015-06-26 2016-12-29 Intel Corporation Processors, methods, systems, and instructions to protect shadow stacks
US10394556B2 (en) 2015-12-20 2019-08-27 Intel Corporation Hardware apparatuses and methods to switch shadow stack pointers
US10430580B2 (en) 2016-02-04 2019-10-01 Intel Corporation Processor extensions to protect stacks during ring transitions

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614745A (en) * 1969-09-15 1971-10-19 Ibm Apparatus and method in a multiple operand stream computing system for identifying the specification of multitasks situations and controlling the execution thereof
US4229790A (en) * 1978-10-16 1980-10-21 Denelcor, Inc. Concurrent task and instruction processor and method
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4530051A (en) * 1982-09-10 1985-07-16 At&T Bell Laboratories Program process execution in a distributed multiprocessor system
DE3751503T2 (en) * 1986-03-26 1996-05-09 Hitachi Ltd Data processor in pipeline structure with the ability to decode and execute multiple instructions in parallel.
US4819155A (en) * 1987-06-01 1989-04-04 Wulf William A Apparatus for reading to and writing from memory streams of data while concurrently executing a plurality of data processing operations
US4943908A (en) * 1987-12-02 1990-07-24 International Business Machines Corporation Multiple branch analyzer for prefetching cache lines
US5050070A (en) * 1988-02-29 1991-09-17 Convex Computer Corporation Multi-processor computer system having self-allocating processors
US5050068A (en) * 1988-10-03 1991-09-17 Duke University Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams
US5241635A (en) * 1988-11-18 1993-08-31 Massachusetts Institute Of Technology Tagged token data processing system with operand matching in activation frames
US5226131A (en) * 1989-12-27 1993-07-06 The United States Of America As Represented By The United States Department Of Energy Sequencing and fan-out mechanism for causing a set of at least two sequential instructions to be performed in a dataflow processing computer

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Computer Architecture Conference Proceedings, Volume 17, No. 3, June 1989, ACM, (Washington, US), R.S. NIKHIL et al.: "Can Dataflow Subsume von Neumann Computing?", pages 262-272 see the whole article *
Conference Proceedings of the 15th Annual International Symposium on Computer Architecture, 30 May - 2 June 1988, Honolulu, Hawaii, IEEE, (US), R.A. IANNUCCI: "Toward a Dataflow/ von Neumann Hybrid Architecture", pages 131-140 see section 2.1, first paragraph; section 3.3; section 3.3.1; figures 8,9 *
Conference Proceedings of the 15th Annual International Symposium on Computer Architecture, 30 May - 2 June 1988, Honolulu, Hawaii, IEEE, (US), R.H. HALSTEAD, Jr. et al.: "MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing", pages 443-451 see figure 6 *
IEEE Transactions on Computers, Volume C-36, No. 12, December 1987, IEEE, (New York, US), R. BUEHRER et al.: "Incorporating Data Flow Ideas Into von Neumann Processors for Parallel Execution", pages 1515-1522 see figures 2,3; page 1517, right-hand column, line 32 - page 1518, right-hand column, line 41 *
Proceedings of the 1988 International Conference on Parallel Processing, 15-19 August 1988, Volume II Software, The Pennsylvania State University Press, (PE, US), B.R. PREISS et al.: "Semi-Static Dataflow", pages 127-134 see section 4.1 *

Also Published As

Publication number Publication date
WO1990014629A2 (en) 1990-11-29
EP0473714A1 (en) 1992-03-11
US5499349A (en) 1996-03-12

Similar Documents

Publication Publication Date Title
WO1990014629A3 (en) Parallel multithreaded data processing system
KR930001086A (en) CPU with integrated multiplication / accumulation unit
EP0377991A3 (en) Data processing systems
JPS56149646A (en) Operation controller
EP0495165A3 (en) Overlapped serialization
EP0284364A3 (en) High speed computer system
CA2000376A1 (en) Vector processor using buffer for preparing vector data
JPS57195397A (en) Locally doubled storage device
JPS5299034A (en) Control system for micro program
JP2839730B2 (en) Emulation device and semiconductor device
JPS5566049A (en) Composite data processing unit and data processing unit
JPS5635254A (en) Processor back-up system
JPS54150049A (en) Pre-fetch order control system
JPS54139445A (en) Composite computer system
Antoshenkov Optimization in Rdb/VMS.
Wen et al. Query optimization techniques of a shared-nothing parallel database system
JPS58197548A (en) Stack control system
JPS6435630A (en) Information processor
JPS57193842A (en) Request conflict detecting system
JPS5447545A (en) Multiple processor system
JP2955710B2 (en) Digital protection relay device
JPS5339032A (en) Branch control system
JPH01307825A (en) System for executing dynamic link through interface module
Pham The experimental migration of a distributed application to a multithreaded environment
JPS6450157A (en) Multi-processor control system

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FR GB IT LU NL SE

AK Designated states

Kind code of ref document: A3

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FR GB IT LU NL SE

WWE Wipo information: entry into national phase

Ref document number: 1990909259

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1990909259

Country of ref document: EP

WWR Wipo information: refused in national office

Ref document number: 1990909259

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1990909259

Country of ref document: EP