WO1991000648A1 - Waveshaping subsystem using converter and delay lines - Google Patents

Waveshaping subsystem using converter and delay lines Download PDF

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Publication number
WO1991000648A1
WO1991000648A1 PCT/US1990/003699 US9003699W WO9100648A1 WO 1991000648 A1 WO1991000648 A1 WO 1991000648A1 US 9003699 W US9003699 W US 9003699W WO 9100648 A1 WO9100648 A1 WO 9100648A1
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WO
WIPO (PCT)
Prior art keywords
voltage
lines
output
circuit
waveform
Prior art date
Application number
PCT/US1990/003699
Other languages
French (fr)
Inventor
Michael D. Smith
Original Assignee
Dallas Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/371,464 external-priority patent/US5200751A/en
Priority claimed from US07/371,465 external-priority patent/US5013932A/en
Application filed by Dallas Semiconductor Corporation filed Critical Dallas Semiconductor Corporation
Publication of WO1991000648A1 publication Critical patent/WO1991000648A1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/028Arrangements specific to the transmitter end
    • H04L25/0286Provision of wave shaping within the driver
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06JHYBRID COMPUTING ARRANGEMENTS
    • G06J1/00Hybrid computing arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03834Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using pulse shaping
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0272Arrangements for coupling to multiple lines, e.g. for differential transmission
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0278Arrangements for impedance matching

Definitions

  • the present invention relates to circuits for shaping waveforms, and to integrated circuits which use such waveform-shaping techniques.
  • the present invention also relates to circuits for translating a digital number into an analog voltage level: such circuits are known as digital to analog converters, or DACs.
  • a variety of architectures are conventionally used for digital-to-analog converters. For example, one commonly used technique is a "current- summing" architecture, wherein current contributions from switchable resistors are summed, and then converted to define an analog output voltage.
  • DACs digital to analog converters
  • the present invention provides a different (and much more versatile) type of programmability. This is particularly advantageous for waveshaping.
  • an integrated circuit digital to analog converter which includes multiple row lines.
  • Each of the row lines is connected to a scaled fraction of a reference voltage, and includes multiple selection gates in series.
  • Each of these selection gates is programmable, to define whether it will respond to the control line to which it is connected.
  • the connections of the row lines to a matrix of busses are also programmable.
  • the selection gates are preferably configured so that, for substantially every normal value of control inputs, multiple result lines will be driven simultaneously.
  • the present invention provides a digital-to-analog converter which allows multiple tap points and multiple programmable output levels which are programmable using the metal mask only.
  • a further set of innovative teachings provides an integrated circuit digital to analog converter, wherein multiple row lines, each connected to a respective reference voltage, are configured so that, for substantially every normal value of control inputs, multiple result lines will be driven simultaneously with different respective voltages; and output selection gates, connected to select one of the result lines for output.
  • the preferred chip embodiment uses this digital-to-analog converter to build a waveform to meet an output template. Since one of several templates may need to be met, depending on load conditions, the digital-to- analog converter needs selectability.
  • the invention provides a multitap, programmable-level digital-to-analog converter using metal mask only to define its characteristics.
  • a very broad class of analog applications require some variable waveshaping capability.
  • One important area is in communications interfaces.
  • the Bell System specification for Tl transmission lines requires that the waveforms of pulse edges have a certain shape at the Bell System interface. (The specified waveform shapes include a certain amount of pre-emphasis, in the form of overshoot on pulse transition edges. This helps to compensate for
  • the customer's Tl transceiver may be separated from the Bell system interface by as little as 0 feet, or as many as 655 feet, of twisted pair line.
  • Tl transceivers for customer use cannot simply generate a single waveform for Tl line drivers, but must be able to generate differing amounts of pre-emphasis, depending on the
  • FIG. 5A shows the standard waveforms for the permissible envelope of Tl pulse shapes (and, overlaid on that, an example of how the pulse shapes used for a short distance
  • connection would be modified for a 300 foot connection or for a 600 foot connection).
  • Figure 5B shows the standard waveforms for the permissible envelope of CEPT pulse shapes.
  • the basic Tl clock period is one over 1.544 MHz, or about 648 nanoseconds.
  • the present invention provides a greatly improved capability in waveform shaping. This is particularly advantageous in Tl interface applications, but is also applicable to a tremendous variety of other applications.
  • an integrated circuit with programmable delay lines is used to implement waveform shaping capability. By using programmable delay lines, an improved time-domain resolution is available which is much less than one clock delay.
  • One advantage of this approach is that the support circuitry is simple. A simple rising edge is all that is required to start the delay line chain, and generate the output waveform. Further, if 1 nsec precision is required, a 1 GHz oscillator is not. A further advantage is that "slow" technologies like CMOS can thus be used to build chips which can precisely synthesize high ⁇ speed and complex waveforms.
  • programming of the delay elements is performed only once, at the initial set-up of the system.
  • the innovative teachings set forth herein can also be applied to systems where it is desired to generate a customized waveform on the fly, or switch between ones of a pre-stored library of customized waveforms.
  • the delay line alterations are performed by laser trimming of capacitors in a delay stage. However, other methods of delay programmation can be used instead.
  • a desired waveform can be tailored very accurately.
  • D/AC digital to analog converter
  • This converter receives control lines from a multi-stage delay line.
  • the delays between the various phases provided from the delay line can either be preset, or may be programmable on the fly.
  • a resistor divider network (or other reference voltage-generating means, such as a capacitor array) is used to generate a set of voltage levels, and an array of transistors is connected so that each of the control lines selects one of the voltage levels for output.
  • the different voltage values are initially maintained constant, but alternatively active devices could be used in analog mode, or to switch resistors in or out of the string, to change the tap voltages on fly.
  • a matrix of switching transistors provides unique advantages of late programmability.
  • Each of the fractional output supply voltage lines is connected through a series of pass transistors, each of which is gated by one of the outputs from the multi-stage delay line taps.
  • Metal options are available to short out each of the pass transistors.
  • metal options can also be used to connect these gated output lines to multiple final output lines.
  • these metal programmation options can be used to provide multiple output waveforms with a precise relative timing.
  • this capability is used to provide fully complementary (mirror-image) waveforms.
  • this capability could also be used to implement more complex functionality.
  • the advantage of metal-level options is that late modification of the circuit's functionality is possible. This is well recognized in the semiconductor industry.
  • Several techniques are available to generate a desired waveform, from diode networks to digital-to-analog converters and oscillator dividers.
  • the disadvantage of an oscillator divider to set the time "pickets" in a waveshaping system is the limited number of time points available: the total number of time points available per period is equal to the oscillator frequency f osc divided by the data rate (1.544 MHz in Tl). Such a system is shown in Figure 4. This limited time-domain resolution means that precise shaping of a high speed waveform is difficult.
  • the present invention permits the divider and oscillator to be replaced with precision delay elements that can be easily programmed.
  • the lowest time resolution which is recognized is 125 nanoseconds. Since the presently preferred embodiment provides time- domain resolution of approximately 1 nanosecond, the capabilities thus provided are far in excess of that required by the Tl standard.
  • the present invention is advantageous for many applications where a complex waveform needs to be reproduced repeatedly. For example, the present invention can be very advantageous for applications such as speech or music synthesis.
  • Figure 1 shows the overall organization of the digital-to-analog converter used in the presently preferred embodiment.
  • Figure 2 shows the organization of the voltage/time array preferably used in the digital-to- analog converter of Figure 1.
  • Figures 3A and 3B are overlays, which show important portions of the layout actually used for the array 100, in the presently preferred embodiment.
  • Figure 4 shows a conventional waveform generation system, controlled by a high-frequency oscillator.
  • Figure 5A shows the permissible envelopes of pulse waveforms at a Tl transmitter. (The overlaid curves show how this envelope must be modified under different load conditions.)
  • Figure 5B shows the permissible envelope of pulse waveforms for CEPT transmission.
  • Figure 6 shows a complete Tl interface, as enabled by the innovative teachings set forth herein.
  • Figure 7 shows the overall architecture of the integrated circuit which, in the preferred embodiment, implements the interface unit 620.
  • Figure 8 shows the circuitry actually used, in the presently preferred embodiment, to provide the timing (control) inputs to the output selection circuitry.
  • Figure 9 shows the circuitry of the delay lines 810, in the presently preferred embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Figure 6 shows a complete Tl interface, as enabled by the innovative teachings set forth herein.
  • Pins TTIP and TRING of a transmit line interface unit 620 is connected through transformer 621 to a twisted pair 622, which sends data out to the telephone company interface.
  • the transformer provides impedance matching and DC isolation.
  • pins RTIP and RRING of a receiver line interface chip 610 are connected, through a transformer 611, to another twisted pair 612, which receives data from the telephone company.
  • a data transceiver unit 630 performs the appropriate data formatting transformations, to link the serial data interfaces of units 610 and 620 to a system backplane connection 631.
  • the system backplane may be a VME bus, or conform to another of the many bus architectures available.
  • a system controller unit 640 controls the data transceiver unit 630 and the line interface chips 610 and 620.
  • a five-wire serial data bus 642 (including data in, data out, interrupt, clock, and address lines) links the controller chip 640 with the data transceiver unit 630.
  • the system controller unit 640 is a DS5000 nonvolatile microcontroller, but of course, a wide variety of other programmable logic could be used instead.
  • the twisted-pair line driven by the transmit interface chip 620 may go through a digital cross connect (commonly referred to as a "DSX") to the channel service unit (often referred to in Tl literature as a CSU). The telephone companies' lines begin at the channel service unit.
  • DSX digital cross connect
  • the transmit interface unit 620 performs waveform synthesis, as will now be described, to meet the Tl specification.
  • Figure 7 shows the overall architecture of the integrated circuit which, in the preferred embodiment, implements this interface unit 620.
  • An input data multiplexer 710 selects between loopback signals LNEG, LPOS, and LCLK, and transmit signals TPOS, TNEG, and TCLK, in accordance with control signals LB and TAIS, to provide data and clock outputs. (These signals are described in greater detail below.)
  • These data and clock outputs are fed, through zero code suppression circuitry 720, to waveshaping circuitry 730.
  • the waveshaping circuitry 730 accordingly generates shaped analog waveforms, as will be described below.
  • the output of the waveshaping circuitry 730 is fed to line driver circuits 740, which provide the inputs TTIP and TRING (which will be connected to transformer 621).
  • FIG. 1 shows a portion of the waveshaping subsystem 730 employed on the transmitter chip of the presently preferred embodiment.
  • the complete subsystem would also include delay line elements, as described below.
  • Four taps are used to generate the waveshape required for Tl transmission. (More taps can easily be designed in, if required.)
  • This embodiment is a double-ended digital-to-analog converter, which can provide exactly matching waveforms at outputs OUTp OS and OUTXJ- DQ .
  • An input voltage V j - ⁇ p (which may be obtained, for example, from an on-chip bandgap voltage reference) is provided as a central input to the voltage/time array 100.
  • This reference voltage V j ⁇ p is also fed through op amps 102 and 104, to generate a greater (maximum) reference voltage
  • the array 100 produces outputs intermediate between V j ⁇ p and GV f tpp on one side (and, on the other side, outputs intermediate between j ⁇ p and LV j ⁇ p), as selected by control inputs to the array (which are not shown).
  • the array 100 produces eight outputs in parallel (CLU, OLD, TLIU, TL1L, TL2U, TL2L, TL3U, and TL3D) for every control input. (Each of these output lines is tied back to j ? through a filtering capacitor 112.) Output multiplexing logic 110 selects which pair of these output lines will provide the voltage levels for the output pair OUTPQS OUTNEG-
  • Timing control signals TCEPT, TTl, TT2, TT3, and TEND control five pairs of switching transistors 114. Signals TCEPT and TEND are used to synthesize CEPT waveforms, while signals TTl, TT2, TT3, and TEND are used for Tl waveforms.
  • Polarity reversal logic 120 (controlled by inputs TXPOS and TXNEG, as clocked through flip-flops 122) selects which one of the selected output pair will be connected to drive OUTp OS , and which one will be connected to drive OUT j Q .
  • Signal TXNEG indicates an inverted mark and signal TXPOS indicates a non-inverted mark.
  • NAND gate 123 will turn on transistors 124 to tie both outputs to V ⁇ p. This polarity reversal is required for AMI formats such as Tl and CEPT, since it guarantees that the same waveform will appear for every mark signal, whether inverted or noninverted.
  • OUTpos and OUT ⁇ in accordance with the signals received from the polarity reversal logic 120.
  • Two slew-rate-limiting capacitors 107 are provided at the final outputs; these also provide frequency compensation for op amps 106 and 108.
  • Figure 8 shows the circuitry actually used, in the presently preferred embodiment, to provide the timing (control) inputs to the voltage/time array 100.
  • An input clock signal, on line 800, is coupled through a D flip- flop 802. (Gate 801 prevents the input clock from being propagated, if a previous clock is still being propagated through delay lines 810.)
  • Delay elements 810A, 810B, and 810C are connected in series. Delay elements 810D and 810E are also connected in series.
  • the signal TCLKSEL is used to deactivate elements 810D-810E for Tl use, or to deactivate 810A-810C for CEPT use.
  • a bias-regulating signal BR, and a trip-point-select signal VTRIP, are connected in common to all of the delay elements 810.
  • each delay element 810 is connected to a respective one- shot circuit 812.
  • one-shot 812 ⁇ also receives the initial clock pulse.
  • Gate 814 combines the outputs of the one-shots, to produce a sequenced clock signal SEQCLK.
  • This sequenced clock signal clocks a counter chain 820, which includes several flip-flops connected in series.
  • This counter chain in the presently preferred embodiment, is somewhat similar to a Johnson counter, but also has similarities to a ring counter.
  • the first clock pulse sets the first flip-flop 822A, and drives its output high.
  • each clock pulse shifts the high-output state to the next flip-flop in the chain, to drive timing signals TTl, TT2, TT3, in succession, until the last stage drives timing signal TEND.
  • Significant control signals are marked onto Figures 5 A and 5B, to show their timing relations.
  • Figure 5A shows (overlaid with the Tl waveform envelope) the timing of the control signals TTl, TT2, TT3, and TEND, which are used, in the preferred embodiment, to generate a Tl waveform using the circuitry of Figure 8.
  • Figure 5B shows (overlaid with the CEPT waveform envelope) the delays used for the control signals TCEPT and TEND, which are used, in the preferred embodiment, to generate a CEPT waveform using the circuitry of Figure 8.
  • Figure 9 shows the circuitry of the delay lines 810, in the presently preferred embodiment.
  • the BR input is a temperature-compensated voltage which sets the drive current level.
  • the BR control voltage is actually mirrored from a transistor which has the same gate length as current sink transistor 902, which is controlled by the BR voltage. In the presently preferred embodiment, the nominal gate length of this device is about 20 microns, but of course this could be widely varied.
  • the current passed by transistor 902 is mirrored again, through transistors 904 and 905, to provide the charging current for the delay stage.
  • This charging current is integrated in capacitor 910.
  • input signal IN goes high (while enable signal E is high)
  • transistor 912 will be turned off.
  • the current passed by transistor 905 will then flow into capacitor 910, and the voltage on node 914 will begin to rise.
  • Comparator 920 compares the voltage on node 914 with the TMTM input. As the capacitor 910 charges, device 924- ⁇ will pass an increasingly more current, and device 924p will pass increasingly less. Whenever the current passed by pull-down devices 92 ⁇ and 926 N exceeds that passed by pull-up devices 924p and 926 p , the voltage of node 922 will begin to drop. This node is connected to a digital output buffer 930.
  • the enable signal E which disables the delay lines, is taken from the TCLKSEL signal or its complement.
  • this signal is provided as a complemented input to delay lines 810D and 810E, but is not complemented at the input to lines 810A, 810B, and 810C.
  • the waveshaping output can be switched between the waveform needed for the Tl standard and the waveform needed for the CEPT standard. More generally, such a configuration with switchable delay lines provides the capability for rapid selection of customized waveforms, even if those waveforms are very different.
  • Figure 2 shows the organization of the voltage/time array 100. Since this is a regular array, only some of the repeating elements are shown. Moreover, it should be noted that this is a programmable array design, and an important aspect of this design is the ease with which certain elements can be changed.
  • a resistor divider 210 is used to quantize the voltage levels. Resistors
  • 210 1? 210 2 , 210 3 , etc. divide down the difference between GV j ⁇ p and p into the desired number of levels.
  • Each of the row lines 220 is connected to one of the taps on the resistor string 210.
  • the first row line 220- ⁇ sees a voltage which is equal to
  • each of the resistors 210 k has the same value. However, of course, this is not by any means a necessary part of the invention.
  • Each of the row lines 220 k includes a series string of transistors M_. __ -
  • control input LEN1 The gate of transistor M- ⁇ j is connected to a control input LEN1
  • the gate of transistor M ⁇ is connected to a control input LEN2, and so forth.
  • the number of control inputs n is arbitrary, and can be readily changed by designers.
  • Programmable metal straps 222 are available to short out any one of the transistors My. In the example of Figure 2, these straps are shown in the first row only. Note that every transistor in the first row is shorted out, except for transistor M 1 2 . Thus, in this example the first row will be conductive if and only if control line LEN2 is driven high.
  • each of the rows 220 is connected to be totally conditional on a single control input.
  • other control strategies can be used instead. If more than one transistor in a row is left operable, the output of that row will be dependent on an AND combination of multiple control inputs.
  • the row lines 220 cross a set of column busses 230.
  • the intersecting row lines 220 and column busses 230 are not automatically connected: a connection is formed only where a strap 232 of programmable metal is formed. Again, an example of such a connection is shown only in row 1: the output of the first row 220 j is connected, through the second column buss 220, to. the second result line TL2U.
  • Each of the result lines 240 is connected to one of the column busses. Thus, there need to be at least as many column busses as result lines. However, optionally, there may be more column busses than result lines, which can be advantageous as described below.
  • the column busses 230 do not connect the top and bottom halves of the array 100. However, this could be done in alternative embodiments, to provide greater resolution at voltages close to Vppp- In a further alternative embodiment, some or all of the column lines 230 can be extended to provide the outputs of the array 100, without using separate result lines 240. However, this is not preferred.
  • each half of the array 100 includes 100 row lines, 6 series transistors on each row line, 8 column busses, and four output lines.
  • these numbers can readily be varied.
  • Figure 2 shows cell Row 1 programmed for the first tap point to connect to TL2U when LEN2 goes high; no other logic level will connect TL2U to this tap point. Should the user desire to modify TL2 to tap no. 3 when LEN2 is selected, a simple metal-mask modification will accomplish this.
  • Figures 3A and 3B are overlays which show important portions of the layout actually used for the array 100, in the presently preferred embodiment.
  • Figure 3A shows the metal layer.
  • Figure 3B shows the poly (i.e. polysilicon) layer 304, active area 302, and contacts 306.
  • active refers to locations where the thick field oxide has been cleared. Thus, a MOS transistor will occur wherever poly crosses active. See Meade & Conway's Introduction to VLSI Systems, which is hereby incorporated by reference.)
  • Each of the many small squares shown in Figure 3B is a contact. Each contact location will connect the metal layer to polysilicon (if polysilicon is under the contact) or else to substrate.
  • the portion shown in Figures 3A and 3B includes 6 rows and 6 columns of cells, and eight of the column lines 230. However, the array structure shown can very easily be repeated, simply by replicating elements, to vary these numbers as desired. Note that the channel locations of transistors M , M 12 , and M 21 are shown in both Figures 3A and 3B, to help show the overlay of these Figures, even though the actual transistor structure is defined by the structure shown in Figure 3B and not by that shown in Figure 3A
  • the resistor string 210 is provided by an extended portion of the active area, in the presently preferred embodiment.
  • the active area provides a sheet resistance, in the preferred embodiment, which is large enough that resistor 222 will not overload the drive capability of the op amps which provide the greater reference voltage GV ⁇ (Of course, as will obvious to those skilled in the art of IC design, the resistor string 210 could alternatively be realized using polysilicon resistors.) Note that, in the example shown, only one of the rows has been programmed: in Figure 3A, metal straps 222 will short out transistors M 51 , M 59 , M 53 , M 54 , and M 56 , so that transistor M 55 is the only active device left operational in this row.
  • Jumper 232 connects this row to column line 230 .
  • the effect of the metal options shown on the fifth row is that column line 230 4 will be connected to the divided-down voltage at the start of this row if control signal MAG5 is high.
  • polysilicon links 310 permit easy selection of the connections of the column lines 230: each of the left link portions 310A is connected to the end of a row 220, and each of the right link portions 310B is connected to the end of another row 220 to the right of the array portion shown. (The whole structure shown is preferably replicated in mirror image to the right of the of the structure shown, starting with another resistor string 210.) On each of the links 310, four contacts are brought up to four tabs (in the metal level).
  • Each of these tabs can be connected to either or both of two column lines 230.
  • these metal tabs allow designers to have easy access (by routing lines in the metal level) to the column lines 230 j , 230 2 , et It may also be advantageous, for reasons of space compaction, to use further right-left replication (in the orientation shown) to provide additional subarrays, which can be connected together electrically to act as if they were a single larger array.
  • the straps and jumpers 222 and 232 represent modifications of the initial pattern. That is, when a designer calls up a metal layer pattern for modification, no jumpers 222 would (typically) be present to short out transistors, and no straps 232 would connect a link 310A or 310B to any of the column lines 230. The designer can then modify the initial pattern as desired. (Of course, in practice it is also possible, and likely to become increasingly common, to do such mask modification in software, so that the services of an experienced designer are not needed.)
  • each target waveform can be scaled to a maximum value of unity, since scaling can be accomplished by output buffer stages.
  • the target waveform envelopes will be defined by other considerations, e ⁇ by interface standards (in communications or comparable applications), or to provide a maximal basis in a parametric model of perception (in speech synthesis, music synthesis, or comparable applications), or simply by the inputs of a customer or another design group. 2.
  • the designer picks a piecewise-linear approximation to the target waveform, so that the target waveform is approximated as a sequence of time segments, and, at each segment, the output is a constant voltage, or a constant slew rate, or an asymptotic approach to a constant voltage. (For simplicity, it is most preferable that the approximation use a sequence of constant voltages.)
  • the output values of successive segments may be different (but the resulting waveform will have a maximum slew rate defined by the electrical characteristics of the circuit).
  • the designer then estimates the resultant waveform which occurs when the semi-custom analog circuit according to the present invention is programmed to synthesize a waveform with voltage-of-time dependency in accordance with the approximation of the preceding step.
  • steps 2-3 are iterated.
  • the designer may then further iterate steps 2-4, attempting to reduce the complexity of the approximation of step 2, without unacceptably degrading the goodness of fit.
  • step 7 The designer then attempts to condense the parameter sets of step 6. For example, if two different target waveforms use nearly the same voltage for respective parts of their respective delays, the designer may be able to use exactly the same voltage for these two instances, which would reduce the number of taps required in the resistor string (or other voltage source). Optimization of this type requires iteration of steps 1-7.
  • connection options for the integrated circuit in conventional fashion, if the numbers of control lines, different time delays, and output voltage levels do not exceed the capability of the resistor string.
  • the transmit line interface chip 620 interfaces user equipment to North American (Tl-1.544 MHz) and European (CEPT-2.048 MHz) primary rate communications networks.
  • the device is compatible with all types of twisted pair and coax cable found in such networks.
  • On-chip components include: programmable waveshaping circuitry, line drivers, remote loopback and zero suppression logic.
  • a line-coupling transformer is the only external component required.
  • Short loop (DSX-1,0 to 655 feet) and long loop (CSU; 0 db, -7.5 db and -15 db) pulse templates found in Tl applications are supported.
  • Appropriate CCl ' lT Red Book recommendations are met in the CEPT mode.
  • Application areas include digital-to-analog converters, CSU, CPE, channel banks and PABX to computer interfaces such as DMI and CPI.
  • This embodiment also supports ISDN-PRI (primary rate interface) specifications.
  • PIN DESCRIPTION IN TYPE DESCRIPTION TAIS I Transmit Alarm Indication Signal.
  • ZCSEN I Zero Code Suppression Enable.
  • B8ZS or HDB3 encoder enabled.
  • TCLKSEL I Transmit Clock Select. Tie to VSS for 1.544 MHz
  • Input Data Modes Input data is sampled on the falling edges of
  • TCLK and LCLK may be bipolar (dual rail) or unipolar (single rail, NRZ).
  • TPOS, TNEG and TCLK are the data and clock inputs when
  • TPOS and TNEG must be tied together in NRZ applications.
  • the device supports Tl short loop (DSX-1; 0 to 655 feet), Tl long loop (CSU; 0 db, -7.5 db and -15 db) and CEPT (CCITT Red Book G.703) pulse template requirements.
  • On-chip laser trimmed delay lines clocked by either TCLK or LCLK control a precision digital-to analog converter to build the desired waveforms which are buffered differentially by the line drivers.
  • the line coupling transformer also contributes to the pulse shape seen at the cross-connect point; using the transformers specified in Table 4 ensures that the measured waveform meets DSX-1 and/or CSU template requirements. Transformers are 1:1.
  • the waveshaping circuitry does not contribute significantly to output jitter. Output jitter will be dominated by the jitter on TCLK or LCLK.
  • TCLK and LCLK need only be accurate in frequency, not duty cycles.
  • TTIP and TRING traces should be minimized and isolated form neighboring interconnect.
  • the device will enter a standby mode when the input data is all "zeros". This disables the output drivers and reduces power consumption significantly.
  • FAULT PROTECTION The line drivers are fault protected and will withstand a shorted transformer secondary (or primary) without damage.
  • Inputs MTIP and MRING are normally tied to TTIP and TRING to provide fault monitoring capability.
  • Output LF* will transition low if 192
  • TCLK cycles occur without a "one” occurring at MTIP or MRING.
  • LF* will tristate on the next "one” occurrence or two TCLK periods later, whichever is greater.
  • the "one" threshold of MTIP and MRING varies with the line type selected at LENO, LENl and LEN2. This insures detection of the lowest level 0 to 1 transition (-15 dB buildout) as it occurs on TTIP and TRING.
  • MTIP and MRING may be tied to neighboring device's TTIP and TRING outputs to provide superior fault monitoring.
  • TCLKSEL 1 and LENO, LENl and LEN2 are at any state except all zeros.
  • the converter architecture provided by the present invention can provide normal digital-to-analog converter functionality. For example, by using a ladder of 2 n equal resistors, an n-bit digital-to-analog converter can be directly configured. By using resistors scaled in powers of two, and adding a shunting transistor in parallel with each resistor, a wider-range digital-to-analog converter can be configured.
  • control inputs LENl etc. are used to select the voltage magnitudes coming out of the voltage/time array 100, and the timing control signals TTl etc. are used to select the sequence of these magnitudes to form the desired waveform.
  • the sequence control can be performed by using the array inputs LENl etc.
  • switching logic is also used to switch output-loading capacitors in or out, to provide variable slew rate control on the outputs.
  • This capability permits a user to more easily match a complex target waveform specification where it may be necessary to provide controlled rates of voltage change. (By comparison, the presently preferred embodiment simply uses capacitors on the output line to limit the maximum slew rate. Instead, this alternative embodiment would permit the maximum slew rate to be varied dynamically.
  • each of the units 110, 120, 130, and 140 is built on a separate integrated circuit, but alternatively some of these units could be combined.
  • the delay line blocks can be modified so that their delay is not constant.
  • such a circuit can be configured to (for example) provide delay for a predetermined percentage of the clock period (as long as the clock frequency is within a permissible range).
  • alternative versions of the voltage/time array also permit the tap voltages of the resistor string 210 to be varied. This can be done in several ways. In one class of alternative embodiments, this is done by configuring the jumpers 232 so that, in some states of the control logic, two of the row lines would both be connected to a common isolated column buss.
  • the second transistors M 22 and M 3 -* > in the second and third row lines are not shunted by straps 222, and all other transistors on these two row lines are shunted; the second and third row lines 220 2 and 220 3 are both connected, through respective jumpers 230, to a dummy column buss
  • the output-switching logic can also be used to disable outputs which (under some control states) may be in use as intermediate nodes, to change the total value R S M of the resistor string.
  • Such changes in scaling can also be accomplished by switching trim resistors in or out of resistors R j - R 4 . However, this would not be as suitable for rapid switching, due to the need for the amplifiers to settle.
  • a further option is switching additional series resistors in or out of the resistor chain 210, but this is even less desirable, due to the resulting layout complexities.
  • a further advantage of the disclosed architecture is that changes in the sequencing of output levels can easily be accomplished by programmation changes in the array 100. Thus, for example, even if the timing control signals TTl etc. are generated elsewhere, sequencing changes can readily be made in the time/voltage array 100, by changing the connections of the magnitude control inputs LENl etc. This capability gives the designer additional flexibility.
  • the innovative architecture is highly modular and expandable: As many sequencing transistors as desired can be added into a row; large numbers of scaled voltages can be used if desired; the number of column busses can be increased if desired; and the number of result lines can also readily be increased.
  • some ANDing logic could be added, to steal phases from overlaps. For example, suppose that row hne ROWl is gated only by control signal LEN4, and another row line ROW2 is gated only by control signal LEN5. If control signals LEN4 and LEN5 are sequential phase signals which overlap for part (but not all) of their durations, then an intermediate phase can be created by defining another row line (for example, ROW3) to be gated by both LEN4 and LEN5. In this case, it may be desirable to define some of the control lines as complementary.
  • any problem of collision can be avoided if row line ROWl is gated both by control signal LEN4 and also by another signal LEN5* which is the complement of LEN5, and if row line ROW2 is similarly gated by LEN5 and LEN4*.
  • the presently preferred embodiment provides a digital-to-analog converter which is fully double-ended - e. which provides complementary waveforms on a pair of output lines - but the innovative teachings can readily be adapted to a single-ended design instead.
  • the use of the double- ended digital-to-analog converter architecture is particularly advantageous for a Tl transmitter, since it means that exactly symmetrical waveforms can be produced, regardless of whether the Mark signal is inverted or not.
  • This very flexible architecture can be further modified, if desired, to make it more like a programmable logic array, by adding additional gates and interconnects to the topology of the row lines, and thereby introducing additional features of combinatorial or sequential digital or analog functions.
  • the innovative ideas set forth above could also be adapted to use other programmation methods.
  • the transistors can be designed as EPROM- like or EEPROM-like devices, where the transistor's threshold voltage is shifted by storing charge on a floating gate.
  • the programmation can also (less preferably) be performed using distributed fuses or antifuses, or using battery-backed static gates. (However, these alternative approaches tend to place more burden on the interconnect density, and are therefore less preferable.)

Abstract

A waveform generating circuit, wherein a master clock signal is fed into a tapped string of adjustable delay lines, (810A-810G in Fig. 8) and the tapped delay outputs are used to control selection of scaled voltage fractions for output. The use of adjustable delay lines (810A-810G in Fig. 8) means that very high-domain resolution can be achieved, simply by making a small adjustment to the value of a trimmable capacitor. This structure provides a programmable time/voltage array (100 in Fig. 1), and the programming of this array determines which of the possible reference voltages will be enabled by which of the control inputs. Another set of programmable options, in an output connection matrix, determines which of the internal voltage lines will be connected to which output lines. After the output connection matrix, output selection logic is used to determine which class of output levels are to be used. The output selection logic also preferably includes polarity-reversal gates so that the polarity of a bipolar output can be reversed. This structure is advantageously applied to a novel digital to analog converter.

Description

WAVESHAPING SUBSYSTEM
USING CONVERTER AND
DELAY LINES
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to circuits for shaping waveforms, and to integrated circuits which use such waveform-shaping techniques. In particular, the present invention also relates to circuits for translating a digital number into an analog voltage level: such circuits are known as digital to analog converters, or DACs.
The two chief variables in digital to analog converters are resolution and speed. For example, a converter which can operate at a data rate of 30 MHz will be more expensive than a converter which can only operate at 10 MHz (if their resolutions are equal); and a converter with 12 bits of resolution will be more expensive than one with only 10 bits of resolution (if their other parameters are the same). A variety of architectures are conventionally used for digital-to-analog converters. For example, one commonly used technique is a "current- summing" architecture, wherein current contributions from switchable resistors are summed, and then converted to define an analog output voltage. (In the "R/2R" versions of this architecture, the switchable resistors are not simply switched in or out, but instead each switch selects between a resistor and another resistor of twice the value.) Another general class of architectures use switched-capacitor techniques. A good general discussion of converters may be found in P. Allen and D. Holberg, Analog Circuit Design (1987)(which is hereby incorporated by reference). A description of a conventional CMOS converter may be found in Cecil, "A CMOS 10-Bit D/A Converter," which appeared at page 196 of the 1974 ISSCC Digest, and which is hereby incorporated by reference.
Conventionally, digital to analog converter architectures and analog to digital converter architectures have had a very close relation. Not only are the system applications often similar or identical, but many of the same circuit techniques are actually used. This overlap may have constrained the evolution of digital-to-analog converter design: the present application provides an architecture for digital to analog converters which is not similar to analog to digital architectures. This unusual architecture has substantial advantages over normal digital to analog converters, particularly in applications where waveform shaping is required.
Several digital to analog converters (DACs) are in existence that allow programmable output levels through the use of amplifiers or similar techniques. However, the present invention provides a different (and much more versatile) type of programmability. This is particularly advantageous for waveshaping.
Among the innovative teachings set forth herein is an integrated circuit digital to analog converter, which includes multiple row lines. Each of the row lines is connected to a scaled fraction of a reference voltage, and includes multiple selection gates in series. Each of these selection gates is programmable, to define whether it will respond to the control line to which it is connected. The connections of the row lines to a matrix of busses are also programmable. The selection gates are preferably configured so that, for substantially every normal value of control inputs, multiple result lines will be driven simultaneously. Thus, the present invention provides a digital-to-analog converter which allows multiple tap points and multiple programmable output levels which are programmable using the metal mask only. A further set of innovative teachings provides an integrated circuit digital to analog converter, wherein multiple row lines, each connected to a respective reference voltage, are configured so that, for substantially every normal value of control inputs, multiple result lines will be driven simultaneously with different respective voltages; and output selection gates, connected to select one of the result lines for output.
These innovative teachings result in tremendous design flexibility, with many options available. One important resulting advantage is quick turnaround for program changes, since the metal definition is one of the last steps in the process of manufacturing silicon. The preferred chip embodiment uses this digital-to-analog converter to build a waveform to meet an output template. Since one of several templates may need to be met, depending on load conditions, the digital-to- analog converter needs selectability.
It should also be noted that, during the design of partly-customized analog integrated circuits for waveform synthesis, extensive modelling may often be required to define the templates precisely. In some cases, experimental test results may suggest modifications quite late in the design process. For such applications, the programmability provided by the present invention is highly advantageous. The invention provides a multitap, programmable-level digital-to-analog converter using metal mask only to define its characteristics.
A very broad class of analog applications require some variable waveshaping capability. One important area is in communications interfaces. An important example, within this area, is the Tl specification, which is very commonly used for telephone line interfaces. The Bell System specification for Tl transmission lines requires that the waveforms of pulse edges have a certain shape at the Bell System interface. (The specified waveform shapes include a certain amount of pre-emphasis, in the form of overshoot on pulse transition edges. This helps to compensate for
5 frequency-dependent attenuation later in transmission.) In a Short Loop interface (which is very widely used to interface customer equipment to the telephone network) the customer's Tl transceiver may be separated from the Bell system interface by as little as 0 feet, or as many as 655 feet, of twisted pair line.
10 The attenuation and shape of the data signals will therefore be strongly affected by the length of line used, and by the characteristics of the transformer used at the output. Therefore, Tl transceivers for customer use cannot simply generate a single waveform for Tl line drivers, but must be able to generate differing amounts of pre-emphasis, depending on the
15 length of twisted pair used in any particular installation.
This variable pre-emphasis must be achieved within a waveform template which is reasonably complex. Figure 5A shows the standard waveforms for the permissible envelope of Tl pulse shapes (and, overlaid on that, an example of how the pulse shapes used for a short distance
20 connection would be modified for a 300 foot connection or for a 600 foot connection). (Similarly, Figure 5B shows the standard waveforms for the permissible envelope of CEPT pulse shapes.)
The conventional way to implement this variable pre-emphasis has been to use an oscillator which runs at a multiple of the Tl frequency, and
25 to use this higher-frequency signal to control the times at which different output voltages at different subperiods of the basic Tl clock are connected to the output. (The basic Tl clock period is one over 1.544 MHz, or about 648 nanoseconds.) However, this approach has inherent limitations on its time-domain resolution. The present invention provides a greatly improved capability in waveform shaping. This is particularly advantageous in Tl interface applications, but is also applicable to a tremendous variety of other applications. In the presently preferred embodiment, an integrated circuit with programmable delay lines is used to implement waveform shaping capability. By using programmable delay lines, an improved time-domain resolution is available which is much less than one clock delay.
One advantage of this approach is that the support circuitry is simple. A simple rising edge is all that is required to start the delay line chain, and generate the output waveform. Further, if 1 nsec precision is required, a 1 GHz oscillator is not. A further advantage is that "slow" technologies like CMOS can thus be used to build chips which can precisely synthesize high¬ speed and complex waveforms. In the presently preferred embodiment, programming of the delay elements is performed only once, at the initial set-up of the system. However, of course, the innovative teachings set forth herein can also be applied to systems where it is desired to generate a customized waveform on the fly, or switch between ones of a pre-stored library of customized waveforms. In the presently preferred embodiment, the delay line alterations are performed by laser trimming of capacitors in a delay stage. However, other methods of delay programmation can be used instead.
By using the outputs of a programmable multi-stage delay line to drive selection gates which are connected to pass various outputs of a voltage- divider network, a desired waveform can be tailored very accurately.
It is most preferable, where a broad temperature range must be endured, to use delay stages which are as nearly equal as possible. (Otherwise, separate temperature compensation might be required for each stage.) However, where broad temperature range is not an absolutely paramount consideration, the unequal delays which are inherently available with these innovative teachings may be quite advantageous.
An innovative teaching set forth in the present application is a digital to analog converter (D/AC) which is metal-programmable to achieve a desired output waveform. This converter receives control lines from a multi-stage delay line. The delays between the various phases provided from the delay line can either be preset, or may be programmable on the fly. A resistor divider network (or other reference voltage-generating means, such as a capacitor array) is used to generate a set of voltage levels, and an array of transistors is connected so that each of the control lines selects one of the voltage levels for output.
Again, in the presently preferred embodiment, the different voltage values are initially maintained constant, but alternatively active devices could be used in analog mode, or to switch resistors in or out of the string, to change the tap voltages on fly.
In the presently preferred embodiment, a matrix of switching transistors provides unique advantages of late programmability. Each of the fractional output supply voltage lines is connected through a series of pass transistors, each of which is gated by one of the outputs from the multi-stage delay line taps. Metal options are available to short out each of the pass transistors.
Moreover, metal options can also be used to connect these gated output lines to multiple final output lines. Thus, these metal programmation options can be used to provide multiple output waveforms with a precise relative timing. In the presently preferred embodiment, this capability is used to provide fully complementary (mirror-image) waveforms. However, of course, this capability could also be used to implement more complex functionality.
The advantage of metal-level options is that late modification of the circuit's functionality is possible. This is well recognized in the semiconductor industry. Several techniques are available to generate a desired waveform, from diode networks to digital-to-analog converters and oscillator dividers. The disadvantage of an oscillator divider to set the time "pickets" in a waveshaping system is the limited number of time points available: the total number of time points available per period is equal to the oscillator frequency fosc divided by the data rate (1.544 MHz in Tl). Such a system is shown in Figure 4. This limited time-domain resolution means that precise shaping of a high speed waveform is difficult.
The present invention permits the divider and oscillator to be replaced with precision delay elements that can be easily programmed.
In the Tl standard, the lowest time resolution which is recognized is 125 nanoseconds. Since the presently preferred embodiment provides time- domain resolution of approximately 1 nanosecond, the capabilities thus provided are far in excess of that required by the Tl standard. The present invention is advantageous for many applications where a complex waveform needs to be reproduced repeatedly. For example, the present invention can be very advantageous for applications such as speech or music synthesis.
Many uses of a digital-to-analog converter are driven by an end requirement of shaping waveforms, and the instantaneous conversion of bits to voltages is merely a means to that end. Thus, the innovative circuits and architectures taught by the present invention provides an architecture which departs significantly from the normal ways of characterizing the performance of digital-to-analog converters, but which in many cases will be much more advantageous to users than a conventional digital-to-analog converter would be.
Note that a tapped delay chain (including adjustable delay elements) has been used to control sampling times for capturing high-speed analog signals. See U.S. Patent 4,763,105 to Jenq (which is hereby incorporated by reference). However, this patent is primarily directed to high-speed analog-to-digital conversion (using low-speed sampling at successive times), and does not appear to suggest any relevance to digital-to-analog conversion or waveshaping.
BRIEF DESCRIPTION OF THE DRAWING
The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:
Figure 1 shows the overall organization of the digital-to-analog converter used in the presently preferred embodiment. Figure 2 shows the organization of the voltage/time array preferably used in the digital-to- analog converter of Figure 1. Figures 3A and 3B are overlays, which show important portions of the layout actually used for the array 100, in the presently preferred embodiment.
Figure 4 shows a conventional waveform generation system, controlled by a high-frequency oscillator.
Figure 5A shows the permissible envelopes of pulse waveforms at a Tl transmitter. (The overlaid curves show how this envelope must be modified under different load conditions.) Figure 5B shows the permissible envelope of pulse waveforms for CEPT transmission.
Figure 6 shows a complete Tl interface, as enabled by the innovative teachings set forth herein. Figure 7 shows the overall architecture of the integrated circuit which, in the preferred embodiment, implements the interface unit 620.
Figure 8 shows the circuitry actually used, in the presently preferred embodiment, to provide the timing (control) inputs to the output selection circuitry. Figure 9 shows the circuitry of the delay lines 810, in the presently preferred embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS
The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment, wherein these innovative teachings are advantageously applied to the particular problems of a Tl transmit interface unit. However, it should be understood that this embodiment is only one example of the many ad¬ vantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
Figure 6 shows a complete Tl interface, as enabled by the innovative teachings set forth herein. Pins TTIP and TRING of a transmit line interface unit 620 is connected through transformer 621 to a twisted pair 622, which sends data out to the telephone company interface. (The transformer provides impedance matching and DC isolation.) Similarly, pins RTIP and RRING of a receiver line interface chip 610 are connected, through a transformer 611, to another twisted pair 612, which receives data from the telephone company. A data transceiver unit 630 performs the appropriate data formatting transformations, to link the serial data interfaces of units 610 and 620 to a system backplane connection 631. (For example, the system backplane may be a VME bus, or conform to another of the many bus architectures available.)
A system controller unit 640 controls the data transceiver unit 630 and the line interface chips 610 and 620. A five-wire serial data bus 642 (including data in, data out, interrupt, clock, and address lines) links the controller chip 640 with the data transceiver unit 630. In the presently preferred embodiment, the system controller unit 640 is a DS5000 nonvolatile microcontroller, but of course, a wide variety of other programmable logic could be used instead. The twisted-pair line driven by the transmit interface chip 620 may go through a digital cross connect (commonly referred to as a "DSX") to the channel service unit (often referred to in Tl literature as a CSU). The telephone companies' lines begin at the channel service unit. The transmit interface unit 620 performs waveform synthesis, as will now be described, to meet the Tl specification. Figure 7 shows the overall architecture of the integrated circuit which, in the preferred embodiment, implements this interface unit 620. An input data multiplexer 710 selects between loopback signals LNEG, LPOS, and LCLK, and transmit signals TPOS, TNEG, and TCLK, in accordance with control signals LB and TAIS, to provide data and clock outputs. (These signals are described in greater detail below.) These data and clock outputs are fed, through zero code suppression circuitry 720, to waveshaping circuitry 730. The waveshaping circuitry 730 accordingly generates shaped analog waveforms, as will be described below. The output of the waveshaping circuitry 730 is fed to line driver circuits 740, which provide the inputs TTIP and TRING (which will be connected to transformer 621).
Figure 1 shows a portion of the waveshaping subsystem 730 employed on the transmitter chip of the presently preferred embodiment. (The complete subsystem would also include delay line elements, as described below.) Four taps are used to generate the waveshape required for Tl transmission. (More taps can easily be designed in, if required.) This embodiment is a double-ended digital-to-analog converter, which can provide exactly matching waveforms at outputs OUTpOS and OUTXJ-DQ. An input voltage Vj-^p (which may be obtained, for example, from an on-chip bandgap voltage reference) is provided as a central input to the voltage/time array 100. This reference voltage Vj^p is also fed through op amps 102 and 104, to generate a greater (maximum) reference voltage
GVjjg and a lesser (minimum) reference voltage LVD^. Resistors Rj and R2 set voltage GVj^ , and resistors R3 and R set voltage LVj^ By matching Rj - R4, variations in supply, temperature, processing, and V- PP values can be eliminated, as can be seen by the following equations:
VREF - R2 VREF
T V - ^ v
LVREF - (R3 + R4) V EF
The positive and negative waveforms will be matched if: Abs(GVREF - VREP) = Abs(VREF - LV^p).
By eliminating V^p , this gives
Figure imgf000014_0001
The array 100 produces outputs intermediate between Vj^p and GVftpp on one side (and, on the other side, outputs intermediate between j^p and LVj^p), as selected by control inputs to the array (which are not shown).
In the presently preferred embodiment, the array 100 produces eight outputs in parallel (CLU, OLD, TLIU, TL1L, TL2U, TL2L, TL3U, and TL3D) for every control input. (Each of these output lines is tied back to j ? through a filtering capacitor 112.) Output multiplexing logic 110 selects which pair of these output lines will provide the voltage levels for the output pair OUTPQS OUTNEG-
Timing control signals TCEPT, TTl, TT2, TT3, and TEND control five pairs of switching transistors 114. Signals TCEPT and TEND are used to synthesize CEPT waveforms, while signals TTl, TT2, TT3, and TEND are used for Tl waveforms.
Polarity reversal logic 120 (controlled by inputs TXPOS and TXNEG, as clocked through flip-flops 122) selects which one of the selected output pair will be connected to drive OUTpOS, and which one will be connected to drive OUTj Q. Signal TXNEG indicates an inverted mark and signal TXPOS indicates a non-inverted mark. During a space, neither TXPOS nor TXNEG will be high, and NAND gate 123 will turn on transistors 124 to tie both outputs to V^p. This polarity reversal is required for AMI formats such as Tl and CEPT, since it guarantees that the same waveform will appear for every mark signal, whether inverted or noninverted.
Finally, two op amp follower stages 106 and 108 drive the final outputs
OUTpos and OUT^ , in accordance with the signals received from the polarity reversal logic 120. Two slew-rate-limiting capacitors 107 are provided at the final outputs; these also provide frequency compensation for op amps 106 and 108.
Figure 8 shows the circuitry actually used, in the presently preferred embodiment, to provide the timing (control) inputs to the voltage/time array 100. An input clock signal, on line 800, is coupled through a D flip- flop 802. (Gate 801 prevents the input clock from being propagated, if a previous clock is still being propagated through delay lines 810.)
Delay elements 810A, 810B, and 810C are connected in series. Delay elements 810D and 810E are also connected in series. The signal TCLKSEL is used to deactivate elements 810D-810E for Tl use, or to deactivate 810A-810C for CEPT use. A bias-regulating signal BR, and a trip-point-select signal VTRIP, are connected in common to all of the delay elements 810.
The output of each delay element 810 is connected to a respective one- shot circuit 812. (In addition, one-shot 812γ also receives the initial clock pulse.) Gate 814 combines the outputs of the one-shots, to produce a sequenced clock signal SEQCLK. This sequenced clock signal clocks a counter chain 820, which includes several flip-flops connected in series. (This counter chain, in the presently preferred embodiment, is somewhat similar to a Johnson counter, but also has similarities to a ring counter.) The first clock pulse sets the first flip-flop 822A, and drives its output high. Thereafter, each clock pulse shifts the high-output state to the next flip-flop in the chain, to drive timing signals TTl, TT2, TT3, in succession, until the last stage drives timing signal TEND. Significant control signals are marked onto Figures 5 A and 5B, to show their timing relations. Figure 5A shows (overlaid with the Tl waveform envelope) the timing of the control signals TTl, TT2, TT3, and TEND, which are used, in the preferred embodiment, to generate a Tl waveform using the circuitry of Figure 8. Figure 5B shows (overlaid with the CEPT waveform envelope) the delays used for the control signals TCEPT and TEND, which are used, in the preferred embodiment, to generate a CEPT waveform using the circuitry of Figure 8.
Figure 9 shows the circuitry of the delay lines 810, in the presently preferred embodiment. The BR input is a temperature-compensated voltage which sets the drive current level. (The BR control voltage is actually mirrored from a transistor which has the same gate length as current sink transistor 902, which is controlled by the BR voltage. In the presently preferred embodiment, the nominal gate length of this device is about 20 microns, but of course this could be widely varied.) The current passed by transistor 902 is mirrored again, through transistors 904 and 905, to provide the charging current for the delay stage.
This charging current is integrated in capacitor 910. When input signal IN goes high (while enable signal E is high), transistor 912 will be turned off. The current passed by transistor 905 will then flow into capacitor 910, and the voltage on node 914 will begin to rise.
Comparator 920 compares the voltage on node 914 with the ™™ input. As the capacitor 910 charges, device 924-^ will pass an increasingly more current, and device 924p will pass increasingly less. Whenever the current passed by pull-down devices 92^ and 926N exceeds that passed by pull-up devices 924p and 926p, the voltage of node 922 will begin to drop. This node is connected to a digital output buffer 930.
The enable signal E, which disables the delay lines, is taken from the TCLKSEL signal or its complement. In Figure 8, note that this signal is provided as a complemented input to delay lines 810D and 810E, but is not complemented at the input to lines 810A, 810B, and 810C. Thus, by switching this signal, the waveshaping output can be switched between the waveform needed for the Tl standard and the waveform needed for the CEPT standard. More generally, such a configuration with switchable delay lines provides the capability for rapid selection of customized waveforms, even if those waveforms are very different.
Figure 2 shows the organization of the voltage/time array 100. Since this is a regular array, only some of the repeating elements are shown. Moreover, it should be noted that this is a programmable array design, and an important aspect of this design is the ease with which certain elements can be changed.
A resistor divider 210 is used to quantize the voltage levels. Resistors
2101? 2102, 2103, etc., divide down the difference between GVj^p and p into the desired number of levels. Each of the row lines 220 is connected to one of the taps on the resistor string 210. Thus, for example, the first row line 220-^ sees a voltage which is equal to
VREF + (GVRHP - V^^SUM-^210/1- )}
^SUM where RguM -~ tne resistance of the whole string 210, and R2ιo/ι is the resistance of the single resistor 210 The voltages on the other row lines 2202, 2203, etc., will be similarly scaled. In the presently preferred embodiment, each of the resistors 210k has the same value. However, of course, this is not by any means a necessary part of the invention. Each of the row lines 220k includes a series string of transistors M_. __ -
M^. The gate of transistor M-^j is connected to a control input LEN1, the gate of transistor M^ is connected to a control input LEN2, and so forth. The number of control inputs n is arbitrary, and can be readily changed by designers.
Programmable metal straps 222 are available to short out any one of the transistors My. In the example of Figure 2, these straps are shown in the first row only. Note that every transistor in the first row is shorted out, except for transistor M1 2. Thus, in this example the first row will be conductive if and only if control line LEN2 is driven high.
In the presently preferred embodiment, each of the rows 220 is connected to be totally conditional on a single control input. However, as discussed below, other control strategies can be used instead. If more than one transistor in a row is left operable, the output of that row will be dependent on an AND combination of multiple control inputs.
At the other end of the row lines 220 (opposite to the resistor string 210), the row lines 220 cross a set of column busses 230. The intersecting row lines 220 and column busses 230 are not automatically connected: a connection is formed only where a strap 232 of programmable metal is formed. Again, an example of such a connection is shown only in row 1: the output of the first row 220j is connected, through the second column buss 220, to. the second result line TL2U.
Each of the result lines 240 is connected to one of the column busses. Thus, there need to be at least as many column busses as result lines. However, optionally, there may be more column busses than result lines, which can be advantageous as described below.
In the presently preferred embodiment, the column busses 230 do not connect the top and bottom halves of the array 100. However, this could be done in alternative embodiments, to provide greater resolution at voltages close to Vppp- In a further alternative embodiment, some or all of the column lines 230 can be extended to provide the outputs of the array 100, without using separate result lines 240. However, this is not preferred.
In the presently preferred embodiment, each half of the array 100 includes 100 row lines, 6 series transistors on each row line, 8 column busses, and four output lines. However, of course, these numbers can readily be varied.
For example, Figure 2 shows cell Row 1 programmed for the first tap point to connect to TL2U when LEN2 goes high; no other logic level will connect TL2U to this tap point. Should the user desire to modify TL2 to tap no. 3 when LEN2 is selected, a simple metal-mask modification will accomplish this.
Figures 3A and 3B are overlays which show important portions of the layout actually used for the array 100, in the presently preferred embodiment. (The line of thick and thin bars on the right side of each Figure is not actually part of the integrated circuit, but is provided to show the alignment of these two Figures.) Figure 3A shows the metal layer. Figure 3B shows the poly (i.e. polysilicon) layer 304, active area 302, and contacts 306. (The "active" area refers to locations where the thick field oxide has been cleared. Thus, a MOS transistor will occur wherever poly crosses active. See Meade & Conway's Introduction to VLSI Systems, which is hereby incorporated by reference.)
Each of the many small squares shown in Figure 3B is a contact. Each contact location will connect the metal layer to polysilicon (if polysilicon is under the contact) or else to substrate.
The portion shown in Figures 3A and 3B includes 6 rows and 6 columns of cells, and eight of the column lines 230. However, the array structure shown can very easily be repeated, simply by replicating elements, to vary these numbers as desired. Note that the channel locations of transistors M , M12, and M21 are shown in both Figures 3A and 3B, to help show the overlay of these Figures, even though the actual transistor structure is defined by the structure shown in Figure 3B and not by that shown in Figure 3A
The resistor string 210 is provided by an extended portion of the active area, in the presently preferred embodiment. The active area provides a sheet resistance, in the preferred embodiment, which is large enough that resistor 222 will not overload the drive capability of the op amps which provide the greater reference voltage GV^ (Of course, as will obvious to those skilled in the art of IC design, the resistor string 210 could alternatively be realized using polysilicon resistors.) Note that, in the example shown, only one of the rows has been programmed: in Figure 3A, metal straps 222 will short out transistors M51, M59, M53, M54, and M56, so that transistor M55 is the only active device left operational in this row. Jumper 232 connects this row to column line 230 . Thus, the effect of the metal options shown on the fifth row is that column line 2304 will be connected to the divided-down voltage at the start of this row if control signal MAG5 is high. Note that polysilicon links 310 permit easy selection of the connections of the column lines 230: each of the left link portions 310A is connected to the end of a row 220, and each of the right link portions 310B is connected to the end of another row 220 to the right of the array portion shown. (The whole structure shown is preferably replicated in mirror image to the right of the of the structure shown, starting with another resistor string 210.) On each of the links 310, four contacts are brought up to four tabs (in the metal level). Each of these tabs can be connected to either or both of two column lines 230. Thus, these metal tabs allow designers to have easy access (by routing lines in the metal level) to the column lines 230j, 2302, et It may also be advantageous, for reasons of space compaction, to use further right-left replication (in the orientation shown) to provide additional subarrays, which can be connected together electrically to act as if they were a single larger array.
In the metal layer shown in Figure 3B the straps and jumpers 222 and 232 represent modifications of the initial pattern. That is, when a designer calls up a metal layer pattern for modification, no jumpers 222 would (typically) be present to short out transistors, and no straps 232 would connect a link 310A or 310B to any of the column lines 230. The designer can then modify the initial pattern as desired. (Of course, in practice it is also possible, and likely to become increasingly common, to do such mask modification in software, so that the services of an experienced designer are not needed.)
To use this configuration to construct a functional circuit, a designer would normally use the following sequence of steps. (Of course, other steps can be added to this sequence.) Suppose, for example, the goal is to provide a programmable waveform synthesis circuit.
1. First, the designer identifies each target waveforms. (Each waveform can be scaled to a maximum value of unity, since scaling can be accomplished by output buffer stages.) Normally, the target waveform envelopes will be defined by other considerations, e^ by interface standards (in communications or comparable applications), or to provide a maximal basis in a parametric model of perception (in speech synthesis, music synthesis, or comparable applications), or simply by the inputs of a customer or another design group. 2. The designer then picks a piecewise-linear approximation to the target waveform, so that the target waveform is approximated as a sequence of time segments, and, at each segment, the output is a constant voltage, or a constant slew rate, or an asymptotic approach to a constant voltage. (For simplicity, it is most preferable that the approximation use a sequence of constant voltages.) The output values of successive segments may be different (but the resulting waveform will have a maximum slew rate defined by the electrical characteristics of the circuit).
3. The designer then estimates the resultant waveform which occurs when the semi-custom analog circuit according to the present invention is programmed to synthesize a waveform with voltage-of-time dependency in accordance with the approximation of the preceding step.
4. The designer then assesses the goodness-of-fit between the resultant waveform of step 3 and the target waveform of step 1. If the designer so chooses (for example, if the goodness of fit is unacceptable), steps 2-3 are iterated.
5. Optionally, the designer may then further iterate steps 2-4, attempting to reduce the complexity of the approximation of step 2, without unacceptably degrading the goodness of fit.
6. The designer then repeats steps 1-5 for each of the target waveforms. The result of this is a model, for each target waveform, which includes a sequence of delay times; a set of possible output voltages; and a set of control signals.
7. The designer then attempts to condense the parameter sets of step 6. For example, if two different target waveforms use nearly the same voltage for respective parts of their respective delays, the designer may be able to use exactly the same voltage for these two instances, which would reduce the number of taps required in the resistor string (or other voltage source). Optimization of this type requires iteration of steps 1-7.
8. After iteration of such changes, the designer can specify the connection options for the integrated circuit (in conventional fashion), if the numbers of control lines, different time delays, and output voltage levels do not exceed the capability of the resistor string. The organization and operation of the transmit line interface chip, in the presently preferred embodiment, will now be described in greater detail.
The transmit line interface chip 620 interfaces user equipment to North American (Tl-1.544 MHz) and European (CEPT-2.048 MHz) primary rate communications networks. The device is compatible with all types of twisted pair and coax cable found in such networks.
On-chip components include: programmable waveshaping circuitry, line drivers, remote loopback and zero suppression logic. A line-coupling transformer is the only external component required.
Short loop (DSX-1,0 to 655 feet) and long loop (CSU; 0 db, -7.5 db and -15 db) pulse templates found in Tl applications are supported. Appropriate CCl'lT Red Book recommendations are met in the CEPT mode. Application areas include digital-to-analog converters, CSU, CPE, channel banks and PABX to computer interfaces such as DMI and CPI. This embodiment also supports ISDN-PRI (primary rate interface) specifications.
PIN DESCRIPTION IN TYPE DESCRIPTION TAIS I Transmit Alarm Indication Signal. When high, output data is forced to all "ones at the TCLK (LB=0) or LCLK (lb=l) rate. ZCSEN I Zero Code Suppression Enable. When high, B8ZS or HDB3 encoder enabled. TCLKSEL I Transmit Clock Select. Tie to VSS for 1.544 MHz
(Tl) applications, to VDD for 2.048 MHz (CEPT) applications. I Length Select 0,1, and 2
State determines output Tl waveform shape and characteristics.
- Positive Supply. (5.0 volts.) O Transmit Tip and Ring. line driver outputs, connect to transmit line transformer.
- Signal Ground. (0.0 Volts.)
Figure imgf000024_0001
0 Line Fault. Open collector active low output. Held low during an output driver fault and/or failure; tristated otherwise.
I Monitor Tip and Ring. Normally connected to TTIP and TRING.
1 Sense inputs for line fault detection circuitry.
Figure imgf000024_0002
I Loopback. When high, input data is sampled at LPOS and LNEG on falling edges of LCLK; when low, input data is sampled at TPOS and TNEG on falling TCLK. 15 TNEG I Transmit Data 16 TPOS Sampled on falling edges of TCLK when LB=0.
17 TCLK I Transmit Clock. 1.544 MHz or 2.048 MHz primary data clock.
18 LNEG I Loopback Data 19 LPOS Sampled on falling edges of LCLK when LB=1.
20 LCLK I Loopback Clock - 1.544 MHz or 2.048 MHz loopback data clock.
Input Data Modes: Input data is sampled on the falling edges of
TCLK and LCLK and may be bipolar (dual rail) or unipolar (single rail, NRZ). TPOS, TNEG and TCLK are the data and clock inputs when
LB=0; LPOS, LNEG and LCLK when LB=1. TPOS and TNEG (LPOS and LNEG) must be tied together in NRZ applications.
Zero Code Suppression Modes: Transmitted data is treated transparently (no zero code suppression) when ZCSEN = 0. HDB3 code words replace any all-zero nibble when ZCSEN = 1 and TCLKSEL = 1.
B8ZS code words replace any incoming all-zero byte when ZCSEN = 1 and
TCLKSEL *= 0.
Alarm Indication Signal: When TAIS is set the all "ones" code is continuously transmitted at the TCLK rate (LB = 0) or the LCLK rate (LB = 1).
Waveshaping: The device supports Tl short loop (DSX-1; 0 to 655 feet), Tl long loop (CSU; 0 db, -7.5 db and -15 db) and CEPT (CCITT Red Book G.703) pulse template requirements. On-chip laser trimmed delay lines clocked by either TCLK or LCLK control a precision digital-to analog converter to build the desired waveforms which are buffered differentially by the line drivers.
The shape of the "pre-emphasized" Tl waveform is controlled by inputs LEN0, LEN1, and LEN2 (TCLKSEL = 0). These control inputs allow the user to select the appropriate output pulse shape to meet DSX-1 or CSU templates over a wide variety of cable types and lengths. Those cable types include: ABAM, PIC, and PULP.
The CEPT mode is enabled when TCLKSEL = 1. Only one output pulse shape is available in the CEPT mode; inputs LENO, LENl and LEN2 may be any state except all zeros.
The line coupling transformer also contributes to the pulse shape seen at the cross-connect point; using the transformers specified in Table 4 ensures that the measured waveform meets DSX-1 and/or CSU template requirements. Transformers are 1:1.
The waveshaping circuitry does not contribute significantly to output jitter. Output jitter will be dominated by the jitter on TCLK or LCLK.
TCLK and LCLK need only be accurate in frequency, not duty cycles.
LINE DRIVERS: The on-chip differential line drivers interface directly to the output transformer. To optimize device performance, length of the
TTIP and TRING traces should be minimized and isolated form neighboring interconnect. The device will enter a standby mode when the input data is all "zeros". This disables the output drivers and reduces power consumption significantly. FAULT PROTECTION: The line drivers are fault protected and will withstand a shorted transformer secondary (or primary) without damage.
Inputs MTIP and MRING are normally tied to TTIP and TRING to provide fault monitoring capability. Output LF* will transition low if 192
TCLK cycles occur without a "one" occurring at MTIP or MRING. LF* will tristate on the next "one" occurrence or two TCLK periods later, whichever is greater.
The "one" threshold of MTIP and MRING varies with the line type selected at LENO, LENl and LEN2. This insures detection of the lowest level 0 to 1 transition (-15 dB buildout) as it occurs on TTIP and TRING. MTIP and MRING may be tied to neighboring device's TTIP and TRING outputs to provide superior fault monitoring.
Tl LINE LENGTH SELECTION Nl LENO OPTION SELECTED APPUCATION
Test Mode Do not use
-7.5 dB buildout Tl CSU
-15 dB buildout Tl CSU
0 dB buildout (0-133 feet) Tl CSU, DSX-1 CrossConnect 133 - 266 feet DSX-1 CrossConnect
266 - 399 feet DSX-1 CrossConnect
399 - 533 feet DSX-1 CrossConnect
Figure imgf000027_0001
533 - 655 feet DSX-1 CrossConnect
NOTE: The LENO, LENl and LEN2 inputs control Tl output waveshapes when TCLKSEL = 0. The G.703 (CEPT) template is selected when
TCLKSEL = 1 and LENO, LENl and LEN2 are at any state except all zeros.
Further Modifications and Variations
It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts. Note that the converter architecture provided by the present invention can provide normal digital-to-analog converter functionality. For example, by using a ladder of 2n equal resistors, an n-bit digital-to-analog converter can be directly configured. By using resistors scaled in powers of two, and adding a shunting transistor in parallel with each resistor, a wider-range digital-to-analog converter can be configured.
Although a digital-to-analog converter which uses programmable delay lines to provide the control signals (as in the preferred embodiment) is highly advantageous for shaping waveforms, the ability to provide a more conventional digital-to-analog converter gives the circuit designer more options.
In particular, while the primary embodiment described is directed to Tl interface requirements, it must be recognized that the waveshaping capabilities provided are very widely applicable. Many applications can make use of the capability to provide a semi-custom waveform, with very high time-domain resolution, economically.
It should also be recognized that it is not strictly necessary for all of the delay line stages to be connected in series. While this is convenient (to minimize capacitor size), this arrangement does have the minor disadvantage that a change in an early delay stage will also change the total delay of all later stages. Thus, in some applications it may be preferable to use multiple delay stages in series and in parallel.
It should also be noted the a variety of ways can be used to configure the outputs of the delay stages into control inputs for the voltage generator stages. For example, it may be preferable to provide more delay line taps than would be needed for any one waveform type, with transistors to disable some of the control lines depending on the waveform type needed. In the presently preferred embodiment, the control inputs LENl etc. are used to select the voltage magnitudes coming out of the voltage/time array 100, and the timing control signals TTl etc. are used to select the sequence of these magnitudes to form the desired waveform. However, alternatively, at least some of the sequence control can be performed by using the array inputs LENl etc. (In fact, the functions of these two groups of control inputs could even be reversed if desired, with the LENl etc. inputs each used to control the sequence of levels appearing on each column bus, and the TTl etc. controls used to select which of the column busses would be connected to the output lines.)
In a further optional alternative, switching logic is also used to switch output-loading capacitors in or out, to provide variable slew rate control on the outputs. This capability permits a user to more easily match a complex target waveform specification where it may be necessary to provide controlled rates of voltage change. (By comparison, the presently preferred embodiment simply uses capacitors on the output line to limit the maximum slew rate. Instead, this alternative embodiment would permit the maximum slew rate to be varied dynamically.)
As a further class of alternatives, it is also possible to perform additional programming dynamically. For example, instead of trimming capacitors to adjust the delay line stages, this can be done by switching capacitors (or resistors), or even by using the non-linear capacitance of certain semiconductor structures to provide varactor trimming.
It is also possible to use different techniques to provide the multiple input reference voltages. Instead of the resistor string or capacitor array mentioned above, more complex circuits can be used, including (optionally) active devices to permit changing these input voltage levels on the fly. It will be readily recognized by those skilled in the art that the innovative concepts could readily be adapted to a different allocation of functions onto integrated circuits. In the presently preferred embodiment each of the units 110, 120, 130, and 140 is built on a separate integrated circuit, but alternatively some of these units could be combined.
In a further alternative embodiment, the delay line blocks can be modified so that their delay is not constant. In some applications, it may be preferable to use variable-delay blocks. Instead of providing a delay of a fixed number of nanoseconds, such a circuit can be configured to (for example) provide delay for a predetermined percentage of the clock period (as long as the clock frequency is within a permissible range).
It should also be noted that the use of a highly programmable digital- to-analog converter, as in the presently preferred embodiment, is not by any means the only way in which the innovative ideas set forth could be used. Instead of a digital-to-analog converter, other analog voltage genera¬ tion circuits could be used. A tremendous variety of such circuits are known, and such circuits can be selected for the utility in forming a piece- wise time-domain approximation of a desired waveform.
In addition to the selection of one of the scaled reference voltages from the resistor string 210, alternative versions of the voltage/time array also permit the tap voltages of the resistor string 210 to be varied. This can be done in several ways. In one class of alternative embodiments, this is done by configuring the jumpers 232 so that, in some states of the control logic, two of the row lines would both be connected to a common isolated column buss. For example, suppose that the example of Figure 2 is modified as follows: the second transistors M22 and M3 -*> in the second and third row lines are not shunted by straps 222, and all other transistors on these two row lines are shunted; the second and third row lines 2202 and 2203 are both connected, through respective jumpers 230, to a dummy column buss
230dummy
If these changes are made, the voltage seen at TL2U when signal
LEN2 is high will no longer be
Figure imgf000031_0001
but instead will be
REF + (GVRHP - ),
Figure imgf000031_0002
which is closer to Vj^ .
In such embodiments, the output-switching logic can also be used to disable outputs which (under some control states) may be in use as intermediate nodes, to change the total value RS M of the resistor string.
Such changes in scaling can also be accomplished by switching trim resistors in or out of resistors Rj - R4. However, this would not be as suitable for rapid switching, due to the need for the amplifiers to settle. A further option is switching additional series resistors in or out of the resistor chain 210, but this is even less desirable, due to the resulting layout complexities. A further advantage of the disclosed architecture is that changes in the sequencing of output levels can easily be accomplished by programmation changes in the array 100. Thus, for example, even if the timing control signals TTl etc. are generated elsewhere, sequencing changes can readily be made in the time/voltage array 100, by changing the connections of the magnitude control inputs LENl etc. This capability gives the designer additional flexibility.
Note that the innovative architecture is highly modular and expandable: As many sequencing transistors as desired can be added into a row; large numbers of scaled voltages can be used if desired; the number of column busses can be increased if desired; and the number of result lines can also readily be increased.
In a further alternative, some ANDing logic could be added, to steal phases from overlaps. For example, suppose that row hne ROWl is gated only by control signal LEN4, and another row line ROW2 is gated only by control signal LEN5. If control signals LEN4 and LEN5 are sequential phase signals which overlap for part (but not all) of their durations, then an intermediate phase can be created by defining another row line (for example, ROW3) to be gated by both LEN4 and LEN5. In this case, it may be desirable to define some of the control lines as complementary. In the example just described, any problem of collision can be avoided if row line ROWl is gated both by control signal LEN4 and also by another signal LEN5* which is the complement of LEN5, and if row line ROW2 is similarly gated by LEN5 and LEN4*.
The presently preferred embodiment provides a digital-to-analog converter which is fully double-ended - e. which provides complementary waveforms on a pair of output lines - but the innovative teachings can readily be adapted to a single-ended design instead. The use of the double- ended digital-to-analog converter architecture is particularly advantageous for a Tl transmitter, since it means that exactly symmetrical waveforms can be produced, regardless of whether the Mark signal is inverted or not.
This very flexible architecture can be further modified, if desired, to make it more like a programmable logic array, by adding additional gates and interconnects to the topology of the row lines, and thereby introducing additional features of combinatorial or sequential digital or analog functions.
Again, it must be understood that the innovative teachings herein are very broadly applicable. It is believed that these teachings may provide a generally useful integrated circuit element, which can be as versatile in analog design problems as logic arrays have proven to be for digital designers.
In addition, the innovative ideas set forth above could also be adapted to use other programmation methods. For example, instead of shunting transistors with metal straps, the transistors can be designed as EPROM- like or EEPROM-like devices, where the transistor's threshold voltage is shifted by storing charge on a floating gate. For another example, the programmation can also (less preferably) be performed using distributed fuses or antifuses, or using battery-backed static gates. (However, these alternative approaches tend to place more burden on the interconnect density, and are therefore less preferable.)
As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly their scope is not limited except by the allowed claims.

Claims

CLAIMSWhat is claimed is:
1. A circuit for shaping waveforms, comprising: a plurality of delay elements, said delay elements being serially connected, with taps, to drive plural control Mnes at predetermined sequential times; a voltage generator circuit, connected to receive said control lines, and configured to output a voltage which is selected, in accordance with the instantaneous state of said control lines, from plural predetermined possible voltages; wherein plural ones of said delay elements have adjustable delay characteristics.
2. A transmit line interface unit, comprising: a plurality of delay elements, said delay elements being serially connected, with taps, to drive plural control lines at predetermined sequential times; a voltage generator circuit, connected to receive said control lines, and configured to output a voltage which is selected, in accordance with the instantaneous state of said control lines, from plural predeteιτnined possible voltages; wherein plural ones of said delay elements have adjustable delay characteristics; and wherein said predetermined possible voltages, and the control relation of said control lines to said voltage generator circuit, are predefined so that a user can select a waveform, consisting of voltage levels selected from said predetermined possible voltages separated by time delays defined by said delay elements, which provide the output waveform specified by a communications interface standard.
3. A method for transmitting data in accordance with a predetermined protocol which requires loading-dependent voltage levels, comprising the steps of: providing a transmit line interface unit, which includes delay stages which provide predetermined signals on a plurality of control lines, in accordance with time-domain boundaries of a waveform compatible with the predetermined protocol, and a voltage generator circuit, connected to receive said control lines, and configured to output a voltage which is selected, in accordance with the instantaneous state of said control lines, from a set of plural possible voltages; programming said voltage generator circuit, to change said set of possible voltages, in accordance with the load characteristics of a particular installation; and repeatedly clocking said delay lines stages to produce said compatible waveform at the output of said voltage generator circuit.
4. The circuit of Claim 1, wherein said voltage generator circuit comprises an analog to digital converter circuit, and said control lines comprise digital bits of input thereto.
5. The circuit of Claim 1, wherein said voltage generator circuit generates complementary bipolar outputs in response to the signals on said control lines.
6. The circuit of Claim 1, wherein plural ones of said delay elements each include capacitors which can be trimmed to change a time constant thereof.
7. The circuit of Claim 1, wherein plural ones of said delay elements each have a programmable delay time.
8. The circuit of Claim 1, wherein a clock signal is applied as an input to said plurality of delay elements.
9. The circuit of Claim 1, wherein the outputs of said delay stages are logically combined to provide a clock signal to a counter, and the count value output of said counter provides a multibit input to said voltage generator circuit.
10. The circuit of Claim 1, wherein the output of at least one of said delay stages are connected through a respective one-shot circuit.
11. An integrated circuit digital to analog converter, comprising: a voltage source, which provides multiple scaled voltages; a plurality of row lines, connected to receive respective ones of said scaled voltages from said voltage source; each of said row lines including multiple selection transistor locations in series, respective ones of said selection transistors having gates which are connected to control inputs, programmable connections being located to short out selected respective ones of said selection transistors; a plurality of column busses; a plurality of programmable jumpers, each selectably connecting a respective one of said row lines to a respective one of said column busses; said selection transistors being configured so that, for substantially every normal value of control inputs, multiple ones of said column busses will be driven simultaneously.
12. An integrated circuit digital to analog converter, comprising: a voltage source, which provides multiple scaled voltages; a plurality of row lines, each connected to a respective one of said scaled voltages, and respectively configured, to receive at least one of a plurality of control inputs, so that, for substantially every normal value of the control inputs, multiple ones of said row lines will connect a respective one of said scaled voltages into a path which leads to a respective one of a plurality of result lines; and output selection gates, connected to select one of said result lines for output.
13. A method for designing an analog integrated circuit to generate at least one predetermined analog target waveform, comprising the steps of:
(a.) providing an initial standardized integrated circuit definition, which includes (1) a voltage source, which provides multiple scaled voltages;
(2) a plurality of row lines, connected to receive respective ones of said scaled voltages from said voltage source;
(3) each of said row lines including multiple selection transistor locations in series, respective ones of said selection transistors having gates which are connected to with control inputs, with programmable connections shorting ones of said respective selection transistors;
(4) a plurality of column busses; (5) a plurality of programmable jumpers, each connecting a respective one of said row lines to a respective one of said column busses;
(6) said selection transistors being configured so that, for substantially every normal value of control inputs, multiple ones of said column busses will be driven simultaneously;
(b.) defining a piecewise approximation to the target waveform as a sequence of signals at successive time segments, wherein, at each segment, the corresponding signal is selected from the group consisting of: constant voltages, signals which change at a fixed rate, and signals which asymptotically approach a constant voltage; and
(c.) providing a plurality of partially fabricated integrated circuit structures corresponding to said initial standardized definition, and patterning at least one interconnect layer of said integrated circuit structures to provide said programmable connections and said programmable jumpers in locations which will sequentially provide the successive voltage values indicated by said approximation of said target waveform.
14. The integrated circuit of Claim 11, comprising at least 64 of said row lines.
15. The integrated circuit of Claim 11, wherein said scaled voltages provided by said voltage source include both voltages which are positive with respect to a reference voltage connection, and also voltages which are negative with respect to a reference voltage connection; and wherein said selection transistors are configured to provide complementary positive and negative outputs simultaneously on said column busses; and further comprising polarity reversal logic, connected to receive said positive and negative outputs of said selection transistors and to selectably exchange said positive and negative outputs in accordance with the state of a control signal.
16. The method of Claim 13, further comprising the additional step, subsequent to said step (b) and prior to said step (c), of estimating the resultant waveform which occurs when a semi-custom analog circuit according to the definition of step (a.) is programmed, according to said step (c), to synthesize a waveform with voltage-of-time dependency in accordance with the approximation of said step (b).
17. The method of Claim 13, further comprising the additional steps, subsequent to said step (b) and prior to said step (c), of estimating the resultant waveform which occurs when a semi-custom analog circuit according to the definition of step (a.) is programmed, according to said step (c), to synthesize a waveform with voltage-of-time dependency in accordance with the approximation of said step (b); and assessing the goodness-of-fit between the resultant waveform of step 3 and the target waveform of step 1.
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