WO1991009403A3 - Dual port, dual speed image memory access arrangement - Google Patents

Dual port, dual speed image memory access arrangement Download PDF

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Publication number
WO1991009403A3
WO1991009403A3 PCT/US1990/007035 US9007035W WO9109403A3 WO 1991009403 A3 WO1991009403 A3 WO 1991009403A3 US 9007035 W US9007035 W US 9007035W WO 9109403 A3 WO9109403 A3 WO 9109403A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
high speed
port
controllably
dual
Prior art date
Application number
PCT/US1990/007035
Other languages
French (fr)
Other versions
WO1991009403A2 (en
Inventor
Kurt Michael Sanger
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Priority to DE69023229T priority Critical patent/DE69023229T2/en
Priority to EP91900457A priority patent/EP0458926B1/en
Publication of WO1991009403A2 publication Critical patent/WO1991009403A2/en
Publication of WO1991009403A3 publication Critical patent/WO1991009403A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/24—Systems for the transmission of television signals using pulse code modulation

Abstract

A dual port, dual speed image memory interface is capable of controllably inputting or outputting medium speed serial data through a medium speed port at the same time that high speed serial imagery data is being supplied to or read from a high speed data rate port. Access to the medium speed port is through a mux/demux unit, which is coupled to receive imagery data at the medium data rate and controllably writes successive data signals, in parallel, into respective ones of a set of plural memory units, and controllably reads out data from the parallel-connected memory units and assembles the accessed data in the form of a serial output digital data stream for transmission to a requesting destination device signals at the medium data rate. Access to the high speed port is through a high data rate shift register, which is coupled to receive high speed imagery data and controllably transfers successive pixel signals, in parallel, to the input stage of each of internal shift registers that are coupled to respective row access ports of the plurality of parallel-connected memory units. The contents of the internal shift registers are transferred into associated rows of memory to store successive lines of imagery data. During high speed read out successive rows of memory data are transferred from the internal shift registers into a respective stage of the high data rate shift register, which is then serially clocked for high speed readout.
PCT/US1990/007035 1989-12-15 1990-12-03 Dual port, dual speed image memory access arrangement WO1991009403A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE69023229T DE69023229T2 (en) 1989-12-15 1990-12-03 TWO GATES, TWO SPEED IMAGE ACCESS ARRANGEMENT.
EP91900457A EP0458926B1 (en) 1989-12-15 1990-12-03 Dual port, dual speed image memory access arrangement

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US451,398 1989-12-15
US07/451,398 US5157775A (en) 1989-12-15 1989-12-15 Dual port, dual speed image memory access arrangement

Publications (2)

Publication Number Publication Date
WO1991009403A2 WO1991009403A2 (en) 1991-06-27
WO1991009403A3 true WO1991009403A3 (en) 1991-10-17

Family

ID=23792024

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/007035 WO1991009403A2 (en) 1989-12-15 1990-12-03 Dual port, dual speed image memory access arrangement

Country Status (5)

Country Link
US (1) US5157775A (en)
EP (1) EP0458926B1 (en)
JP (1) JPH04505976A (en)
DE (1) DE69023229T2 (en)
WO (1) WO1991009403A2 (en)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367680A (en) * 1990-02-13 1994-11-22 International Business Machines Corporation Rendering context manager for display adapters supporting multiple domains
JPH0821233B2 (en) * 1990-03-13 1996-03-04 株式会社東芝 Image memory and method for reading data from image memory
JP2965043B2 (en) * 1990-04-10 1999-10-18 三菱電機株式会社 Dual port memory
GB2250615B (en) * 1990-11-21 1995-06-14 Apple Computer Apparatus for performing direct memory access with stride
US5636358A (en) * 1991-09-27 1997-06-03 Emc Corporation Method and apparatus for transferring data in a storage device including a dual-port buffer
US5386532A (en) * 1991-12-30 1995-01-31 Sun Microsystems, Inc. Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels
US5388237A (en) * 1991-12-30 1995-02-07 Sun Microsystems, Inc. Method of and apparatus for interleaving multiple-channel DMA operations
US5371877A (en) * 1991-12-31 1994-12-06 Apple Computer, Inc. Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memory
US6299065B1 (en) * 1992-01-13 2001-10-09 Metrologic Instruments, Inc. Bar code processing system with multiport signal decoder
US5303200A (en) * 1992-07-02 1994-04-12 The Boeing Company N-dimensional multi-port memory
US5623634A (en) * 1992-09-15 1997-04-22 S3, Incorporated Resource allocation with parameter counter in multiple requester system
US5442747A (en) * 1993-09-27 1995-08-15 Auravision Corporation Flexible multiport multiformat burst buffer
JP3579461B2 (en) * 1993-10-15 2004-10-20 株式会社ルネサステクノロジ Data processing system and data processing device
US5422998A (en) * 1993-11-15 1995-06-06 Margolin; Jed Video memory with flash fill
FR2717979B1 (en) * 1994-03-24 1996-06-21 Sgs Thomson Microelectronics Pixel matrix filter.
US6549948B1 (en) * 1994-10-18 2003-04-15 Canon Kabushiki Kaisha Variable frame rate adjustment in a video system
FI971718A (en) * 1997-04-22 1998-10-23 Nokia Telecommunications Oy Adding card slots to a high-capacity bus
US5917769A (en) * 1997-08-12 1999-06-29 Lucent Technologies Inc. Method and system rotating data in a memory array device
US6072412A (en) * 1998-04-29 2000-06-06 Sony Corporation Parallel port to serial digital fiber link connector
US5982700A (en) * 1998-05-21 1999-11-09 Integrated Device Technology, Inc. Buffer memory arrays having nonlinear columns for providing parallel data access capability and methods of operating same
US6216205B1 (en) 1998-05-21 2001-04-10 Integrated Device Technology, Inc. Methods of controlling memory buffers having tri-port cache arrays therein
US5978307A (en) * 1998-05-21 1999-11-02 Integrated Device Technology, Inc. Integrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating same
US5999478A (en) * 1998-05-21 1999-12-07 Integrated Device Technology, Inc. Highly integrated tri-port memory buffers having fast fall-through capability and methods of operating same
US6267294B1 (en) * 1998-09-11 2001-07-31 Robotic Vision Systems Inc. Method of operating a charge coupled device in an accelerated mode, and in conjunction with an optical symbology imager
SE518865C2 (en) 1998-12-22 2002-12-03 Switchcore Ab Converter for data in serial and parallel format, has twin port storage cells linked to data channels via database with buffer circuit
US7231537B2 (en) * 2003-07-03 2007-06-12 Micron Technology, Inc. Fast data access mode in a memory device
JP2011227834A (en) * 2010-04-22 2011-11-10 Sony Corp Signal control device and signal control method
KR102016629B1 (en) * 2018-01-18 2019-08-30 미쓰비시덴키 가부시키가이샤 PLC, network unit, CPU unit, and data transfer method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2582423A1 (en) * 1985-05-22 1986-11-28 Grenoble Inst Nal Polytechni Buffer memory to be interposed between two synchronous systems with different speeds
EP0309877A2 (en) * 1987-09-30 1989-04-05 Deutsche Thomson-Brandt GmbH Memory device
US4864402A (en) * 1986-06-20 1989-09-05 Sony Corporation Video memory

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435792A (en) * 1982-06-30 1984-03-06 Sun Microsystems, Inc. Raster memory manipulation apparatus
US4597061B1 (en) * 1983-01-03 1998-06-09 Texas Instruments Inc Memory system using pipleline circuitry for improved system
US4646270A (en) * 1983-09-15 1987-02-24 Motorola, Inc. Video graphic dynamic RAM
US4663735A (en) * 1983-12-30 1987-05-05 Texas Instruments Incorporated Random/serial access mode selection circuit for a video memory system
US4665495A (en) * 1984-07-23 1987-05-12 Texas Instruments Incorporated Single chip dram controller and CRT controller
US4631692A (en) * 1984-09-21 1986-12-23 Video-7 Incorporated RGB interface
JPS6242228A (en) * 1985-08-19 1987-02-24 Nec Corp Display information processing system
US4905189B1 (en) * 1985-12-18 1993-06-01 System for reading and writing information
US4794464A (en) * 1986-09-02 1988-12-27 Eastman Kodak Company Video time division multiplexer with plural dual port memories
JPS63136391A (en) * 1986-11-27 1988-06-08 Nec Corp Semiconductor memory device
US4821226A (en) * 1987-01-30 1989-04-11 Rca Licensing Corporation Dual port video memory system having a bit-serial address input port
US4789960A (en) * 1987-01-30 1988-12-06 Rca Licensing Corporation Dual port video memory system having semi-synchronous data input and data output
JPH01224993A (en) * 1988-03-04 1989-09-07 Nec Corp Multiport memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2582423A1 (en) * 1985-05-22 1986-11-28 Grenoble Inst Nal Polytechni Buffer memory to be interposed between two synchronous systems with different speeds
US4864402A (en) * 1986-06-20 1989-09-05 Sony Corporation Video memory
EP0309877A2 (en) * 1987-09-30 1989-04-05 Deutsche Thomson-Brandt GmbH Memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN. vol. 33, no. 22, October 1989, HASBROUCK HEIGHTS, NEW JERSEY pages 171 - 178; PRICE: 'CMOS 256-KBIT VIDEO RAM, WITH WIDE TWO-WAY BUS, PICKS UP SPEED DROPS POWER ' see page 172, right column, line 7 - page 173, right column, line 8; figures 1-4 SA 42750 030 *

Also Published As

Publication number Publication date
DE69023229D1 (en) 1995-11-30
EP0458926B1 (en) 1995-10-25
WO1991009403A2 (en) 1991-06-27
DE69023229T2 (en) 1996-06-13
US5157775A (en) 1992-10-20
EP0458926A1 (en) 1991-12-04
JPH04505976A (en) 1992-10-15

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