WO1993011499A1

WO1993011499A1 - Orthogonal rotator

Info

Publication number: WO1993011499A1
Application number: PCT/JP1992/001558
Authority: WO
Inventors: Derek J. Lentz; Linley M. Young
Original assignee: Seiko Epson Corporation
Priority date: 1991-11-27
Filing date: 1992-11-27
Publication date: 1993-06-10
Also published as: JPH07502352A; JP3150342B2

Abstract

A high performance orthogonal rotator for a graphics processor orthogonally rotates pixel regions in a bit map by an angle of 90° or 270°. Optionally, the pixel regions can be vertically mirrored as well as orthogonally rotated. Source data bytes from a source bit map are loaded into columns of a matrix array constructed from parallel registers forming the rows. Orthogonal rotation and vertical mirroring is accomplished by the order in which bytes are loaded from the source bit map and by the order in which bytes are read into a destination bit map. To accomplish a 90° rotation without vertical mirroring, data bytes are first loaded into the matrix array columns beginning with the LSB column and ending with the MSB column. Then, data words are read beginning with the MSW located in the bottom register and ending with the LSW located in the top register. To achieve a 90° rotation with vertical mirroring, data bytes are first loaded into the matrix array columns beginning with the LSB column and ending with the MSB column. Then, data words are read beginning with the LSW in the top register and ending with the MSW in the bottom register. To accomplish a 270° rotation without vertical mirroring, data bytes are first loaded into the matrix array columns beginning with the MSB column and ending with the LSB column. Then, data words are read beginning with the LSW in the top register (108) and ending with the MSW in the bottom register. To effectuate a 270° rotation with vertical mirroring, data bytes are first loaded into the matrix array columns beginning with the MSB column and ending with the LSB column. Then, data words are read beginning with the MSW in the bottom register and ending with the LSW in the top register.

Description

D E S C R I P T I O N

Title of the Invention : ORTHOGONAL ROTATOR

Cross-Reference to Related Application

This application is related to a pending patent application entitled, "Single Chip Page Printer Controller," Serial No. 07/726,929 filed July 8, 1991, which is incorporated by reference as if set forth in full hereinbelow.

Background of the Invention

1. Field of the Invention

The present invention relates to the field of computer graphics and, more particularly, to manipulating data stored in a bit map pertaining to an video image to be presented by a raster printer, screen, display device, or other humanly visible manifestation.

2. Related Art

In raster graphics systems, a graphics image is stored in memory and presented to a printer, screen, or display device by representing the image in the form of a matrix of bits. The matrix is referred to as a "bit map" or a "frame buffer". For monochrome systems, one bit in the bit map represents one visible dot, or picture element (pixel, for short), on the display. Forgray scale or color systems, several bits in the bit map represent one pixel or group of pixels on the display.

Many types of graphics processors have been designed and implemented in the art for controlling the display of graphics images. Graphics processor dedicated to this task help relieve the processing burden of the controlling processor. Graphics processors are usually designed to not only generate image data, but also manipulate existing image data in the bit map. A typical graphics manipulation is rotation. "Rotation" refers to moving an image, or parts thereof, about an axis perpendicular to the display, as opposed to "translation^", or "shifting", which refers to the linear component of movement, i.e., movement across the display.

In order to rotate an image using straightforward mathematics implemented in hardware and/or software, extensive calculations are required. A reason is that the bit map is dealt with as a coordinate system having an X and a Y component. In order to manipulate a bit in the bit map, both the X and Y components must be considered. s a resu t o t e comp ex mat emat cs nvo ve n rotat ng grap ics images, rotation operations have commonly been implemented by drawing characters at every angle to be used and storing the characters in font tables or font caches. Essentially, all available characters are stored in the font tables, and any rotated view of a character is treated as a separate and unique character. Therefore, in order to provide for the most common rotations of a character, i.e., 90°, 180°, or 270°, four fonts are stored in the font table corresponding to each angle of rotation.

Furthermore, the font table can be reduced in size by storing only a single version of a character and then when rotation is needed, software can be utilized to rotate the character. However, rotation using software is much slower than rotation using" hardware, thereby resulting in a decrease in system performance.

Another technique for implementing rotation is suggested in U.S. Patent 4,797,852 to S. Nanda, entitled "Block Shifter For Graphics Processor", which is incorporated by reference as if set forth in full hereinbelow. A block shifter is provided in the form of a matrix array of registers. Rotation is achieved by first loading the block shifter with data from memory. Then, bits are shifted horizontally and vertically as determined by a predetermined algorithm, thereby allowing for bits stored in the array to change positions. Once a rotation operation is completed, the bit pattern representing the rotated data is read in sequential word order from the register array from a lateral output or vertical output. As a result of Nanda' s teachings, only one font per character need be stored in a font table, because all rotational views are accomplished by character block transfer.

Although the foregoing techniques have to some extent reduced the arithmetic overload associated with performing image rotations, the system circuitry required to implement them is undesirably large. Hence, high performance graphics systems utilizing lesser real estate, or space, than those in the art are still needed in the highly competitive graphics industry where speed, efficiency, and space considerations are the primary driving forces.

Summary of the Invention

The present invention is an orthogonal rotator which can be used to orthogonally (90° or 270°) rotate as well as vertically mirror a bit map region in a graphics processor.

In the present invention, a register array means is configured in the form of a matrix having rows and columns of bit locations. A bit control means in conjunction with a word control means controls the register array means. The bit control means loads source data bytes from a source bit map into the columns of the register array means. Orthogonal rotation and vertical mirroring is accomplished by the order in which bytes are loaded into the register array means from the source bit map in map.

Specifically, to accomplish a 90° rotation without vertical mirroring, the bit control means loads source data bytes into the columns of the register array means in the order beginning with the least significant bit (LSB) positions residing in the far left column (hereafter, LSB column) and ending with the most significant bit (MSB) • positions residing in the far right column (hereafter, MSB column). The word control means then reads data words from the register array means beginning with the most significant word (MSW) in the bottom register and ending with the least significant word (LSW) in the top register.

To achieve a 90° rotation with vertical mirroring, data bytes are loaded into the register array means in the order beginning with the LSB column and ending with the MSB column. Then, data words are read from the register array means beginning with the LSW in the top register and ending with the MSW in the bottom register.

To accomplish a 270° rotation without vertical mirroring, data bytes are loaded into the register array means in the order beginning with the MSB column and ending with the LSB column. The word control means then reads words from the register array means beginning with the LSW in the top register 108 and ending with the MSW in the bottom register.

To effectuate a 270° rotation with vertical mirroring, source data bytes are loaded into the register array means in the order beginning with the MSB column and ending with the LSB column. Then, data words are read from the register array means beginning with the MSW in the bottom register and ending with the LSW in the top register.

The present invention has many advantages and applications. For example, it can be easily implemented in little real estate within an integrated circuit, such as a RISC type microprocessor, in order to provide for rapid and reliable rotation of image data (byte by byte) in a bit map. The orthogonal rotator can easily implement a clearing function.

The independent operation of the orthogonal rotator permits other subsystems of a graphics processor to concurrently function while the orthogonal rotator is performing, thereby providing a more rapid graphics capability.

Still another advantage of the present invention is that it allows for a trade- off among hardware, software, performance, and space requirements. For instance, data can be read from the novel orthogonal rotator, via software or hardware, or combinations thereof, depending upon the performance and space requirements. Moreover, the number of word registers in the orthogonal rotator is flexible. The number of word registers can be increased to thereby increase the performance of the system at the expense of space. In other words, although the preferred embodiment has 8 word registers, this number could be increased to 16 or 32, if desired. Furthermore, if hardware costs and real estate are of primary concern, then the number of word registers can be reduced.

Yet another advantage of the present invention is that the novel orthogonal . rotator may be used in combination with a simple horizontal mirroring^' system which can effectively rotate a bit map region by an angle of 180°, to thereby provide for all rotations in increments of 90°. A horizontal mirroring. system for this purpose is taught in a copending application entitled, "Pixel Modification Unit", with Serial

No. (^"Attv Docket SP029). which is incorporated herein by reference.

Brief Description of the Drawings

The present invention, as defined in the claims, can be better understood with reference to the following drawings.

FIGURE 1 is a block diagram of the orthogonal rotator having a register array in accordance with the present invention;

FIGURE 2(a) illustrates a 90° rotation of a region within a video image in a bit map;

FIGURE 2(b) illustrates a 270° rotation of a region within a video image in a bit map; FIGURE 2(c) illustrates a 90° rotation with vertical mirroring of a region within a video image in a bit map;

FIGURE 2(d) illustrates a 270° rotation with vertical mirroring of a region within a video image in a bit map;

FIGURE 3 illustrates a block diagram of a register array bit within the register array of FIGURE 1 with the surrounding communication paths; and

FIGURE 4 illustrates a high level flow chart of the methodology of the present invention.

Detailed Description of the Preferred Embodiments FIGURE 1 is a block diagram of a high performance orthogonal rotator 100 in accordance with the present invention. The orthogonal rotator 100 can orthogonally rotate, i.e., rotate by 90° or 270°, as well as vertically mirror regions of bit map data on a byte-by-byte basis from a graphics source bit map 102.

FIGUREs 2(a)-2(d) visually illustrate the concepts of orthogonal rotation and vertical mirroring in the context of this document.* In FIGURE 2(a), a region 202 within the source bit map 102 is rotated by an angle of 90° (counterclockwise convention), as shown by the orthogonally-rotated region 204 in the destination bit map 122. , orthogonally rotated by an angle of 270^° (counterclockwise convention), as indicated by the orthogonally-rotated region 206 in the destination bit map 122.

In FIGURE 2(c), the bit map region 202 within the source bit map 102 is rotated by an angle of 90° and is also vertically mirrored. The configuration of the rotated and vertically-mirrored region 214 is shown in the destination bit map 122.

Furthermore, in FIGURE 2(d), the bit map region 202 within the source bit map 102 is orthogonally rotated by an angle of 270° and is also vertically mirrored. The configuration of the rotated and vertically-mirrored region 216 is illustrated in the destination bit map 122.

Referring back to FIGURE 1, from an architecture vantage point, the novel orthogonal rotator 100 comprises a bit decode/control logic 104, a word decode/control logic 105, and a register array 106. In the preferred embodiment, the register array 106 has 8 rows of respective registers 108-114. Generally, a bit select control signal 116 from controlling software, for example, is provided to the bit decode/control logic 104, while source data 118 is provided to the registers 108-114, so as to generate orthogonally- rotated output data 120. The orthogonally-rotated output data 120 is placed in the graphics destination bit map 122, as shown.

A common convention in the graphics industry is to have the least significant bit (LSB) of each byte on the left of image bit maps and the most significant bit (MSB) of each byte on the right of image bit maps. The foregoing common convention is used in the description herein for discussion purposes, but this convention need not be utilized in order to practice the present invention. Thus, in FIGURE 1, the bit b^i corresponds to the right-most bit in the bit maps, while the bo corresponds to the left-most bit in the bit maps. Moreover, the least significant word (LSW) is stored in the top register 108, while the most significant word (MSW) is stored in the bottom register 114.

The present invention envisions transferring source data bytes (8 bits) into columns of the register array 106. Source data bytes are written to the register array until the array is full, completely or in part. As specifically shown in FIGURE 1, each source data byte 124-130 is bit spliced so that each of its bits is channeled to a different register (or row) 108-1J4. Each bit-spliced bit is then multiplexed to all bits of its exclusive register, i.e. , one of registers 108-114. For instance, source bit 0 is passed to all 32 bits of array register 0. Source bit 1 is passed to all 32 bits of array register 1, and so on, as shown in FIGURE 1.

The bit select control signal 116 is decoded by the bit decode/control 104 so as to generate a set of 32-bit load select control signals, which are fed to the respective registers 108-114, as shown in FIGURE 1. The load select signals are bit sliced across the columns of the register array 106. In other words, load select control bit 0, denoted by reference numeral 132, controls the column 0 comprising all bits \.Q. Load select control bit 1, denoted by reference numeral 134, controls the column 1 comprising all bits b^, and so on. Thus, the bit select control signal 116 selects the array column where the inputted source data byte will be written. Furthermore, even though a source data bit is multiplexed over all bits of a register 108-114, only 1 bit of each register 108-114 is loaded by the source data bit.

Furthermore, a word select control signal 144 and a load/read control signal 146 are decoded by a word decode/control logic 148 so as to generate a word load signal and a word read signal for each of the registers 108-114, as shown in FIGURE 1. FIGURE 3 illustrates a block diagram of an arbitrary register array bit position 302 within the register array 106. The register array bit position 302 may be any of the bits b3 i-bø within any of the registers 108-114 in FIGURE 1.

As shown in FIGURE 3, a bit load 304, in response to a bit select signal 116, can cause a source bit n (0 < n < 7, in the preferred embodiment) to be placed into the register array bit position 302. A word load 306, in response to a word select control signal in combination with a load control signal, can cause a word from a parallel load bus 308 to be placed in the particular word register, or row, containing the register array bit 302. A word read 310, in response to a word select control signal in conjunction with a read control signal, can cause a word to be written to a read bus 312. Hence, because of the word load 306 and the word read 310, there is random access to the registers 108-114, or rows, within the register array 106. Moreover, there is random access to bits b3i-bo within the set of registers 108-114, or rows, as a result of the bit load 304 to the register array bit position 302.

In accordance with another feature of the present invention, the orthogonal rotator can permit clearing of either all registers simultaneously or individual registers. The bit control/decode logic 104 can cause clearing of all registers 108-114 in a simultaneous fashion. Such a total clearing function may be desirable for initialization purposes, for example. For this type of clearing, the entire orthogonal rotator 100 may be pre-loaded via a single instruction (not shown) to the bit control/decode logic 104. In addition, clearing of individual registers may be performed via the word control/decode logic 148. In the context of this document, "clearing" means that a register(s), or row(s), is filled with the same state (either 1 or 0) of the source bit n, which is channeled to the register.

FIGURE 4 illustrates the methodology of the present invention to be implemented in the architecture shown in FIGURE 1. As indicated in FIGURE 4, orthogonal rotation and vertical mirroring is essentially accomplished by the order in which source data bytes are loaded from the source bit map 102 into the register array 106 and by the order in which data words are read from the register array 106 into the destination bit map 122. , , shown in FIGURE 2(a), the control logic 104 loads each data byte 124-130 from the source bit map 102 into the columns of the register array 106 by beginning with the column (LSB column) having the LSB position of each register row 108-114 and ending with the column (MSB column) having the MSB position of each register row 108-114. Furthermore, data words (1 word=4 bytes) are then read from the register array 106 beginning with the MSW in the bottom register 114 and ending with the LSW in the top register 108. The foregoing methodology is indicated in flow chart blocks 404,406, and 408 of FIGURE 4. It should be noted that the 90° rotation without vertical mirroring could have been performed by first multiplexing the source data bits in the reverse order than what is shown in FIGURE 1, by then loading the bytes into the columns of the register array 106 by beginning with the LSB column and ending with the MSB column, and by finally reading the data words from the top register 108 to the bottom register 114. In essence, reversing the order of the source bits takes care of having to read the data words from the bottom register 114 to the top register 108. The preceding methodology is also equally applicable to the discussion which follows further below in regard to a 270° rotation with vertical mirroring.

In order to achieve a 90^° rotation with vertical mirroring, as shown in FIGURE 2(c), data bytes are loaded into the register array 106 beginning with the LSB column and ending with the MSB column. Further, data words are then read from the register array 106 beginning with the LSW in the top register 108 and ending with the MSW in the bottom register 114. The foregoing methodology is indicated in blocks 404, 406, and 410 of FIGURE 4. To accomplish a 270^° rotation without vertical mirroring, as shown in

FIGURE 2(b), data bytes are loaded into the register array 106 by beginning with the MSB column and ending with the LSB column. Then, data words are read from the register array 106 beginning with the LSW in the top register 108 and ending with the MSW in the bottom register 114. The foregoing methodology is indicated in blocks 404,412, and 414 of FIGURE 4.

In order to effectuate a 270° rotation with vertical mirroring, as shown in FIGURE 2(d), data bytes are loaded into the register array 106 by beginning with the MSB column ^"and ending with the LSB column. Then, data words are read from the register array 106 beginning with the MSW in the bottom register 114 and ending with the LSW in the top register 108. The foregoing methodology is indicated in blocks 404, 412, and 416 of FIGURE 4.

Another advantage of the present invention is that the orthogonal rotator 100 may be used in combination with a simple horizontal mirroring system which can effectively rotate a bit map region by an angle of 180°, to thereby provide for all rotations in increments of 90°. A horizontal mirroring system for this purpose is taught in a copending application entitled, "Pixel Modification Unit", with Serial No. CAttv Docket SP029). which is incorporated by reference as if set forth in full here nbelow.

Although the preferred embodiment of the present invention has been described in detail above, those skilled in the art will readily appreciate the many additional modifications and applications that are possible without materially departing from the novel teachings of the present invention. For example, a register array 106 could be constructed, still in accordance with the teachings of the present invention, with a greater or lesser number of rows (registers) and/or columns (number of outputted bits) than was described in regard to the preferred embodiment. As another example, the source bits could be controllably multiplexed to the register array 106 so as to ehminate the need for reading the array in a particular manner, while still effectuating the orthogonal rotations. Accordingly, all such modifications and applications are intended to be included within the scope of the present invention, as defined within the following claims.

Claims

ClaimsThe inventors claim the following:

1. A system for orthogonally rotating a source data region in a source bit map of a graphics processor, comprising: register array means having rows and columns of bit locations; and bit control means for controlling said register array means to read source data bytes into said columns, said control means for loading said rows in the order from the right column to the left column in the case of a 90-degree orthogonal rotation, and for loading said rows in the order from the left column to the right column in the case of a 270-degree orthogonal rotation; and word control means for reading said rows into a destination bit map, said word control means for reading from the bottom row to the top row of said register array means so as to effectuate said 90-degree orthogonal rotation of said source data region, and for reading from the top row to the bottom row so as to effectuate said

270-degree orthogonal rotation of said source data region.

2. The system of claim 1, wherein said bit control means loads said columns in the order from the left column to the right column in the case of said 90-degree orthogonal rotation so as to effectuate vertical mirroring in combination with said 90-degree rotation.

3. The system of claim 1, wherein said bit control means loads said columns in the order from the right column to the left column in the case of said 270-degree orthogonal rotation so as to effectuate vertical mirroring in combination with said 270-degree rotation.

4. The system of claim 1, further comprising: bit-splicing means for channeling each bit of said source data bytes to an exclusive row of said register array means; and bit select decode means for receiving a control signal from said graphics processor and in response, for enabling only a single bit location within all of said rows to be loaded with the corresponding source data bit channelled to the respective row.

5. The system of claim 1, wherein said register array means comprises eight 32-bit registers, each of said registers corresponding to one of said rows.

6. A method for orthogonally rotating a source data region from a source bit map in a graphics processor, comprising the steps of: loading source data bytes into columns of a matrix array comprised of parallel registers forming rows, loading said data bytes from the right column to the left column in ^"the case of a 90-degree orthogonal rotation, loading said data bytes from the left column to the right column in the case of a 270-degree orthogonal ' rotation; reading data words from said matrix array in the order starting from the register in the bottom row and ending at the register -in the top row so as to effectuate a 90° orthogonal rotation of said source data region; and reading said data words from said matrix array in the order starting from the register in the top row and ending at the register in the bottom row so as to effectuate a 270° orthogonal rotation of said source data region.

7. The method of claim 6, further comprising the step of loading said data bytes from the left column to the right column so as to effectuate vertical mirroring in combination with said 90-degree orthogonal rotation.

8. The method of claim 6, further comprising the step of loading said data bytes from the right column to the left column so as to effectuate vertical mirroring in combination with said 270° orthogonal rotation.

9. The method of claim 6, further comprising the steps of: channeling each bit of said source data bytes to an exclusive row of said matrix array; and enabling only a single bit location within all of said rows to be loaded with the corresponding source data bit channelled to the respective row.