WO1994001922A1

WO1994001922A1 - Electrical power generation system

Info

Publication number: WO1994001922A1
Application number: PCT/US1993/006101
Authority: WO
Inventors: P. John Dhyanchand; Vietson M. Nguyen
Original assignee: Sundstrand Corporation
Priority date: 1992-07-09
Filing date: 1993-06-28
Publication date: 1994-01-20
Also published as: US5317498A

Abstract

An electrical power generation system (10) for generating a controlled AC output including a generator (14) for converting mechanical input into variable frequency AC, a rectifier (16) for rectifying the AC into DC having a variable magnitude, an inverter (24) for inverting the DC into a controlled AC output, a feedforward sensor (22a and 22b) for sensing the rate of change of the DC, a feedback AC sensor (58a, 58b and 58c) for sensing the controlled output AC, and an inverter controller (52) responsive to the rate of change of the DC and to the controlled AC output for regulating the magnitude of the controlled AC output.

Description

ELECTRICAL POWER GENERATION SYSTEM

BACKGROUND OF THE INVENTION

The present invention relates to an electrical power generation system of the type having an electrical generator for generating DC and wherein a variable parameter relating to the generated DC is sensed in a feedforward approach in order to control the output of an inverter which inverts the DC into controlled AC. Copending patent application (3800) discloses an inverter control system which senses both a variable parameter relating to the DC input supplied to an inverter and the output of the inverter in order to control that output. That system is particularly useful in electrical power generation systems such as those employing permanent magnet generators driven by variable speed devices for supplying variable frequency electrical power to a variable speed, constant frequency (VSCF) system. As the variable speed device varies its speed, the frequency of the output from the generator varies. In a VSCF system, the variable frequency output from the generator is rectified to produce DC. If the frequency of the input to the rectifier varies, the voltage level of the DC output of the rectifier will vary. The DC voltage supplied by the rectifier in such an electrical power generation system can vary by 2:1 or more. Because a normal inverter system for inverting such DC into AC output has time delays associated with the inverter, with the inverter controller and with any filters used in the inverter system, the control of the output AC by a VSCF system in response to changes in the input DC is delayed.

Copending patent application, having serial number 454,434 filed on December 20, 1989 and assigned to the same assignee as the present application, discloses an inverter system for providing a stepped output utilizing plural inverters. The system shown therein responds to the AC output for controlling the phase between the inverter outputs in order to control the AC output. A stepped inverter is also shown in United States Patent 3,775,662. Such a stepped-waveform inverter generates an output having a stepped shape that generally approximates a sine wave. The purpose of approximating a sine wave is to reduce the size of the filters provided at the output of the inverter that are used to remove unwanted harmonics. Such systems use feedback to control the inverter output, but often there is a generator control loop as well in order to regulate the input DC supplied to the inverter. Systems of the type shown in copending patent application 454,434 filed on December 20, 1989 can be used with the present invention, although the present invention can be used with other inverters as well. If the DC supplied to the inverter can be sensed and used as a control input, the response time for controlling the AC supplied by the inverter can be made much faster and control of the output AC does not have to be delayed as a result of the time delays inherent in such systems. Moreover, sensing the input DC in a feedforward approach also permits omission of the generator loop.

SUMMARY OF THE INVENTION

Accordingly, the present invention relies upon a feedforward approach by sensing a parameter relating to the input DC in order to allow for faster compensation for changes in this parameter. The present invention includes an electrical generation means for providing input DC which varies in magnitude, an inverter for inverting the input DC into controlled output AC, a feedforward sensor for sensing the parameter, a feedback sensor for sensing the controlled output AC, and an inverter controller for controlling the inverter in response to the feedforward sensor and the feedback sensor such that the output of the inverter may be controlled. The electrical generation means may be an electrical generator for providing a variable frequency output and a rectifier for supplying the DC responsive to the variable frequency output of the electrical generator. In another aspect of the invention, a method for controlling an inverter which receives input DC from an electrical generator includes the steps of sensing a variable parameter relating to input DC in order to provide a feedforward sensing signal varying in accordance with the varying parameter, sensing the output AC supplied by the inverter in order to provide a feedback signal varying in accordance with the output AC, and controlling the inverter in response to the feedforward signal and the feedback signal.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages will become more apparent from a detailed consideration of the invention when taken in conjunction with the drawings in which:

Figure 1 is generalized block diagram of an inverter system incorporating the present invention;

Figure 2 is a block diagram illustrating the manner in which the inverter of Figure 1 is controlled;

Figure 3 is a block diagram of the inverter of Figure 1;

Figure 4 is a circuit diagram of a first subinverter pair and their associated transformers of the inverter of Figure 3;

Figure 5 is a circuit diagram of one of the activation circuits of the inverter of Figure 3;

Figure 6 illustrates a first-phase relationship of a niamber of waveforms generated by the inverter and a waveform produced by the summation of those waveforms;

Figure 7 illustrates a second-phase relationship of a number of waveforms generated by the inverter and a waveform produced by the summation of those waveforms; Figure 8 illustrates a third-phase relationship of a number of waveforms generated by the inverter and a waveform produced by the summation of those waveforms; Figures 9a-9c are vector diagrams illustrating the operations of the inverter;

Figure 10 illustrates various waveforms relating to the operation of the phase-angle control circuit of Figure 3; Figure 11 is a circuit diagram of the phase-angle control circuit shown schematically in Figure 3;

Figure 12 is a circuit diagram of the sensing circuit shown schematically in Figure 3; Figure 13 is a graph of a voltage signal used in the phase-angle control circuit to control the phase relationship of the waveforms generated by the inverter; and,

Figures 14a and 14b illustrate the manner of generating a constant phase angle between the subinverter pair waveforms of the inverter.

DETAILED DESCRIPTION

A block diagram of a preferred embodiment of the power generation system 10 incorporating the present invention as shown in Figure 1. This power generation system includes a prime mover 12, such as the engine of an aircraft, for driving a generator 14 for providing a wild frequency AC output. Generator 14 may be of the permanent magnet type having permanent magnet 3 driven by an output shaft from prime mover 12 through disconnects 6 and 7. Prime mover 14 also includes pickups 4 for providing thre^-phase AC wild frequency output to rectifier 16. ι_cFilters 5 may be included for filtering undesired components of the electrical waveforms supplied by pickups 4.

Rectifier 16 is a full wave rectifier having a pair of rectifiers for each phase from generator 14 together with a smoothing capacitor for supplying DC to inverter 24. Inverter 24 inverts the DC into PWM pulses arranged to provide sinusoidal AC having a controlled magnitude. Filter 26 filters the pulses for providing three-phase output AC of controlled frequency and magnitude. The input DC supplied to inverted 24 from rectifier 16 is also sensed over lines 22a and 22b by a feedforward sensing arrangement comprising amplifier 12, high pass filter 14 and conditioning circuit 16 to provide a feedforward signal on line 15. Specifically, differential amplifier 12 provides an output depending upon the difference in DC between lines 22a and 22b. This difference signal is supplied through high pass filter 14 which provides an output dependent upon the rate at which transients in the DC occur. The output from high pass filter 14 can be conditioned by conditioning circuit 16, if desired, to provide a feedforward signal on line 15 for use by the inverter control system. Thus, the signal on line 15 varies in accordance with the rate of change of the DC voltage on lines 22a and 22b but may vary in any other desired relationship wherein the signal on line 15 is continuous or at least has multiple point-? each having a corresponding level of DC voltage on lines 22a and 22b.

Although the system shown in Figure 1 senses the voltage of the DC supplied by rectifier 16, it could alternatively sense the frequency of the ourput of generator 14 since the DC voltage from rec ier 16 will have a value dependent upon the frequency of the AC supplied by generator 14. Thus, either the frequency of the AC supplied by generator 14 or the DC voltage or the rate of change of the DC voltage supplied by 16 can be parameters related to the DC supplied to inverter 24.

Without feedforward control, changes in DC must pass through the inverter, the inverter controller and any possible filters before the output AC of inverter 24 can be regulated in response to those changes. Because of the time constants associated with the inverter, the inverter controller and filters, the controller responds slowly to changes in DC. By using the feedforward approach disclosed herein, however, changes in input DC can be sensed and used to provide much faster inverter control response.

As shown in Figure 2, inverter 24 includes an inverter control system which senses the phase voltage at the point of reference (POR) near the loads which are supplied power by inverter system 10. The phase voltages can be conditioned by signal conditioning circuit 11 and the output of signal conditioning circuit 11 is used as one input to summing junction 17. The phase current, on the other hand, is sensed at the output from the summing transformers. Signal conditioning circuit 13 provides the V/I response as shown in Figure 2. This arrangement is designed to provide a voltage to summing junction 19 only when the phase current exceeds two per unit phase current units. These units can be of any chosen value, but, for illustra¬ tion purposes only, a value of 58A per unit is suitable for the 20 KVA design shown herein. Summing junction 19 receives a reference voltage signal V^ in order to establish a set point voltage for the voltage at the point of reference. The output of summing junction 19 is connected as a further input to summing junction 17. Summing junction 17 also receives an input 15 from the feedforward input DC sensor as shown in Figure l. The output of summing junction 17 is used as an input to compensator 21 which provides signal level gain, lead and lag adjustment and buffering before it is supplied to logic arrangement 23. Logic circuit 23 controls the inverters in the way illustrated more fully hereinbelow. Logic circuit 23 also receives soft start input from soft start circuit 25 such that the output AC supplied to POR is gradually increased to the desired level in order to eliminate damaging inrush current transients that might occur by bringing the output AC up to the desired level too rapidly.

Furthermore, a hall-effect sensor is used if desired for sensing the DC current in DC lines 22a and 22b. Current protection circuit 27 senses an overcurrent condition in the input DC current and will operate through logic 23 for turning off inverter 24 during periods of overcurrent.

One arrangement for the circuits shown in Figure 2 is illustrated in Figures 3-14. As shown in Figure 3, inverter 24 includes four subinverter pairs 30, 32, 34, and 36. Each of the subinverter pairs 30, 32, 34, and 36 is coupled to a respective transformer pair 31, 33, 35, and 37. The output subinverter pairs 30, 32, 34, and 36 receive input DC from input DC lines 22a and 22b. Output lines 28a, 28b, and 28c interconnect the transformer pairs, and the transformer pair 37 is connected to neutral line 28d. Each of the subinverter pairs 30, 32, 34, and 36 is controlled by a respective activation circuit 40a, 40b, 40c, and 40d.

A regulator circuit for regulating the voltage at the POR is shown in Figure 3 to comprise a sensing circuit 50 and phase-angle control circuit 52. Sensing circuit 50 senses the current on the three transformer output lines 28a, 28b, and 28c via three lines 56a, 56b, and 56c which may be connected to corresponding current transformers around respective transformer output lines 28a, 28b, and 28c. Sensing circuit 50 senses the voltage on the three phase output lines from filter 26 at the point of reference (POR) by way of three lines 58a, 58b, and 58c. Sensing circuit 50 generates phase control signal φ_c having a magnitude based on both the voltage at the point of reference and the current sensed on lines 28a, 28b, and 28c and provides the φ. signal to the phase control circuit 52 by way of line 60. Based on the magnitude of φ_c, the phase-angle control circuit 52 causes the phase angle between the waveforms generated by the first and second subinverter pairs 30, 32 and the waveforms generated by the third and fourth subinverter pairs 34, 36 to be varied. As a result of the control of the phase angle, the voltage at POR is regulated.

Alternatively, instead of sensing the output AC at the point of reference, the regulator circuit 50 could sense the AC output on lines 28a, 28b, and 28c before the output from transformer pairs 31, 33, 35, and 37 is filtered by filter 26.

Phase control signal φ_c is also dependent upon input 15 to sensing circuit 50. That is, signal φ_c responds to the feedforward signal on input 15 in order to anticipate changes at the point of reference resulting from a rate of change in input DC on lines 22a and 22b.

Phase angle control circuit 52 varies the magnitude of the phase angle between the waveforms from subinverter pairs 30, 32 and the waveforms from subinverter pairs 34, 36 by generating reset signal RES3 based upon the magnitude of phase control signal φ_c and reference signal REF1. Signal REF1 is

to phase angle control circuit 52 from Activation circuit 40a by way of line 66. Signal J^ES3 is transmitted from phase angle control circuit 93 to activation circuit 40c by way of line 70. As described in more detail below, signal RES3 controls the phase angle between the waveforms generated by first and second subinverter pairs 30, 32 and the waveforms generated by third and fourth subinverter pairs 34, 36. Activation circuit 40a generates reset signal RES2 which is transmitted to activation circuit 40b by way of line 68, and activation circuit 40c generates reset signal RES4 which is transmitted to activation circuit 40d by way of line 72. As described in more detail below, signal RES2 causes the phase angle between the waveforms from first and second subinverter pairs 30 and 32 to be fixed and signal RES4 causes the phase angle between the waveforms from third and fourth subinverter pairs 34 and 36 to be fixed.

First subinverter pair 30 and first transformer pair 31 are shown in Figure 4, it being understood that subinverter pairs 32, 34, and 36 and transformer pairs 33, 35, and 37, may be similar. First subinverter pair 30 includes two subinverters 30a and 30b and first transformer pair 31 includes three-phase transformers 31a and 31b-

Subinverter 30a includes six transistor switches 82a, 82b, 82c, 84a, 84b, and 84c, each of which has a diode connected thereacross.

Subinverter 30a is connected to three wye-connected primary windings 80a, 80b, and 80c of transformer 31a which are controlled by the three pairs of switches 82a-c and 84a-c. The upper terminal of winding 80a is connected to the junction of switches 82a, 84a; and the upper terminal of winding 80b is connected to the junction of switches 82b and 84b; and the upper terminal of winding 80c is connected to the junction of switches 82c and 84c. Primary windings 80a-c of transformer 31a are magnetically coupled to three secondary windings 90a, 90b, and 90c, respectively.

During operation of subinverter 30a, one of the t* switches in each vertical branch is conduct.. In particular, one of two switches 82a and 84a is conducting and the other is off; one of tfc itches 82b and 84b is conducting and the other is Xf ; and, one of the switches 82c and 84c is conducting and the other is off. Switches 82a-c and 84a-c are switched in a conventional manner to generate waveform 220 shown in Figure 6 on each of the three wye-connected windings 80a, 80b, and 80c. Eac. of the three waveforms 220 differ in phase by 120^s1. Because windings 80a-c are wye-connected, waveform 220 has four possible amplitudes +A, +A/2, -A/2, and -A, where A is the maximum amplitude. Subinverter 30b includes six transistor switches 94a, 94b, 94c, 96a, 96b, and 96c, each of which has a diode connected across it. Subinverter 30b is connected to three delta-connected primary windings 92a, 92b, and 92c of transformer 31b which are controlled by three pairs of the switches 94a-c and 96a-c. The upper terminal of winding 92a is connected to the junction of switches 94a and 96a; the upper terminal of winding 92b is connected to the junction of switches 94b and 96b; and, the upper terminal of winding 92c is connected to, the junction of switches 94c and 96c. The three delta-connected primary windings 92a-c are magnet¬ ically coupled to three secondary windings 98a-c of transformer 31b, respectively. Secondary winding 98a is connected in series with secondary winding 90a in line 28a, secondary winding 98b is connected in series with secondary winding 90b in line 28b, and secondary winding 98c is connected in series with secondary winding 90c in line 28c.

Switches 94a-c and 96a-c are switched in a manner similar to switches 82a-c and 84a-c to generate waveform 222 in Figure 5 on each of the three delta-connected windings 92a, 92b, and 92c. Each of the three waveforms 222 have a phase difference of 120° with respect to one another. Be¬ cause the windings are delta-connected, such a waveform has three possible amplitudes, +A, 0, and -A, where A is the maximum amplitude. While switches 82a-c, 84a-c, 94a-c, and 96a-c are shown to be transistors, other types of switches maybe used, such as gate turn off devices or darlington-connected transistor pairs. The circuit diagrams for the second, third, and fourth subinverter pairs 32, 34, and 36 and the second, third, and fourth transformer pairs 33, 35, and 37 can be identical to the one shown in Figure 3 and are not shown separately for purposes of simplicity.

The activation of the 12 switches 82a-c, 84a-c, 94a-c, and 96a-c in each of the subinverter pairs is controlled by a respective one of the activation circuits 40a, 40b, 40c, and 40d. Since the four activation circuits can be identical, only one is shown in Figure 5. Activation circuit 40 includes three four-bit counters 110, 112, and 114 connected to EPROM 116 which is connected to driver circuit 118. Counters 110, 112, and 114 are driven by clock signal CLK generated by a main controller (not shown) . The carry output of counter 110 is used as an input to counter 112 by way of line 111, and the carry output of counter 112 is used as a carry input to counter 114 by way of line 113. Upon each pulse of the CLK signal, the ten-bit output of counters 110, 112, and 114 is incremented by one. This 10-bit output is used as an address for EPROM 116.

EPROM 116 has a six-bit binary code stored in each of its address locations. The six binary bits control the activation of the twelve switches in one of the subinverters. In particular, one bit of the six-bit binary code is output on the line 122 to the driver 118, which driver generates a pair of complemented switching signals on line 124 and line 126. Line 124 is connected to the base of one switch in one vertical branch of one of the subinverters, such as switch 82a, and line 126 is connected to the base of the other switch in that vertical branch, such as switch 84a. The remaining 5 bits of the six-bit binary code are output on lines 130, 132, 134, 136, and 138, respectively, to driver circuit 118 which driver circuit generates on its outputs a pair of complemented driving signals for each of the five binary signals. These driving signals are supplied to respective pairs of the remaining switches of the subinverter.

During operation of activation circuit 40, as the CLK signal periodically increments counters 110, 112, and 114, the six bits of the binary code are periodically output from EPROM 116 via lines 122 and 130-138 to driver 118, and the twelve switches of each of the subinverters 30a, 30b, 32a, 32b, 34a, 34b, 36a, and 36b are controlled to generate waveforms 220, 222, 224, 226, 228, 230, 232, and 234 shown in Figure 6 in the primary windings in each of the transformers 31a, 31b, 33a, 33b, 35a, 35b, 37a, and 37b, respectively.

EPROM 116 generates a first reference signal REFA on line 142 and second reference signal REFB on line 144. Reset signal RES may be input to counters 110, 112, and 114 by way of line 140. When the RES signal is activated, counters 110, 112, and 114 are reset, thus providing a ten-bit address to EPROM 116 equal to zero. The contents of each EPROM in the four activation circuits 40a, 40b, 40c, and 40d can be identical. If each of the EPROMS is given the same sequence of addresses, the resulting waveforms generated by the subinverters would be identical and thus have zero phase angle. Accordingly, the time of reset of counters 110, 112, and 114 of one activation circuit determines the phase angle between the waveforms generated by that activation circuit and the waveforms generated by the other activation circuits.

When activation circuit 40 of Figure 5 is used for the activation circuit 40a shown in Figure 3, the REFA line 142 of Figure 5 is connected to REF1 line 66 of Figure 3, and REFB line 144 of Figure 5 is connected to RES2 line 68 of Figure 3. When activation circuit 40 of Figure 5 is used for activation circuit 40b, RES line 140 of Figure 5 is connected to RES2 line 68 of Figure 3, and REFA and REFB lines 142 and 144 of Figure 5 are not used. When activation circuit 40 of Figure 5 is used for activation circuit 40c shown in Figure 3, REFB line 144 of Figure 5 is connected to RES4 line 72 of Figure 3, REFA line 142 of Figure 5 is not used, and RES line 140 of Figure 5 is connected to RES3 line 70 in Figure 3. When activation circuit 40 of Figure 5 is used for activation circuit 40d, RES line 140 of Figure 5 is connected to RES4 line 72 of Figure 3, and REFA and REFB lines 142 and 144 of Figure 5 are not used.

Stepped waveform inverters having eight subinverters as shown in Figure 3 are referred to as 48-step inverters, although the invention applies equally well to 24-step inverters using two subinverter pairs or a 36-step inverter using three subinverter pairs.

In Figure 6, the waveforms generated by subinverters 30a, 30b, 32a, 32b, 34a, 34b, 36a, and 36b in primary windings of the transformers 31a, 31b, 33a, 33b, 35a, 35b, 37a, and 37b are shown.

The summing transformer output waveform 240, which is the last waveform shown in Figure 6, is generated on each of the three transformer output lines 28a, 28b, and 28c with each of the three waveforms 240 being 120° apart.

In the operation of the inverter, the phase angle between the waveforms generated by first and second subinverter pairs 30 and 32 and the waveforms generated by third and fourth subinverter pairs 34 and 36 is varied depending upon the voltage at the POR and the level of the parameter relating to the input DC on lines 28a and 22b.

Figures 6-8 illustrate the various phase relationships of the subinverter waveforms during operation of inverter 24. In Figures 6-8, the phase angle between the first subinverter pair waveforms 220 and 222 and the second subinverter pair waveforms 224 and 226 is fixed at 15°. Likewise, the phase angle between the third subinverter pair waveforms 228 and 230 and the fourth subinverter pair waveforms 232 and 234 is fixed at 15°. However, the phase angle between waveforms 220, 222, 224, and 226 produced by the first and second subinverter pair waveforms and the waveforms 228, 230, 232, and 234 produced by the third and fourth subinverter pairs is variable. For example, this variable phase angle is 15° in Figure 6, 120° in Figure 7, and 180° in Figure 8. The resultant output voltage may be regulated by controlling the phase angle between the first and second subinverter pair waveforms and the third and fourth subinverter pair waveforms. For example, waveform 240 has a peak positive amplitude of +160V and a peak negative amplitude of -160V in Figure 6, a peak positive amplitude of +80V and a peak negative amplitude of -80V in Figure 7, and a 0 amplitude in Figure 8. In Figures 9a-9c, the vector diagrams in those figures illustrate these modes of operation. Vector V, represents the first subinverter pair wave¬ forms 220 and 222; vector V₂ represents the second subinverter pair waveforms 224 and 226; vector V₃ represents the third subinverter pair waveforms 228 and 230; and, vector V₄ represents the fourth subinverter pair waveforms 232 and 234. The phase angle between V, and V₂ is held at a constant 15° as is the phase angle between V₃ and V₄. The phase angle between V, and V₃ (and consequently between V₂ and V₄) , however, is variable. This variable phase angle can vary, for example, from 15° as shown in Figures 6 and 9a, to 120° as shown in Figures 7 and 9b, to 180° as shown in Figures 8 and 9c. One manner of controlling the variable phase angle between the first and third subinverter pair waveforms is illustrated in Figure 10. In Figure 10, waveform 220 generated in first subinverter wye-connected windings 80a-c is shown in its phase relationship with respect to REF1. As can be seen, REF1 changes from zero to positive when waveform 220 transitions to a positive amplitude and from positive to zero when waveform 220 transitions to a negative amplitude. Signal RAMP is generated based upon the magnitude of signal REF1. When signal REF1 is positive, the amplitude of signal RAMP slowly increases. When the magnitude of signal REF1 changes to zero, the magnitude of RAMP quickly decreases to zero.

Signal RAMP is used to generate signal RES3 based on a phase control signal φ_Λ generated from phase control signal φ_e of Figure 3. The magnitude of signal Φ varies, depending upon the magnitude of the voltage sensed at the POR, the current sensed on lines 28a-c and the voltage sensed on DC link 22a, 22b. The relative values of RAMP and Φ_e3 are used to genera a comparison signal COMP having a positive amplitude when the value of signal RAMP is greater than the value of φ_a and a zero amplitude when the value of signal RAMP is less than the value of signal Φ . The point of intersection of the rising portion of signal RAMP and signal φ^ determines the magnitude of the phase delay between the subinverter waveforms 220 and 228. This intersection point is shown as point 260 in Figure 10.

At the intersection point 260, signal COMP changes from zero to a positive amplitude. The rising edge of signal COMP triggers signal RES3 to become positive, or activated. When signal RES3 is activated, it resets the counters associated with third subinverter pair 34. As a result, the counters produce a zero ten-bit address, and the corresponding EPROM initiates generation of waveform 228.

The contents of the EPROM associated with each subinverter pair 30, 32, 34, and 36 can be identical. If each of the EPROMs is given the same sequence of addresses, the resulting waveforms would be identical and have zero phase angle difference. Accordingly, the time of reset of the counters associated with each activation circuit determines the phase angle between the waveforms associated with that activation circuit and the waveforms associated with the other activation circuits.

Thus, with respect to Figure 10, the time occurrence of the rising edge of signal RES3 controls the phase difference between waveform 220 and waveform 228.

It should be appreciated that the magnitude of signal φ_ά determines the magnitude of the phase delay between waveforms 220 and 228. If the magnitude of signal Φ is larger, signal φ_a will intersect the signal RAMP later thus causing a larger phase delay. If the magnitude of signal φ_ά is smaller, signal φ_a will intersect the signal RAMP earlier causing a smaller phase delay.

One phase angle control circuit 52 for accomplishing the control of the variable phase angle between subinverter pairs 30 and 32 and subinverter pairs 34 and 36 (i.e., between waveform 220 and waveform 228) is shown in Figure 11. The REF1 and φ. signals are supplied to phase angle control circuit 52 by way of lines 66 and 60, respectively, and circuit 52 generates signal RES3 on line 70. In Figure 11, circuit 52 includes a RAMP generator comprising comparator 302 having an inverting input which receives signal REF1 and a noninverting input that receives a predetermined reference voltage. The RAMP signal generator also includes transistor 304, capacitor 306, and a constant current source comprising operational amplifier 308 and transistor 310. Capacitor 306 is slowly charged by the constant current source through transistor 310 when transistor 304 is nonconducting and is quickly discharged through transistor 304 when transistor 304 becomes conductive. Transistor 304 conducts when the value of the signal REF1 is less than the predetermined voltage provided at the noninverting input of comparator 302. As a result, the signal RAMP is produced on line 312. The signal RAMP is input to the noninverting input of comparator 314 by way of line 312. The inverting input of comparator 312 is supplied with signal φ_a having a magnitude based upon signal φ_e. Comparator 314 generates on line 316 a comparison signal COMP having a high output when the value of the RAMP signal is greater than φ_ύ and a low output when the value of the RAMP signal is less than the value of φ^. The comparison signal on line 316 is provided to a monostable multivibrator or one shot 318 comprising three inverters and a capacitor. The output of one shot 318 provides signal RES3 which determines the phase angle between the waveforms of the first subinverter pair 30 and the third subinverter pair 34 (and consequently also the phase angle between the waveforms of the second subinverter pair 32 and the fourth subinverter pair 36) . The magnitude of φ^ is determined by amplifier 350 and Zener diode 352 shown in Figure 11. Amplifier 350 acts as a voltage follower. The output of amplifier 350 follows the magnitude of signal φ_t. Zener diode 352 is connected to the output of amplifier 350 and acts to limit the magnitude of signs., _c3 to a maximum predetermined value. This predetermined value is the voltage that causes the maximum phase angle difference of 180° between the waveforms of the first and third subinverter pairs. gnal φ_e is generated by sensing circuit 50 based upon the currents in lines 28a-c, the voltage at the point of reference, and the DC link voltage. Sensing circuit 50 is shown in detail in Figure 12. In Figure 12, sensing circuit 50 includes a first portion which generates a voltage based on the amount of current sensed in lines 56a, 56b, and 56c. The three phases of output current, I_φA, I_φB, and I_φc, on lines 56a, 56b, and 56c, respec¬ tively, are rectified by half-wave rectifier circuit 360. The output of half-wave rectifier circuit 360 is filtered by smoothing capacitor 362 and then provided to the inverting input of operational amplifier 364 used for scaling purposes. The output of operational amplifier 364 is passed through Zener diode 366 which is coupled to the inverting input of operational amplifier 368 that acts as an inverter. The operational amplifier 368 generates a negative voltage, -I₀, that is zero if the amount of current sensed in lines 56a, 56b, and 56c is not above a predetermined threshold. As shown in Figure 2, this threshold is two units. If the current sensed is above the threshold, then the magnitude of -I₀ is proportional to the amount of current over the threshold. Signal -I₀ is transmitted to summing point 370 by way of line 372.

Precision full-wave rectifiers 390, 392, and 394 are connected to receive phase voltages V , V_B, and V^c from the point of reference POR. The rectified phase voltages are summed at the inverting input of operational amplifier 400. Operational amplifier 400 generates a negative voltage at its output, -V₀, which has a magnitude that is propor¬ tional to the average voltage sensed at POR. Signal -V₀ is transmitted to summing point 370.

Summing point 370 is also connected to circuit 402 which generates a predetermined reference voltage V,^. Voltage V_ref represents the desired voltage at which the transformer output at POR should be kept. Summing junction 370 also receives an input on line 15 representing the magnitude of the rate of change of the DC voltage on DC bus 22a, 22b. At the summing point 370, V^, -V₀, -I₀, and the rate of change of the input DC signal on line 15 are summed to produce an error signal, V_OT, which equals V^ +d_V(JC/dt -I₀ -V₀. In normal operation, when the magnitude of the summing trans¬ former output current is below the predetermined current threshold, the value of -I₀ will be zero, and the error signal will equal V^ +d_VdC/dt -V₀. However, if the output current exceeds the threshold, then I₀ will be a nonzero value and it will effectively reduce the magnitude of the predetermined voltage V^ at POR. If the current is large enough, the magnitude of I₀ will become as large as V^ +d_Vdc/dt nd the effective reference voltage V,^ +d_VdC/dt -I₀ will become zero. As a result, the actual voltage V₀ will be reduced to zero. The amount of sensed current necessary to reduce the effective reference voltage to zero is at 3 up as shown in Figure 2. Thus, when the current reaches this value, the c . cput voltage at the point of reference drops to zero. If V^ changes, the controller will change the phase angle between the waveforms of subinverters 30 and 34 to counteract the change in V_&. without having to wait through the system time constants. The summed error voltage at summing point 370 is provided as an input to the inverting input of operational amplifier 404 which integrates the error. Amplifier 404 is coupled to operational amplifier 406 that acts as a buffer and which produces signal φ_c which ultimately determines the phase angle between the waveforms generated by the first and third subinverter pairs 30 and 34.

In Figure 13, the magnitude of phase control signal φ_a with respect to signal φ. during operation of the inverter is shown. Signal φ_ά has a minimum voltage that produces a minimum phase angle of 15° between the waveforms of the first and third subinverter pairs 30 and 34. Signal φ^ has a maximum voltage that produces the maximum phase angle of 180°.

The manner of generating the fixed phase angle between the waveforms of the first and second subinverter pairs 30 and 32 is illustrated in Figure 14a. The fixed phase angle is determined by signal RES2 which determines the time of reset of the counters associated with second subinverter pair 32a and 32b. As shown in Figure 14a, signal RES2 is activated 15° after the beginning of waveform 220. Since the beginning of waveform 224 coincides with activation of signal RES2, waveform 224 begins at 15° as shown in Figure 14a. The manner of generating the fixed phase angle between the waveforms of the third and fourth subinverter pairs 34 and 36 is illustrated in Figure 14b. The fixed phase angle is determined by signal RES4 which determines the time of reset of the counters associated with the fourth subinverter pair 36a and 36b. As shown in Figure 14b, signal RES4 is activated 15° after the beginning of waveform 228. Since the beginning of waveform 232 coincides with the activation of signal RES4, waveform 232 begins at 15° as shown in Figure 14b.

As either the voltage at the point of reference POR or the voltage of the DC link 22a, 22b varies, the variable phase angle between waveform 220 and waveform 228 will be adjusted in order to maintain the voltage at the point of reference POR at the value determined by V„_f or the combination of V„_f and I₀ if I₀ is above its minimum value.

The fixed phase angle between waveforms 220 and 224 and between waveforms 228 and 232 could be generated in another manner. Instead of making the contents of the four EPROMs identical so that if all the EPROMs are reset at the same time the phase angle difference between the waveforms would be zero, the contents of the EPROM associated with the first subinverter pair 30 could be shifted with respect to the contents of the EPROM associated with the second subinverter pair 32 so that when both EPROMs were reset, a 15° phase angle between their respective waveforms would be produced. Similarly, the contents of the EPROM associated with the third subinverter pair 34 could be shifted with respect to the contents of the EPROM associated with the fourth subinverter pair 36 so that when both EPROMs are reset, a 15° phase angle between their respective waveforms would be produced. As a result, signals RES2 and RES4 would be unnecessary. Also, two of the four sets of counters associated with EPROMs could be eliminated since the remaining two sets of counters could each drive a pair of EPROMs.

It should be appreciated that another fixed phase angle between the first and second subinverter waveforms and between the third and fourth subinverter waveforms could be used. For example, instead of a fixed angle of 15°, 10° could be used. Modifications and alternative embodiments of the invention will be apparent to those skilled in the art in view of the foregoing description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teachings those skilled in the art the best mode of carrying out the invention. The details of the structure may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which come within the scope of the appended claims is reserved.

Claims

WHAT IS CLAIMED IS:

1. A system for providing controlled AC output comprising: electrical generation means for providing DC, said DC having a parameter relating thereto; inverter means connected to said electrical generation means for inverting said DC into said controlled AC output; feedforward parameter sensing means for sensing said parameter relating to said DC, said feedforward parameter sensing means providing a feedforward signal varying in accordance with said parameter; feedback AC sensing means for sensing said controlled AC output, said feedback AC sensing means providing a feedback signal varying in accordance with said controlled AC output; and, inverter control means connected to said inverter means, to said feedforward parameter sensing means, and to said feedback AC sensing means for controlling said controlled AC output in response to said feedforward signal and to said feedback signal.

2. The system of claim 1 wherein said inverter means comprises first inverter means for inverting said E id for producing a first inverter AC output h ing a first phase, second inverter means for inverting said DC and for produc¬ ing a second inverter AC output having a second phase, and c, ibining eans for combining said first inverter AC output an. said second inverter AC output into said controlled AC output, and wherein said inverter control means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon said feedforward signal and said feedback signal.

3. The system of claim 1 wherein said parameter relating to said DC rate of change of said DC and wherein said feedforward sensing means comprises rate sensing means for sensing said rate of change of said DC.

4. The system of claim 3 wherein said controlled AC output has a voltage component and wherein said feedback AC sensing means comprises voltage sensing means for sensing said voltage component of said controlled AC output.

5. The system of claim 4 wherein said inverter means comprises first inverter means for inverting said DC and for producing a first inverter AC output having a first phase, second inverter means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter AC output into said controlled AC output, and wherein said inverter control means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon said voltage of said DC and said voltage component.

6. The system of claim 4 wherein said inverter control means comprises comparator means for comparing said rate of change of said DC, said voltage component, and a reference voltage.

7. The system of claim 6 wherein said controlled AC output also has a current component and said feedback AC sensing means further comprises current sensing means for sensing said current component of said controlled AC output, said current sensing means providing an output current signal only when said current component of said controlled AC output exceeds a predetermined threshold, said comparator means also comparing said output current signal.

8. The system of claim 7 wherein said inverter means comprises first inverter means for inverting said DC and for producing a first inverter AC output having a first phase, second inverter means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter AC output into said controlled AC output, and wherein said inverter control means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon said voltage of said DC, and said voltage component and said current component.

9. A system for providing controlled AC output comprising: electrical generation means for converting mechanical input into electrical output having a variable frequency; rectifier means for rectifying said electrical output and for providing DC having a magnitude dependent upon said frequency; inverter means connected to said rectifier means for inverting said DC into said controlled AC output; feedforward sensing means connected to one of said electrical generation means and said rectifying means for sensing a parameter relating to said DC, said feedforward sensing means providing a feedforward signal varying in accordance with said parameter; feedback AC sensing means for sensing said controlled AC output, said feedback AC sensing means providing a feedback signal varying in accordance with said controlled AC output; and inverter control means connected to said inverter means, to said feedforward sensing means, and to said feedback AC sensing means for controlling said controlled AC output in response to said feedforward signal and to said feedback signal.

10. The. system of claim 9 wherein said inverter means comprises first inverter means for inverting said DC and for producing a first inverter AC output having a first phase, second inverter means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter AC output into said controlled AC output, and wherein said inverter control means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon said feedforward signal and said feedback signal.

11. The system of claim 10 wherein said electrical generation means comprises a permanent magnet generator.

12. The system of claim 9 wherein said feedforward sensing means is connected to said rectifier means and said parameter relating to said DC is rate of change of said DC and wherein said feedforward sensing means comprises rate sensing means for sensing said rate of change of said DC.

13. The system of claim 12 wherein said controlled AC output has a voltage component and wherein said feedback sensing means AC sensing means comprises voltage sensing means for sensing said voltage component of said controlled AC output.

14. The system of claim 13 wherein said electrical generation means comprises a permanent magnet generator. 15. The system of claim 13 wherein said inverter means comprises first inverter means for inverting said DC and for producing a first inverter AC output having a first phase, second inverter means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter Ac output into said controlled AC output, and wherein said inverter control means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon said voltage of said DC and said voltage component.

16. The system of claim 13 wherein said inverter control means comprises comparator means for comparing said rate of change of said DC, said voltage component, and a reference voltage.

17. The system of claim 16 wherein said controlled AC output also has a current component and said feedback AC sensing means further comprises current sensing means for sensing said current component of said controlled AC output, said current sensing means providing an output current signal only when said current component of said controlled AC output exceeds a predetermined threshold, said comparator means also comparing said output current signal.

18. The system of claim 17 wherein said inverter means comprises first inverter means for inverting said DC and for producing a first inverter AC output having a first phase, second inverter means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter AC output into said controlled AC output, and wherein said inverter control means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon said voltage of said DC, said voltage component, said current component, and said voltage reference.

19. The system of claim 18 wherein said electrical generation means comprises a permanent magnet generator.

20. The system of claim 9 wherein said electrical generation means comprises a permanent magnet generator. 21. A method for generating controlled output AC comprising the following steps: converting mechanical input to variable frequency AC; rectifying said variable frequency AC for providing DC; sensing rate of change of said DC; sensing the controlled AC output; and inverting said DC having said variable magnitude into controlled output AC in response to said rate of change of said DC and said controlled AC output.

22. The method of claim 21 wherein said controlled AC output has a voltage component and wherein said step of sensing said controlled AC output comprises the step of sensing the voltage component of said controlled AC output.

23. The method of claim 22 wherein said inverting step comprises the step of comparing said rate of change said DC, said voltage component of said controlled output AC and a reference, said reference establishing a desired level for said controlled AC output. AMENDED CLAIMS [received by the International Bureau on 15 November 1993 (15.11.93); original claims 1-21 amended; remaining claims unchanged (9 pagesj]

2. The system of claim l wherein said inverting means comprises first inverting means for inverting said DC and for producing a first inverter AC output having a first phase, second inverting means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter AC output into said controled AC output, and wherein said inverter controlling means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon the comparison of said feedforward signal and said feedback signal.

3. The system of claim 1 wherein said parameter related to said DC is related to a rate of change of said DC and wherein said feedforward sensing means comprises rate sensing means for sensing said rate of change of said DC.

5. The system of claim 4 wherein said voltage means produces an output voltage signal dependent upon said voltage component, wherein said inverting means comprises first inverting means for inverting said DC and for producing a first inverter AC output having a first phase, second inverting means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter AC output into said controlled AC output, and wherein said inverter controlling means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon said rate of change of said DC and said output voltage signal.

6. The system of claim 4 wherein said comparing means for comprises means for comparing said rate of change of said DC, said output voltage signal, and a reference voltage.

7. The system of claim 6 wherein said controlled AC output also has a current component and said feedback AC sensing means further comprises current sensing means for sensing said current component of said controlled AC output, said current sensing means providing an output current signal only when said current component of said controlled AC output exceeds a predetermined threshold, said means of said comparing means also comparing said output current signal to said rate of change of said DC, said output voltage signal, and said reference voltage.

8. The system of claim 7 wherein said inverting means comprises first inverting means for inverting said DC and for producing a first inverter AC output having a first phase, second inverting means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter AC output into said controlled AC output, and wherein said inverter controlling means comprising means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon said comparison of said rate of change of said DC, said output voltage signal, said reference voltage, and said output current signal.

9. A system for providing controlled AC output comprising: mechanical input converting means for converting a mechanical input into an electrical output having a variable frequency; rectifying means for rectifying said electrical output and for providing DC having a magnitude dependent upon said variable frequency; inverting means connected to said rectifying means for inverting said DC into said controlled AC output; feedforward sensing means connected to one of said mechanical input converting means and said rectifying means for sensing a parameter related to said DC, said feedforward sensing means providing a feedforward signal varying in accordance with said parameter; feedback AC sensing means for sensing said controlled AC output, said feedback AC sensing means providing a feedback signal varying in accordance with said controlled AC output; and, inverter controlling means connected to said inverting means, to said feedforward sensing means, and to said feedback AC sensing means for controlling said controlled AC output in response to said feedforward signal and to said feedback signal, said inverter controlling means including summing means for summing said feedforward signal and said feedback signal to produce a sum of said feedforward signal and said feedback signal.

10. The system of claim 9 wherein said inverting means comprises first inverting means for inverting said DC and for producing a first inverter AC output having a first phase, second inverting means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC out ^ut and said second inverter AC output into said co...rolled AC output, and wherein said inverter controlling means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon said sum of said feedforward signal and said feedback signal.

11. The system of claim 10 wherein said mechanical input converting means comprises a permanent magnet generator.

12. The system of claim 9 wherein said feedforward sensing means is connected to said rectifying means, wherein said parameter related to said DC is a rate of change of said DC, and wherein said feedforward sensing means comprises rate sensing means for sensing said rate of change of said DC.

13. The system of claim 12 wherein said controlled AC output has a voltage component and wherein said feedback AC sensing means comprises voltage sensing means for sensing said voltage component of said controlled AC output.

14. The system of claim 13 wherein said mechanical input converting means comprises a permanent magnet generator.

15. The system of claim 13 wherein said voltage sensing means produces an output voltage signal dependent upon said voltage component, wherein said inverting means comprises first inverting means for inverting said DC and for producing a first inverter AC output having a first phase, second inverting means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter Ac output into said controlled AC output, and wherein said inverter controlling means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon a sum of said rate of change of said DC and said output voltage signal.

16. The system of claim 13 wherein said summing means comprises means for summing said rate of change of said DC, said output voltage signal, and a reference voltage.

17. The system of claim 16 wherein said controlled AC output also has a current component and said feedback AC sensing means further comprises current sensing means for sensing said current component of said controlled AC output, said current sen ig means providing an output current signal onlj when said current component of said controlled AC output exceeds a predetermined threshold, said means of said summing means also summing said output current signal with said rate of change of said DC, said output voltage signal, and said reference voltage.

18. The system of claim 17 wherein said inverting means comprises first inverting means for inverting said DC and for producing a first inverter AC output having a first phase, second inverting means for inverting said DC and for producing a second inverter AC output having a second phase, and combining means for combining said first inverter AC output and said second inverter AC output into said controlled AC output, and wherein said inverter controlling means comprises means for controlling said controlled AC output by controlling said first and second phases with respect to one another by an amount dependent upon a sum of said rate of change of said DC, said out' it voltage signal, said output current signal, and said voltage reference.

19. The system of claim 18 wherein said mechanical input converting means comprises a permanent magnet generator.

20. The system of claim 9 wherein said mechanical input converting means comprises a permanent magnet generator.

21. A method for generating a controlled output AC comprising the following steps: converting mechanical input to variable frequency AC; rectifying said variable frequency AC for providing DC; sensing a rate of change of said DC; sensing the controlled AC output; and inverting said DC having said variable magnitude into controlled output AC in response to said rate of change of said DC and said controlled AC output.

23. The method of claim 22 wherein said inverting step comprises the step of comparing said rate of change said DC, said voltage component of said controlled output AC and a reference, said reference establishing a desired level for said controlled AC output.