WO1994012969A1 - Low-power-consumption monitor standby system - Google Patents

Low-power-consumption monitor standby system Download PDF

Info

Publication number
WO1994012969A1
WO1994012969A1 PCT/US1993/011579 US9311579W WO9412969A1 WO 1994012969 A1 WO1994012969 A1 WO 1994012969A1 US 9311579 W US9311579 W US 9311579W WO 9412969 A1 WO9412969 A1 WO 9412969A1
Authority
WO
WIPO (PCT)
Prior art keywords
monitor
signals
power
hsync
vsync
Prior art date
Application number
PCT/US1993/011579
Other languages
French (fr)
Inventor
Dan Kikinis
Original Assignee
Oakleigh Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26839089&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1994012969(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Oakleigh Systems, Inc. filed Critical Oakleigh Systems, Inc.
Priority to DE0672285T priority Critical patent/DE672285T1/en
Priority to JP6513444A priority patent/JP2847099B2/en
Priority to DE69325106T priority patent/DE69325106T2/en
Priority to EP94903345A priority patent/EP0672285B1/en
Publication of WO1994012969A1 publication Critical patent/WO1994012969A1/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G09G1/165—Details of a display terminal using a CRT, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G1/167—Details of the interface to the display terminal specific for a CRT
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00—Apparatus for electrographic processes using a charge pattern
    • G03G15/50—Machine control of apparatus for electrographic processes using a charge pattern, e.g. regulating differents parts of the machine, multimode copiers, microprocessor control
    • G03G15/5075—Remote control machines, e.g. by a host
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3218—Monitoring of peripheral devices of display devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3265—Power saving in display device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3284—Power saving in printer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers
    • G06K15/02—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers
    • G06K15/12—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers by photographic printing, e.g. by laser printers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/005—Power supply circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G09G1/165—Details of a display terminal using a CRT, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K2215/00—Arrangements for producing a permanent visual presentation of the output data
    • G06K2215/0082—Architecture adapted for a particular function
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/022—Power management, e.g. power saving in absence of operation, e.g. no data being entered during a predetermined time
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention is in the field of automatic power saving devices and pertains in particular to reduction of power consumption by computer video monitors.
  • a typical color video monitor may consume as much as 50 to 80 percent of the total electrical energy consumed by a personal computer (PC).
  • PC personal computer
  • a video monitor dissipates this energy as visible light emissions from screen phosphors, thermal waste, electromagnetic radiation, high- energy radiation and acoustic energy. Only the phosphor emissions are normally considered useful and then only when actively being watched by an observer. The radiation emissions have been a hotly debated source of concern regarding possible health risks from long-term exposure. Manufacturers incur considerable extra expense to reduce radiation emissions from video monitors. Some people are annoyed by the acoustic emissions produced by some monitors. Thermal losses from video monitors contribute an additional load on air conditioning equipment.
  • What is needed is a way to shut down high-energy- consuming circuits in the video monitor when the computer determines that the display may be of no interest to anyone. This might be determined by a period of inactivity on input devices such a modem, mouse and keyboard.
  • Many computers and video terminals use such a technique to activate a screen blanking circuit or a program that displays moving images (or no image) to avoid burning the screen phosphors. Activating an input device such as pressing a key or moving a mouse causes the previous screen image to be restored.
  • This technique can be extended to reduce video monitor power consumption by signalling the microcontroller found in many recent design monitors, or an add-on device for "dumb" monitors, to shut down or restore some or all of the monitor's electrical power circuits.
  • One key to accomplishing this end is a means of signalling a monitor to shut down to some selected level without adding to the signals presently provided to a monitor.
  • a system for a general purpose computer having a CPU, a memory means, a monitor, and video signal means for providing horizontal sync (HSYNC) and vertical sync (VSYNC) signals to the monitor, to signal the monitor to assume alternative states.
  • the system comprises timing means for measuring periods of inactivity configured to reset to zero on input interrupts and to provide overflow signals at preset overflow values, and sync disabling means for interrupting at least one of the HSYNC and VSYNC signals to the monitor according to overflow states of the timing means.
  • the video signal means comprises video adapter circuitry having a VSYNC generator and an HSYNC generator
  • the disabling means comprises a register associated with the video adapter circuitry, wherein one bit in the register is a vertical retrace polarity bit, and another bit is a horizontal retrace polarity bit.
  • the timing means is provided by the CPU following a monitor power management instruction routine stored in the memory means, and SYNC signals are disabled by the CPU writing to the register.
  • the monitor power management routine may be stored in the system BIOS.
  • the system is implemented by an add-in time-out controller with sensing means for sensing user input interrupts, and the disabling means comprises at least one switch operable by the time ⁇ out controller and placed in a line carrying one of the HSYNC and VSYNC signals.
  • the system may be accomplished by an add-on (external) time ⁇ out controller connected to interface devices at the ports where user input devices are connected. The interface devices monitor input interrupts, and the add-on time-out controller is connected to an interrupt device at the monitor port for interrupting SYNC signals.
  • the invention in another aspect involves a CRT monitor configured to respond to power level signals from a host computer.
  • the monitor comprises a SYNC detector for monitoring the presence of VSYNC and HSYNC signals from the host, and power level control means for shutting down power circuitry in the CRT monitor in response.
  • a power system for a monitor is provided with an external SYNC detector placed in the monitor cable to the host. This controller drives a switch that controls AC mains power to the monitor.
  • a computer system comprises timing means configured to reset to zero on system interrupts, SYNC disabling means for interrupting SYNC signals to a monitor, SYNC detector means associated with the monitor for sensing the presence of SYNC signals at the monitor, and power level control means associated with the monitor for shutting down power-using circuitry in the monitor in response to the presence of SYNC signals.
  • a method for saving power for a video display monitor comprising steps of sensing input interrupts from user operated devices, resetting a timer to zero on receipt of such interrupts, providing a first power level signal to the monitor based on disabling at least one of a VSYNC and an HSYNC signal to the monitor, providing a second power level signal in a different configuration than for the first power level signal, sensing presence of the SYNC signals at the monitor, and shutting down power circuitry in response to the power level signals.
  • a cathode heater is left on for presence of the first signal, and power is shut off completely in response to receipt of the second signal.
  • the present invention in these several aspects provides a way to save power at a monitor, and minimize radiation emissions as well, in response to periods of inactivity, utilizing to a great extent, existing elements and capabilities of a general-purpose computer. - o -
  • Fig. 1 is a largely schematic representation of a PC according to an embodiment of the present invention.
  • Fig. 2A is a largely schematic representation of a PC enhanced by an add-on device according to an alternative embodiment of the present invention.
  • Fig. 2B is a largely schematic representation of a PC enhanced by an add-in device according to another alternative embodiment.
  • Fig. 3 is a largely schematic representation of a microcontroller-based video monitor according to an embodiment of the present invention.
  • Fig. 4 is a largely schematic representation of a "dumb" monitor equipped with an add-in device according to an alternative embodiment of the present invention.
  • Fig. 5 is a largely schematic representation of an add-on device for controlling AC primary power to a monitor according to another alternative embodiment of the present invention.
  • Fig. 1 shows the functional elements of a preferred embodiment of the present invention capable of providing 3 distinct signals to a monitor to signal the monitor to adjust to as many as three states.
  • the states are selected levels of monitor power management (MPM).
  • MPM monitor power management
  • the signal to the monitor is based on interrupting one or the other or both HSYNC and VSYNC signals.
  • a PC 111 comprises a Basic Input Output System (BIOS) 113 and a Video Graphics Adapter (VGA) 117.
  • BIOS Basic Input Output System
  • VGA Video Graphics Adapter
  • the invention will work equally well with other video adapters, as virtually all such adapters employ HSYNC and VSYNC signals. In some other adapters, equivalent means of interrupting the HSYNC and VSYNC signals would be used.
  • BIOS 113 includes instructions for MPM, which can cause a central processing unit (CPU) 115 to change the state of sync-enable controls in VGA 117.
  • instructions for implementing MPM might be embedded in operating system (OS) device driver routines or Terminate and Stay Resident (TSR) programs.
  • OS operating system
  • TSR Terminate and Stay Resident
  • the MPM instructions monitor CPU 115 interrupts for input devices (not shown) such as the timer, keyboard and serial communication ports.
  • MPM instructions advance a time-out counter on each timer interrupt and reset the count to an initial value on each monitored interrupt.
  • the initial value of the MPM time-out counter may be fixed or adjustable.
  • instructions are executed that change the state of HSYNC Enable 124 and VSYNC Enable 126 control to disable output of horizontal synchronization signals (HSYNC) 123, produced by horizontal sync generator 122, and/or vertical synchronization signals (VSYNC) 125, produced by vertical sync generator 120, or both.
  • a subsequent monitored interrupt causes execution of instructions that change the state of HSYNC Enable 124 and VSYNC Enable 126 control circuits to enable output of HSYNC 123 and VSYNC 125 signals from VGA 117.
  • the enable/disable capability is through writing by the CPU into register 3C2 of the controller, wherein bits six and 7 are reserved for horizontal retrace polarity and vertical retrace polarity respectfully.
  • HSYNC and VSYNC signals 123 and 125 are brought to interface 121 along with other signals, such as R, G, and B signals from D/A/converter 119. The signals are transmitted to a monitor on VGA cable 127 as is known - / - in the art.
  • a current art PC 211 having a CPU 215 is enhanced by installation of a switch 231, which connects between a VGA 217 VSYNC output 225 and VSYNC input 226 to a video interface 221.
  • a switch 231 which connects between a VGA 217 VSYNC output 225 and VSYNC input 226 to a video interface 221.
  • R,G, and B signals are brought to interface 221 from DAC 219.
  • An add-in time-out controller 229 comprising MPM instructions monitors input device activity as described above for Fig. 1. Time-out of all input devices causes instructions to be executed which change the state of program-controlled switch 231, blocking VSYNC input 225 to video interface 221. Resumption of monitored interrupts causes switch 231 to close, returning the VSYNC signals to line 226.
  • a second switch 232 may be used in the HSYNC line to interrupt the HSYNC signals to line 224, and, in this embodiment, the add-in time-out controller controls both switches. In yet another alternative, one switch may be used to interrupt both HSYNC and VSYNC signals.
  • Fig. 2A The functional blocks presented in Fig. 2A are an internal solution to an add-in hardware/software embodiment, and the blocks are not intended to be taken literally as hardware devices and interfaces. It will be apparent to one with skill in the art that there are many equivalent ways the functional blocks might be accomplished.
  • the keyboard, mouse, and modem inputs are monitored by the add-in controller, and are made available as well to the CPU in the typical manner.
  • Fig. 2B shows an external solution for a hardware/software embodiment.
  • an add-on time-out controller 259 is external to computer system 233, and each port that supports an input device and the video output port is fitted with an interface device connected to the add-on time-out controller.
  • interface 243 at COM port 241 used for a modem 245 monitors modem activity and reports to controller 259 on line 244.
  • Interface 249 at keyboard port 247 monitors keyboard 251 activity and reports to controller 259 on line 250.
  • Interface 255 at pointer port 253 monitors pointer 257 activity (mouse, joystick, trackball), and reports to controller 259 on line 256.
  • controller 259 accomplishes the timer functions and outputs signals on line 238 to interface device 237 at video port 235.
  • Line 239 goes to the monitor.
  • Device 237 interrupts HSYNC and VSYNC signals according to the overflow states of add-on controller 259.
  • a color video monitor 347 according to an embodiment of the present invention is shown in Fig. 3.
  • Monitor 347 comprises an interface 333, a microcontroller 339 having MPM instructions according to the present invention and a video circuit (VC) 345 having voltage control circuitry.
  • VC video circuit
  • From interface 333 HSYNC pulses 335 and VSYNC pulses 337 go to microcontroller 339.
  • Microcontroller 339 monitors the HSYNC signal 335 and VSYNC signal 337.
  • the MPM instructions described above count the number of HSYNC pulses occurring between each pair of VSYNC pulses. Zero HSYNC pulses counted causes the MPM instructions in microcontroller 339 to change the voltage on Level-2 signal line 343.
  • an interval count of HSYNC 335 pulses greatly in excess of the maximum video scan rate for monitor 347, indicating a loss of VSYNC 337, causes microcontroller 339 to change the voltage on Level- 1 signal line 341.
  • video circuit 345 When video circuit 345 senses an active voltage level on Level-1 signal line 341, it cuts off power to all circuits in monitor 347 except microcontroller 339, any power necessary to interface 333, and video circuit 345 power-control circuits (not shown). In this level 1 standby mode, power consumption of monitor 347 is reduced by more than 90 percent. If monitor 347 remains in level 1 standby for more than a few seconds, full warm-up time is required to reactivate it. An active voltage level on Level-2 signal line 343 causes video circuit 345 to cut off power to all circuits except those described above plus the CRT cathode heater. In level 2 standby mode monitor 347 power consumption is reduced by 80 to 90 percent.
  • monitor 347 Because the CRT is kept hot, reactivating monitor 347 from level 2 standby requires about 5 seconds or less. Reactivation of monitor 347 occurs when voltape on Level-1 signal line 341 and Level-2 signal line 343 returns to the quiescent state allowing video circuit 345 to activate power to all circuits of monitor 347.
  • Fig. 4 shows an alternative embodiment of the present invention in a monitor 447 with video circuits functionally similar to those described for the monitor shown in Fig. 3, including an interface 433 and a video circuit 445, but without a microcontroller.
  • a sync detect circuit 451 compares pulse intervals for HSYNC 435 and VSYNC 437 against time-constants of adequate duration to allow for brief interruptions of sync pulses. Loss of HSYNC 435 pulses or VSYNC 437 pulses for periods longer than the associated time-constants causes sync detector circuit 451 to change Level-1 signal line 441 or Level-2 signal line 443 voltage to its active state as described for Fig. 3 and with the same results. Similarly, resumption of HSYNC 435 and VSYNC 437 pulses reactivates monitor 447 as described for Fig. 3 above.
  • Fig. 5 shows another alternative embodiment of the present invention suitable for add-on use with a monitor 547 having an interface 533.
  • a sync detect circuit 551 in an external enclosure having pass-through connections, inserts into VGA cable 127.
  • Sync detect circuit 551 monitors video signals on VGA cable 127 and compares the SYNC interval for one or the other of VSYNC and HSYNC to a time-constant in a manner similar to that described for Fig. 4 above. Loss of the monitored SYNC signal in VGA cable 127 for an interval longer than the time-constant causes sync detect circuit 551 to change the voltage on power-control line 561 to its active level, which in turn causes an electronically-controlled switch 553 to open.
  • Electronically-controlled switch 553 controls AC primary power from an electrical cord 559 to a receptacle for monitor 547 power supply cord 557.
  • electronically-controlled switch 553 opens, AC power to a DC power supply 555 is lost, thus causing total shutdown of monitor 547.
  • Resumption of SYNC signals in VGA cable 127 video signal causes sync detect circuit 551 to change power-control line 561 to its quiescent state, thus causing electronically-controlled switch 553 to close, which restores AC power input to DC power supply 555 reactivating monitor 547.
  • Such controls might include shutting down monitor power at will by pressing a "hot key", typing a command line or other program interface step.
  • Other features might allow the operator to change the idle time required to trigger MPM and toggle MPM monitoring on or off.
  • Alternative MPM routines might also require an operator to type a password before enabling the transmission of normal video signals to the video monitor.
  • Alternative devices for both built-in and post-manufacture modification to implement monitor power control might be devised.
  • Embodiments of the present invention for monochromatic and grey-scale video adapters and monitors are also contemplated.

Abstract

A system for lowering the power output of a video display monitor (347, 447, 547) for a computer (111, 211) during periods of operator inactivity senses the presence or absence of horizontal synchronization (HSYNC) and vertical synchronization (VSYNC) signals, which are normally supplied by the host computer to synchronize data transfer to the video monitor with horizontal and vertical sweep circuitry. Time sensing means (229, 259) at the host senses inactivity, and suspends one or another of the HSYNC and VSYNC signals. Sync sensing and control means (451, 551) in the monitor senses the absence of one or both of the HSYNC and VSYNC signals, and controls power-using circuitry (445, 555) in the monitor in response. In an embodiment applicable to monitors having a microprocessor, the system may be incorporated entirely in software at the host and the monitor. In dumb monitors, the system requires add-in and/or add-on devices cooperating with software.

Description

LoK-Power-Consuaiption Monitor Standby System
Field of the Invention
The present invention is in the field of automatic power saving devices and pertains in particular to reduction of power consumption by computer video monitors.
Cross-Reference to Related Documents
The present invention is a continuation-in-part application of copending application Serial No. 07/984,370, titled "Low-Power-Consumption Monitor Standby System", filed December 2, 1992.
Background of the Invention
A typical color video monitor may consume as much as 50 to 80 percent of the total electrical energy consumed by a personal computer (PC). A video monitor dissipates this energy as visible light emissions from screen phosphors, thermal waste, electromagnetic radiation, high- energy radiation and acoustic energy. Only the phosphor emissions are normally considered useful and then only when actively being watched by an observer. The radiation emissions have been a hotly debated source of concern regarding possible health risks from long-term exposure. Manufacturers incur considerable extra expense to reduce radiation emissions from video monitors. Some people are annoyed by the acoustic emissions produced by some monitors. Thermal losses from video monitors contribute an additional load on air conditioning equipment. The energy efficiency of video monitors has historically improved mostly as a result of advances in the electronic circuit components such as the increased use of integrated circuit (IC) devices. Cathode ray tube (CRT) technology has improved rather little in terms of energy efficiency. The number of PC's in regular use is growing rapidly and has reached a point where they have become major consumers of electric power. The United States Environmental Protection Agency has issued power efficiency targets for computer manufacturers to design for in new systems. Low-voltage IC's use less energy, and microprocessor power management techniques allow a computer to reduce energy consumption when idling. Until a suitable replacement for the CRT or a more efficient CRT is developed it will be difficult to substantially improve personal computer energy efficiency.
What is needed is a way to shut down high-energy- consuming circuits in the video monitor when the computer determines that the display may be of no interest to anyone. This might be determined by a period of inactivity on input devices such a modem, mouse and keyboard. Many computers and video terminals use such a technique to activate a screen blanking circuit or a program that displays moving images (or no image) to avoid burning the screen phosphors. Activating an input device such as pressing a key or moving a mouse causes the previous screen image to be restored. This technique can be extended to reduce video monitor power consumption by signalling the microcontroller found in many recent design monitors, or an add-on device for "dumb" monitors, to shut down or restore some or all of the monitor's electrical power circuits. One key to accomplishing this end is a means of signalling a monitor to shut down to some selected level without adding to the signals presently provided to a monitor.
Summary of the Invention
In an embodiment of the present invention a system is provided for a general purpose computer having a CPU, a memory means, a monitor, and video signal means for providing horizontal sync (HSYNC) and vertical sync (VSYNC) signals to the monitor, to signal the monitor to assume alternative states. The system comprises timing means for measuring periods of inactivity configured to reset to zero on input interrupts and to provide overflow signals at preset overflow values, and sync disabling means for interrupting at least one of the HSYNC and VSYNC signals to the monitor according to overflow states of the timing means.
In one embodiment the video signal means comprises video adapter circuitry having a VSYNC generator and an HSYNC generator, and the disabling means comprises a register associated with the video adapter circuitry, wherein one bit in the register is a vertical retrace polarity bit, and another bit is a horizontal retrace polarity bit. The timing means is provided by the CPU following a monitor power management instruction routine stored in the memory means, and SYNC signals are disabled by the CPU writing to the register. The monitor power management routine may be stored in the system BIOS.
In an alternative embodiment the system is implemented by an add-in time-out controller with sensing means for sensing user input interrupts, and the disabling means comprises at least one switch operable by the time¬ out controller and placed in a line carrying one of the HSYNC and VSYNC signals. In yet another alternative the system may be accomplished by an add-on (external) time¬ out controller connected to interface devices at the ports where user input devices are connected. The interface devices monitor input interrupts, and the add-on time-out controller is connected to an interrupt device at the monitor port for interrupting SYNC signals.
In another aspect the invention involves a CRT monitor configured to respond to power level signals from a host computer. The monitor comprises a SYNC detector for monitoring the presence of VSYNC and HSYNC signals from the host, and power level control means for shutting down power circuitry in the CRT monitor in response.
In yet another aspect a power system for a monitor is provided with an external SYNC detector placed in the monitor cable to the host. This controller drives a switch that controls AC mains power to the monitor.
A computer system according to the invention comprises timing means configured to reset to zero on system interrupts, SYNC disabling means for interrupting SYNC signals to a monitor, SYNC detector means associated with the monitor for sensing the presence of SYNC signals at the monitor, and power level control means associated with the monitor for shutting down power-using circuitry in the monitor in response to the presence of SYNC signals.
In yet another aspect a method is provided for saving power for a video display monitor comprising steps of sensing input interrupts from user operated devices, resetting a timer to zero on receipt of such interrupts, providing a first power level signal to the monitor based on disabling at least one of a VSYNC and an HSYNC signal to the monitor, providing a second power level signal in a different configuration than for the first power level signal, sensing presence of the SYNC signals at the monitor, and shutting down power circuitry in response to the power level signals. A cathode heater is left on for presence of the first signal, and power is shut off completely in response to receipt of the second signal.
The present invention in these several aspects provides a way to save power at a monitor, and minimize radiation emissions as well, in response to periods of inactivity, utilizing to a great extent, existing elements and capabilities of a general-purpose computer. - o -
Brief Description of the Drawings
Fig. 1 is a largely schematic representation of a PC according to an embodiment of the present invention.
Fig. 2A is a largely schematic representation of a PC enhanced by an add-on device according to an alternative embodiment of the present invention.
Fig. 2B is a largely schematic representation of a PC enhanced by an add-in device according to another alternative embodiment.
Fig. 3 is a largely schematic representation of a microcontroller-based video monitor according to an embodiment of the present invention.
Fig. 4 is a largely schematic representation of a "dumb" monitor equipped with an add-in device according to an alternative embodiment of the present invention.
Fig. 5 is a largely schematic representation of an add-on device for controlling AC primary power to a monitor according to another alternative embodiment of the present invention.
Description of the Preferred Embodiments
Fig. 1 shows the functional elements of a preferred embodiment of the present invention capable of providing 3 distinct signals to a monitor to signal the monitor to adjust to as many as three states. In an embodiment of the invention, the states are selected levels of monitor power management (MPM). The signal to the monitor is based on interrupting one or the other or both HSYNC and VSYNC signals. In the embodiment shown in Fig. 1 a PC 111 comprises a Basic Input Output System (BIOS) 113 and a Video Graphics Adapter (VGA) 117. The invention will work equally well with other video adapters, as virtually all such adapters employ HSYNC and VSYNC signals. In some other adapters, equivalent means of interrupting the HSYNC and VSYNC signals would be used.
BIOS 113 includes instructions for MPM, which can cause a central processing unit (CPU) 115 to change the state of sync-enable controls in VGA 117. In alternative embodiments instructions for implementing MPM might be embedded in operating system (OS) device driver routines or Terminate and Stay Resident (TSR) programs.
The MPM instructions monitor CPU 115 interrupts for input devices (not shown) such as the timer, keyboard and serial communication ports. MPM instructions advance a time-out counter on each timer interrupt and reset the count to an initial value on each monitored interrupt. The initial value of the MPM time-out counter may be fixed or adjustable. When the MPM time-out counter reaches a pre-set overflow value, due to cessation of monitored interrupts, instructions are executed that change the state of HSYNC Enable 124 and VSYNC Enable 126 control to disable output of horizontal synchronization signals (HSYNC) 123, produced by horizontal sync generator 122, and/or vertical synchronization signals (VSYNC) 125, produced by vertical sync generator 120, or both. A subsequent monitored interrupt causes execution of instructions that change the state of HSYNC Enable 124 and VSYNC Enable 126 control circuits to enable output of HSYNC 123 and VSYNC 125 signals from VGA 117.
In the case of a VGA controller, the enable/disable capability is through writing by the CPU into register 3C2 of the controller, wherein bits six and 7 are reserved for horizontal retrace polarity and vertical retrace polarity respectfully. HSYNC and VSYNC signals 123 and 125 are brought to interface 121 along with other signals, such as R, G, and B signals from D/A/converter 119. The signals are transmitted to a monitor on VGA cable 127 as is known - / - in the art.
In an alternative embodiment, shown in Fig. 2A, useful for refitting existing computers, a current art PC 211 having a CPU 215 is enhanced by installation of a switch 231, which connects between a VGA 217 VSYNC output 225 and VSYNC input 226 to a video interface 221. In a color computer, R,G, and B signals are brought to interface 221 from DAC 219. An add-in time-out controller 229 comprising MPM instructions monitors input device activity as described above for Fig. 1. Time-out of all input devices causes instructions to be executed which change the state of program-controlled switch 231, blocking VSYNC input 225 to video interface 221. Resumption of monitored interrupts causes switch 231 to close, returning the VSYNC signals to line 226. A second switch 232 may be used in the HSYNC line to interrupt the HSYNC signals to line 224, and, in this embodiment, the add-in time-out controller controls both switches. In yet another alternative, one switch may be used to interrupt both HSYNC and VSYNC signals.
The functional blocks presented in Fig. 2A are an internal solution to an add-in hardware/software embodiment, and the blocks are not intended to be taken literally as hardware devices and interfaces. It will be apparent to one with skill in the art that there are many equivalent ways the functional blocks might be accomplished. The keyboard, mouse, and modem inputs are monitored by the add-in controller, and are made available as well to the CPU in the typical manner.
Fig. 2B shows an external solution for a hardware/software embodiment. In this solution an add-on time-out controller 259 is external to computer system 233, and each port that supports an input device and the video output port is fitted with an interface device connected to the add-on time-out controller. For example, interface 243 at COM port 241 used for a modem 245 monitors modem activity and reports to controller 259 on line 244. Interface 249 at keyboard port 247 monitors keyboard 251 activity and reports to controller 259 on line 250. Interface 255 at pointer port 253 monitors pointer 257 activity (mouse, joystick, trackball), and reports to controller 259 on line 256.
In this embodiment controller 259 accomplishes the timer functions and outputs signals on line 238 to interface device 237 at video port 235. Line 239 goes to the monitor. Device 237 interrupts HSYNC and VSYNC signals according to the overflow states of add-on controller 259.
A color video monitor 347 according to an embodiment of the present invention is shown in Fig. 3. Monitor 347 comprises an interface 333, a microcontroller 339 having MPM instructions according to the present invention and a video circuit (VC) 345 having voltage control circuitry. From interface 333 HSYNC pulses 335 and VSYNC pulses 337 go to microcontroller 339. Microcontroller 339 monitors the HSYNC signal 335 and VSYNC signal 337. The MPM instructions described above count the number of HSYNC pulses occurring between each pair of VSYNC pulses. Zero HSYNC pulses counted causes the MPM instructions in microcontroller 339 to change the voltage on Level-2 signal line 343. Similarly, an interval count of HSYNC 335 pulses greatly in excess of the maximum video scan rate for monitor 347, indicating a loss of VSYNC 337, causes microcontroller 339 to change the voltage on Level- 1 signal line 341. Resumption of HSYNC 335 to VSYNC 337 pulse interval counts to a range from the minimum to the maximum scan rate causes MPM instructions in microcontroller 339 to restore quiescent voltage levels to Level-1 signal line 341 and Level-2 signal line 343.
When video circuit 345 senses an active voltage level on Level-1 signal line 341, it cuts off power to all circuits in monitor 347 except microcontroller 339, any power necessary to interface 333, and video circuit 345 power-control circuits (not shown). In this level 1 standby mode, power consumption of monitor 347 is reduced by more than 90 percent. If monitor 347 remains in level 1 standby for more than a few seconds, full warm-up time is required to reactivate it. An active voltage level on Level-2 signal line 343 causes video circuit 345 to cut off power to all circuits except those described above plus the CRT cathode heater. In level 2 standby mode monitor 347 power consumption is reduced by 80 to 90 percent. Because the CRT is kept hot, reactivating monitor 347 from level 2 standby requires about 5 seconds or less. Reactivation of monitor 347 occurs when voltape on Level-1 signal line 341 and Level-2 signal line 343 returns to the quiescent state allowing video circuit 345 to activate power to all circuits of monitor 347.
Fig. 4 shows an alternative embodiment of the present invention in a monitor 447 with video circuits functionally similar to those described for the monitor shown in Fig. 3, including an interface 433 and a video circuit 445, but without a microcontroller. A sync detect circuit 451 compares pulse intervals for HSYNC 435 and VSYNC 437 against time-constants of adequate duration to allow for brief interruptions of sync pulses. Loss of HSYNC 435 pulses or VSYNC 437 pulses for periods longer than the associated time-constants causes sync detector circuit 451 to change Level-1 signal line 441 or Level-2 signal line 443 voltage to its active state as described for Fig. 3 and with the same results. Similarly, resumption of HSYNC 435 and VSYNC 437 pulses reactivates monitor 447 as described for Fig. 3 above.
Fig. 5 shows another alternative embodiment of the present invention suitable for add-on use with a monitor 547 having an interface 533. A sync detect circuit 551, in an external enclosure having pass-through connections, inserts into VGA cable 127. Sync detect circuit 551 monitors video signals on VGA cable 127 and compares the SYNC interval for one or the other of VSYNC and HSYNC to a time-constant in a manner similar to that described for Fig. 4 above. Loss of the monitored SYNC signal in VGA cable 127 for an interval longer than the time-constant causes sync detect circuit 551 to change the voltage on power-control line 561 to its active level, which in turn causes an electronically-controlled switch 553 to open. Electronically-controlled switch 553 controls AC primary power from an electrical cord 559 to a receptacle for monitor 547 power supply cord 557. When electronically- controlled switch 553 opens, AC power to a DC power supply 555 is lost, thus causing total shutdown of monitor 547. Resumption of SYNC signals in VGA cable 127 video signal causes sync detect circuit 551 to change power-control line 561 to its quiescent state, thus causing electronically-controlled switch 553 to close, which restores AC power input to DC power supply 555 reactivating monitor 547.
It will be apparent to one with skill in the art that there are many changes that might be made without departing from the spirit and scope of the invention. Some of these alternatives have already been described, such as MPM instructions implemented in an OS device driver or TSR routines instead of the BIOS, single-level MPM instead of two-level MPM and an external video monitor power control device. Other methods of signalling MPM state changes to a monitor might include time-based coded sequences of frequency changes in HSYNC or VSYNC, coded values in the color signals, or no color signal for an extended period. Alternative embodiments of MPM routines might allow an operator to control MPM operation through command steps, such as menus, dialog boxes or command lines. Such controls might include shutting down monitor power at will by pressing a "hot key", typing a command line or other program interface step. Other features might allow the operator to change the idle time required to trigger MPM and toggle MPM monitoring on or off. Alternative MPM routines might also require an operator to type a password before enabling the transmission of normal video signals to the video monitor. Alternative devices for both built-in and post-manufacture modification to implement monitor power control might be devised. Embodiments of the present invention for monochromatic and grey-scale video adapters and monitors are also contemplated.

Claims

What is claimed is:
1. In a general-purpose computer having a CPU, memory means, input means, a monitor, and video signal means for providing horizontal sync (HSYNC) and vertical sync (VSYNC) signals to the monitor, a system for signalling the monitor to assume alternative power-using states comprising: timing means for measuring periods of inactivity of said input means, said timing means configured to reset to zero on input interrupts and to provide overflow signals at preset overflow values;
SYNC disabling means for interrupting at least one of HSYNC and VSYNC signals to the monitor according to overflow states of said timing means; and power management means associated with said monitor for selectively removing power from power-using circuits in said monitor in response to the absence of said at least one of said HSYNC and VSYNC signals.
2. A system as in claim 1 wherein said video signal means comprises video adapter circuitry having a VSYNC generator and an HSYNC generator and said disabling means comprises a register associated with said video adapter circuitry wherein one bit is a vertical retrace polarity bit and another bit is a horizontal retrace polarity bit, said timing means is provided by said CPU following a monitor power management instruction routine stored in said memory means, and SYNC signals are disabled by said CPU writing to said register.
3. A system as in claim 2 wherein said monitor power management instruction routine is implemented in a system BIOS in a programmable read only memory.
4. A system as in claim 1 wherein said timing means comprises an add-in time-out controller with sensing means for monitoring said input interrupts and said disabling means comprises at least one switch operable by the time¬ out controller in a line carrying one of said HSYNC and said VSYNC signals.
5. A system as in claim 4 wherein said disabling means comprises separately operable switches in each of two lines, one carrying said HSYNC signals and the other carrying said VSYNC signals.
6. A system as in claim 4 wherein said disabling means comprises a single switch interrupting two lines, one carrying said HSYNC signals and the other carrying said VSYNC signals.
7. A system as in claim 1 wherein said timing means comprises an add-on time-out controller connected to sensing devices interfaced at ports connected to user input devices comprising one or more of a modem, a pointer device, and a keyboard, and said SYNC disabling means is a device connected to said time-out controller and interfaced at a port connected to said monitor, for interrupting HSYNC and VSYNC signals according to overflow states of said time-out controller.
8. A cathode ray tube (CRT) monitor for displaying text and characters for a computer system and configured for power management in response to signals from a host computer system, said monitor comprising: detector means for selectively detecting absence of at least one of horizontal sync (HSYNC) and vertical sync (VSYNC) signals conveyed to said monitor by a host computer; and power level control means for selectively shutting down power-using circuitry in said CRT monitor in response to absence of said at least one of HSYNC and VSYNC signals.
9. A CRT monitor as in claim 8 wherein said detector means comprises a microcontroller sensing absence of SYNC signals and said power level control means is configured to operate in three power modes in response to signals from said microcontroller, a first mode having all circuits on, a second mode having all power circuits selectively operable by said power level control means off save a cathode heater remaining on, and a third mode having all power circuits selectively operable by said power level control means off.
10. A CRT monitor as in claim 9 wherein said first power mode is initiated in response to both of said HSYNC and VSYNC signals being sensed by said microcontroller at substantially operable levels.
11. A CRT monitor as in claim 9 wherein said second power mode is initiated in response to one of said HSYNC and said VSYNC signals being sensed by said microcontroller and the other not sensed.
12. A CRT monitor as in claim 11 wherein said third power mode is initiated in response to one of said HSYNC and said VSYNC signals being sensed by said microcontroller and the other not sensed, in the opposite order for initiating said second power mode.
13. A CRT monitor as in claim 9 wherein said third power mode is initiated in response to both said HSYNC and said VSYNC signals not sensed by said microcontroller.
14. A power management system for a cathode ray tube (CRT) monitor having a connecting cable for carrying signals from a host system, said power management system comprising: detection means imposed in line with said connecting cable for selectively detecting horizontal sync (HSYNC) and vertical sync (VSYNC) signals and outputting a disconnect signal in response to the absence of one of said VSYNC and HSYNC signal; and switch means for controlling primary power to said CRT and responsive to said disconnect signal to disconnect primary power from said CRT.
15. A computer system having input means, a system enclosure and a separate monitor, said computer system configured to save CRT power in response to system inactivity, comprising: timing means associated with said system enclosure for timing periods of inactivity of said input means, said timing means configured to reset to zero on input interrupts and to provide overflow signals at preset overflow values;
SYNC signal disabling means associated with said system enclosure for interrupting at least one of horizontal sync (HSYNC) and vertical sync (VSYNC) signals to the monitor according to overflow states of said timing means; detector means associated with said monitor for detecting absence of said at least one of HSYNC and VSYNC signals conveyed to said monitor; and power level control means associated with said monitor and connected to said detector means for shutting down power-using circuitry in said monitor in response to said absence of said at least one of HSYNC and VSYNC signals.
16. A method for saving power for a video display monitor comprising steps of: sensing input interrupts from user input devices; resetting a timing means to zero on receipt of each of said interrupts; providing a first power level signal to said video display monitor based on disabling at least one of a VSYNC and an HSYNC signal to said video display monitor at a first preset time interval accumulated on said timing means; providing a second power level signal to said video display monitor based on disabling at least one of said VSYNC and HSYNC signals in a configuration different than for providing said first power level signal at a second preset time interval accumulated on said timing means; sensing presence of said first and said second power level signals at said video display monitor; shutting down power circuits in said video display monitor except a cathode heater in response to said first power level signal; and shutting down all power circuits in said video display monitor in response to said second power level signal.
PCT/US1993/011579 1992-12-02 1993-11-29 Low-power-consumption monitor standby system WO1994012969A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE0672285T DE672285T1 (en) 1992-12-02 1993-11-29 READINESS SYSTEM FOR COMPUTER SCREEN WITH LOW ENERGY CONSUMPTION.
JP6513444A JP2847099B2 (en) 1992-12-02 1993-11-29 Low power consumption monitor standby system
DE69325106T DE69325106T2 (en) 1992-12-02 1993-11-29 READINESS SYSTEM FOR COMPUTER SCREEN WITH LOW ENERGY CONSUMPTION
EP94903345A EP0672285B1 (en) 1992-12-02 1993-11-29 Low-power-consumption monitor standby system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US98437092A 1992-12-02 1992-12-02
US08/141,413 1993-10-22
US07/984,370 1993-10-22
US08/141,413 US5389952A (en) 1992-12-02 1993-10-22 Low-power-consumption monitor standby system

Publications (1)

Publication Number Publication Date
WO1994012969A1 true WO1994012969A1 (en) 1994-06-09

Family

ID=26839089

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/011579 WO1994012969A1 (en) 1992-12-02 1993-11-29 Low-power-consumption monitor standby system

Country Status (6)

Country Link
US (3) US5389952A (en)
EP (5) EP0672285B1 (en)
JP (2) JP2847099B2 (en)
AT (5) ATE261167T1 (en)
DE (8) DE69332748T2 (en)
WO (1) WO1994012969A1 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996041252A1 (en) * 1995-06-07 1996-12-19 Seiko Epson Corporation Computer system with video display controller having power saving modes
JPH1097356A (en) * 1996-08-14 1998-04-14 Samsung Electron Co Ltd Power saving display device
US5923306A (en) * 1993-06-24 1999-07-13 Nintendo Co. Ltd. Hotel-based video game and communication system
GB2295702B (en) * 1994-11-30 1999-09-22 Lg Electronics Inc Control device for power conservation
EP0978780A1 (en) * 1998-08-06 2000-02-09 Elonex I.P. Holdings Limited Low-power-consumption monitor standby system
US6047127A (en) * 1993-06-24 2000-04-04 Nintendo Co. Ltd. Electronic Entertainment and communications system
US6088806A (en) * 1998-10-20 2000-07-11 Seiko Epson Corporation Apparatus and method with improved power-down mode
US6147696A (en) * 1993-06-24 2000-11-14 Nintendo Co. Ltd. Electronic entertainment and communication system
US6327161B1 (en) 1999-01-13 2001-12-04 Acer Peripherals, Inc. Power-saving circuit
US6762733B2 (en) 1993-06-24 2004-07-13 Nintendo Co. Ltd. Electronic entertainment and communication system
CN106339063A (en) * 2016-08-26 2017-01-18 苏州佳世达电通有限公司 Display control circuit and control method

Families Citing this family (121)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839855B2 (en) * 1990-03-23 2005-01-04 Matsushita Electric Industrial Co., Ltd. Data processing apparatus
JP2935307B2 (en) * 1992-02-20 1999-08-16 株式会社日立製作所 display
FI94571C (en) * 1992-03-02 1995-09-25 Icl Personal Systems Oy Video Display Device
US5821924A (en) * 1992-09-04 1998-10-13 Elonex I.P. Holdings, Ltd. Computer peripherals low-power-consumption standby system
JP3334211B2 (en) * 1993-02-10 2002-10-15 株式会社日立製作所 display
US5745105A (en) * 1993-03-31 1998-04-28 Samsung Electronics Co., Ltd. Power saving apparatus and method of a monitor
GB2282307A (en) * 1993-09-24 1995-03-29 Ibm Disabling display unit when image is unchanged
US7092229B1 (en) * 1993-09-30 2006-08-15 Harmonics Limited, Inc. Electrical filter/protector, and methods of constructing and utilizing same
US6636405B2 (en) 1993-09-30 2003-10-21 Michael Z. Lowenstein Mitigation of 3rd harmonic currents in electrical power distribution systems
US7068264B2 (en) * 1993-11-19 2006-06-27 Hitachi, Ltd. Flat display panel having internal power supply circuit for reducing power consumption
US6522314B1 (en) * 1993-11-19 2003-02-18 Fujitsu Limited Flat display panel having internal power supply circuit for reducing power consumption
JP3266402B2 (en) * 1993-12-28 2002-03-18 キヤノン株式会社 Display device
KR0136966B1 (en) * 1994-01-26 1998-04-28 김광호 A gray voltage generator for a liquid crystal display equiped with a function of controlling viewing angle
JP3477652B2 (en) * 1994-03-18 2003-12-10 富士通株式会社 Information processing terminal device
US5613129A (en) * 1994-05-02 1997-03-18 Digital Equipment Corporation Adaptive mechanism for efficient interrupt processing
US5555032A (en) * 1994-05-09 1996-09-10 Weltrend Semiconductor, Inc. Integrated circuit for economizing power consumption of a monitor by using two reference values for discrminating the input signal
US5481299A (en) * 1994-05-16 1996-01-02 Coffey; Lawrence G. Power saving device for video screen
KR970003439B1 (en) * 1994-05-19 1997-03-18 삼성전자 주식회사 Power control circuit of monitor
US5616988A (en) * 1994-08-19 1997-04-01 Hyundai Electronics Industries Co., Ltd. High energy-saving circuit for a display apparatus
JPH08101657A (en) * 1994-09-30 1996-04-16 Toshiba Corp Computer system and method for controlling power consumption of crt display in its system
KR960024874A (en) * 1994-12-30 1996-07-20 김광호 Password setting device and password setting method of display device using micom
JP3361909B2 (en) * 1995-03-03 2003-01-07 エヌイーシー三菱電機ビジュアルシステムズ株式会社 Display device
KR0170621B1 (en) * 1995-05-15 1999-03-30 김광호 Laster control circuit
US5703629A (en) * 1995-06-08 1997-12-30 Dell Usa, L.P. Computer system including protected graphics display control signal sequencing
US5659371A (en) * 1995-07-21 1997-08-19 Apple Computer, Inc. Method and apparatus for power supply startup in video monitors
JPH09134154A (en) * 1995-11-07 1997-05-20 Sony Corp Video display device
KR0139545Y1 (en) * 1995-12-06 1999-04-01 삼성전자주식회사 Heater preheating device for crt
KR100234423B1 (en) * 1995-12-05 1999-12-15 윤종용 Apparatus and method for power control for computer peripheral
US5623321A (en) * 1995-12-18 1997-04-22 Lucent Technologies Inc. Circuit for cutting off power to an active RF component
KR100199831B1 (en) * 1996-01-15 1999-06-15 구자홍 Power saving control circuit of a image displayer
KR0173428B1 (en) * 1996-02-17 1999-04-01 김광호 Monitor control device and its control method
US5944830A (en) * 1996-03-08 1999-08-31 Samsung Electronics Co., Ltd. Reducing power consumption in monitor by switching off heater power in power-off mode
US6018804A (en) * 1996-03-25 2000-01-25 Thomson Consumer Electronics, Inc. Data bus isolator
KR100214381B1 (en) * 1996-04-16 1999-08-02 구자홍 Bnc/d-sub auto-switching circuit for monitor
US5786903A (en) * 1996-04-23 1998-07-28 Must Systems Inc. Multi-power control system for scanners
US5724611A (en) * 1996-04-25 1998-03-03 Vlsi Technology, Inc. Automatic cache controller system and method therefor
FI102701B1 (en) * 1996-05-06 1999-01-29 Nokia Display Products Oy Method for reducing power consumption in a monitor
GB2313027B (en) * 1996-05-08 2000-03-22 Icl Systems Ab Video display unit
US6385734B2 (en) * 1996-06-03 2002-05-07 Compaq Information Technologies Group, L.P. Portable computer with low power audio CD-player
KR980004313A (en) * 1996-06-29 1998-03-30 김광호 DPMS drive device using communication
KR100225057B1 (en) * 1996-07-23 1999-10-15 윤종용 Control apparatus and method for power supply of monitor having audio system
US5956022A (en) * 1996-10-02 1999-09-21 Mag Technology Co., Ltd. Interactive monitor trouble-shooting device
JPH10105132A (en) * 1996-10-03 1998-04-24 Nec Gumma Ltd Lcd control circuits for reducing power consumption
FI106070B (en) * 1996-10-29 2000-11-15 Nokia Display Products Oy Screen power saving method
KR19980044732A (en) * 1996-12-07 1998-09-05 김광호 Display and Display Method of DPMS Mode in Computer System
WO1998037693A1 (en) * 1997-02-19 1998-08-27 Sanyo Electric Co., Ltd. Television receiver
KR100283572B1 (en) * 1997-02-24 2001-03-02 윤종용 How to Display DPMS on Display Device Using OSD
KR100245202B1 (en) * 1997-03-07 2000-02-15 윤종용 An apparatus for power control and its method in a computer system
KR100474256B1 (en) * 1997-03-11 2005-07-07 삼성전자주식회사 Power consumption control circuit of tilt correction coil
KR100228731B1 (en) * 1997-03-19 1999-11-01 윤종용 Power supply control circuit and method for voice processing part
US6205318B1 (en) * 1997-04-07 2001-03-20 Gateway 2000, Inc. Power management controller for computer system
KR100247390B1 (en) * 1997-04-14 2000-03-15 윤종용 Method of realizing dpms function of display device using usb
KR19980066384U (en) * 1997-05-16 1998-12-05 윤종용 Low power circuit using electronic switch of display monitor
US6049316A (en) * 1997-06-12 2000-04-11 Neomagic Corp. PC with multiple video-display refresh-rate configurations using active and default registers
US5926172A (en) * 1997-08-25 1999-07-20 Int Labs, Inc. Video data transmission and display system and associated methods for encoding/decoding synchronization information and video data
JPH11122506A (en) * 1997-10-16 1999-04-30 Fujitsu Ltd Video signal processing circuit and computer system
US6437761B1 (en) * 1997-10-27 2002-08-20 Sony Corporation Monitor status information storage and display
KR19990040286A (en) * 1997-11-17 1999-06-05 윤종용 Image playback device with screen mute function and screen mute method accordingly
WO1999027516A1 (en) * 1997-11-20 1999-06-03 Wincor Nixdorf Gmbh & Co Kg On delay device for a visual display unit
US6189106B1 (en) 1998-05-08 2001-02-13 Gateway, Inc. Method and apparatus for operating an electronic device at an optimal power mode based upon a scheduled event
US6529190B2 (en) * 1998-09-30 2003-03-04 Sony Corporation Method and apparatus for monitoring/shutting down a power line within a display device
US6313878B1 (en) * 1998-11-20 2001-11-06 Sony Corporation Method and structure for providing an automatic hardware-implemented screen-saver function to a display product
US6563495B1 (en) * 1998-12-21 2003-05-13 Thomson Licensing S.A. Automatic screen saver
US6219039B1 (en) 1999-01-26 2001-04-17 Dell Usa, L.P. Compact PC video subsystem tester
JP2000305670A (en) 1999-04-19 2000-11-02 Toshiba Corp Device and method for controlling electric power saving and information processor
WO2000072296A1 (en) 1999-05-21 2000-11-30 Koninklijke Philips Electronics N.V. Power management in a monitor
US6473078B1 (en) 1999-05-26 2002-10-29 Nokia Display Products Oy Method and device for power consumption management of an integrated display unit
US6404423B1 (en) * 1999-07-09 2002-06-11 Nokia Display Products Oy Method for display power management and monitor equipped with a power management function
US6191504B1 (en) * 1999-09-22 2001-02-20 Sony Corporation Of Japan System and method for reduced standby power consumption in a display device
JP2001109418A (en) 1999-10-04 2001-04-20 Mitsubishi Electric Corp Picture display device and control method therefor
US7414606B1 (en) * 1999-11-02 2008-08-19 Ati International Srl Method and apparatus for detecting a flat panel display monitor
US6801196B1 (en) 1999-11-18 2004-10-05 Intel Corporation Method and apparatus to control power state of a display device
JP2001222346A (en) * 2000-02-10 2001-08-17 Toshiba Corp Computer and computer system and power saving control method
CN1322979A (en) * 2000-05-15 2001-11-21 明碁电脑股份有限公司 Power saving method and device for screen of computer system
JP2002072990A (en) * 2000-06-12 2002-03-12 Sharp Corp Image display system and display device
EP1172936B1 (en) * 2000-07-11 2005-03-09 STMicroelectronics S.r.l. Digital to analogue converter comprising a third order sigma delta modulator
EP1184832A1 (en) * 2000-08-30 2002-03-06 ADI Corporation Display monitor operable in a power-saving mode with reduced pulsed heating filament power
US6769070B1 (en) * 2000-09-08 2004-07-27 Sony Corporation Standby circuit for digital display monitor
JP4601186B2 (en) * 2001-02-19 2010-12-22 シャープ株式会社 Display device
JP2002333872A (en) * 2001-03-07 2002-11-22 Ricoh Co Ltd Lcd power supply control method, control circuit thereof, and imaging device having the circuit
US6809711B2 (en) 2001-05-03 2004-10-26 Eastman Kodak Company Display driver and method for driving an emissive video display
KR100421006B1 (en) * 2001-07-11 2004-03-04 삼성전자주식회사 A apparatus and method for eliminating afterimage state
KR100413686B1 (en) * 2001-07-14 2003-12-31 삼성전자주식회사 Apparatus for saving power in monitor and method thereof
US20030051179A1 (en) * 2001-09-13 2003-03-13 Tsirkel Aaron M. Method and apparatus for power management of displays
US20030051182A1 (en) * 2001-09-13 2003-03-13 Tsirkel Aaron M. Method and apparatus for cognitive power management of video displays
US20030071769A1 (en) * 2001-10-16 2003-04-17 Dan Sullivan Method and apparatus for preventing plasma display screen burn-in
US20030071805A1 (en) * 2001-10-17 2003-04-17 Stanley Randy P. Powering down display screens of processor-based systems
JP3824260B2 (en) * 2001-11-13 2006-09-20 任天堂株式会社 Game system
EP1490859A1 (en) * 2001-12-05 2004-12-29 Koninklijke Philips Electronics N.V. Method for driving a liquid crystal display device in normal and standby mode
KR100452721B1 (en) 2002-01-24 2004-10-14 삼성전자주식회사 display apparatus and controlling method thereof
US7000127B2 (en) * 2002-04-30 2006-02-14 Dell Products L.P. Power saving circuit for display system
US20030222866A1 (en) * 2002-05-30 2003-12-04 Eastman Kodak Company Display driver and method for driving an emissive video display in an image displaying device
TW561334B (en) * 2002-06-20 2003-11-11 Benq Corp Power management system of liquid crystal display
US7634675B2 (en) * 2002-09-05 2009-12-15 Gateway, Inc. Monitor power management
US7664975B2 (en) 2002-10-31 2010-02-16 Samsung Electronics Co., Ltd. Apparatus and method for controlling power of monitor
KR100737887B1 (en) * 2003-05-20 2007-07-10 삼성전자주식회사 Driver circuit, flat panel display apparatus having the same and method of driving the same
TWI221745B (en) * 2003-07-04 2004-10-01 Benq Corp Display apparatus with a function of retaining an image and method of retaining an image
US7117380B2 (en) * 2003-09-30 2006-10-03 International Business Machines Corporation Apparatus, system, and method for autonomic power adjustment in an electronic device
GB0402046D0 (en) 2004-01-29 2004-03-03 Koninkl Philips Electronics Nv Active matrix display device
JP2005295256A (en) * 2004-03-31 2005-10-20 Toshiba Corp Television receiver
US7714852B1 (en) * 2005-11-10 2010-05-11 Landesk Software Limited Systems and methods for blanking a display screen on a display device of a computer system
CN101146143B (en) * 2006-09-13 2012-07-04 鸿富锦精密工业（深圳）有限公司 Energy-saving electronic device and energy-saving method
CN101206517B (en) * 2006-12-22 2011-06-22 群康科技(深圳)有限公司 Computer
JP4960813B2 (en) * 2007-09-14 2012-06-27 株式会社リコー Power control system
KR101379183B1 (en) * 2007-09-20 2014-03-28 삼성전자주식회사 Electronic device and method for removing static electricity
US7904739B2 (en) * 2007-10-08 2011-03-08 Hewlett-Packard Development Company, L.P. Managing a power state for a peripheral
DE202007018449U1 (en) 2007-11-02 2008-10-02 Fujitsu Siemens Computers Gmbh Electronic device, computer and arrangement
KR100960885B1 (en) 2007-12-27 2010-06-04 주식회사 동부하이텍 Method and apparatus for controlling timing controller in monitor system
DE202008005537U1 (en) 2008-03-17 2008-07-24 Maxdata International Gmbh Monitor for a PC and with at least one connector for a video signal
US8423803B2 (en) 2008-04-23 2013-04-16 Hewlett-Packard Development Company, L.P. Method and system for forcing one or more power states on a display
US8884734B2 (en) * 2008-11-17 2014-11-11 Roger Li-Chung Wu Vision protection method and system thereof
JP2010282607A (en) * 2009-05-01 2010-12-16 Ricoh Co Ltd Communication device, method of controlling communication device, program, and storage medium
US20100295782A1 (en) 2009-05-21 2010-11-25 Yehuda Binder System and method for control based on face ore hand gesture detection
JP2011248734A (en) * 2010-05-28 2011-12-08 Oki Data Corp Electronic equipment and electronic system
US8816968B2 (en) 2010-10-13 2014-08-26 International Business Machines Corporation Selective monitor control
JP5923815B2 (en) * 2011-02-07 2016-05-25 Ｎｌｔテクノロジー株式会社 Video signal processing circuit, video signal processing method used in the processing circuit, and image display apparatus
US9805689B2 (en) * 2011-11-30 2017-10-31 Gpo Us, Inc. Apparatus and method for easy diagnosis, repair, and maintenance of a commercial display screen
KR101419490B1 (en) * 2013-10-02 2014-07-14 주식회사 브이디텍 A computer system using the apparatus for saving the power supplied to a monitor, and the method for saving the power supplied to a monitor
KR102058856B1 (en) * 2013-12-31 2019-12-24 엘지디스플레이 주식회사 Liquid crystal display device
DE102014226075A1 (en) * 2014-12-16 2016-06-16 Siemens Aktiengesellschaft Device for coordinated control of an operating state of a production plant and production system and method
US10737105B2 (en) * 2017-10-02 2020-08-11 Avive Solutions, Inc. Modular defibrillator architecture

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3941989A (en) * 1974-12-13 1976-03-02 Mos Technology, Inc. Reducing power consumption in calculators
US4553166A (en) * 1983-12-07 1985-11-12 Zenith Electronics Corporation Video system with automatic power up
US4751502A (en) * 1985-03-27 1988-06-14 Ascii Corporation Display controller for displaying a cursor on either of a CRT display device or a liquid crystal display device
JPH0224696A (en) * 1988-07-13 1990-01-26 Toshiba Corp Display control system
US5059961A (en) * 1989-08-21 1991-10-22 Cheng Te J Screen blanker for a monitor of a computer system
US5079666A (en) * 1989-08-31 1992-01-07 International Business Machines Corporation Power supply shutdown through loss of sync

Family Cites Families (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3453601A (en) * 1966-10-18 1969-07-01 Philco Ford Corp Two speed arithmetic calculator
US3588608A (en) * 1969-02-24 1971-06-28 Sun Electric Corp Circuit protection apparatus for disabling high voltage to a cathode-ray tube
DE2844112C2 (en) † 1977-10-11 1984-02-16 N.V. Philips' Gloeilampenfabrieken, 5621 Eindhoven Video circuit with burn-in protection
US4338623A (en) * 1977-10-11 1982-07-06 U.S. Philips Corporation Video circuit with screen-burn-in protection
GB2078069B (en) * 1980-06-10 1984-03-28 Philips Electronic Associated Projection television apparatus
JPS57123598A (en) * 1981-01-21 1982-08-02 Seiko Instr & Electronics Ltd Sample holding circuit
JPS5899075A (en) † 1981-12-09 1983-06-13 Matsushita Electric Ind Co Ltd Power supply device
US5245312A (en) * 1982-01-09 1993-09-14 Canon Kabushiki Kaisha Self-timer operation informing device
US4532457A (en) * 1982-01-29 1985-07-30 Rca Corporation Television receiver standby circuit
US4488181A (en) * 1982-04-23 1984-12-11 Rca Corporation Electron beam suppression circuit for a television receiver
JPS5955526A (en) * 1982-09-24 1984-03-30 Sharp Corp Interface circuit
US4649373A (en) * 1983-08-10 1987-03-10 International Business Machines Corporation Powered conservation system in battery powered keyboard device including a microprocessor
JPS6090476A (en) * 1983-10-24 1985-05-21 Sony Corp Automatic shut-off device of television set
US4727362A (en) † 1984-07-16 1988-02-23 International Business Machines Corporation Digital display system
US4922448A (en) * 1985-07-10 1990-05-01 Brother Kogyo Kabushiki Kaisha Word processing system having small-sized and large-sized displays for simultaneous display and automatic power shut-off circuit
JPS6289090A (en) * 1985-10-15 1987-04-23 シャープ株式会社 El panel driver
JPS62106523A (en) * 1985-11-01 1987-05-18 Sharp Corp Memory back-up circuit
JPS62216018A (en) * 1986-03-18 1987-09-22 Fujitsu Ltd Battery backup system
US5178152A (en) * 1986-04-21 1993-01-12 Terumo Corporation Electronic sphygmomanometer
JPS62262250A (en) * 1986-05-08 1987-11-14 Mitsubishi Electric Corp Magnetic recording and reproducing device
US4722005A (en) * 1986-09-12 1988-01-26 Intel Corporation Software controllable hardware CRT dimmer
JPS63101896A (en) * 1986-10-17 1988-05-06 株式会社大真空 Remote control system for display device
JPS63121365A (en) * 1986-11-10 1988-05-25 Nec Corp Character display control circuit
JPS63261229A (en) * 1987-04-17 1988-10-27 Mitsubishi Electric Corp Brightness adjustment system for active matrix liquid crystal display device
JPS62276973A (en) * 1987-05-15 1987-12-01 Casio Comput Co Ltd Television receiver
US5226122A (en) * 1987-08-21 1993-07-06 Compaq Computer Corp. Programmable logic system for filtering commands to a microprocessor
WO1989006012A1 (en) * 1987-12-17 1989-06-29 Rakoczy G Istvan Procedure and equipment for automatic shutdown of data processing equipment
JPH01257893A (en) * 1988-04-07 1989-10-13 Mitsubishi Electric Corp Electric power unit
JPH01269979A (en) † 1988-04-22 1989-10-27 Nec Corp Crt terminal device
US4876240A (en) * 1988-05-02 1989-10-24 Xerox Corporation Processes for the preparation of copper oxide superconductors
JP2892010B2 (en) † 1988-05-28 1999-05-17 株式会社東芝 Display control method
JPH024696A (en) * 1988-06-21 1990-01-09 Sanyo Electric Co Ltd Beverage supply apparatus
JPH0253126A (en) * 1988-08-17 1990-02-22 Hitachi Ltd Semiconductor file device
JPH0256620A (en) * 1988-08-23 1990-02-26 Mita Ind Co Ltd Display device of terminal equipment
US4980836A (en) * 1988-10-14 1990-12-25 Compaq Computer Corporation Apparatus for reducing computer system power consumption
JP2559478B2 (en) * 1988-10-14 1996-12-04 株式会社日立製作所 Video memory circuit
JPH02201516A (en) * 1989-01-31 1990-08-09 Toshiba Corp Power save system
JPH02280587A (en) * 1989-04-21 1990-11-16 Sony Corp Liquid crystal picture display device
JPH0391798A (en) * 1989-09-04 1991-04-17 Nec Corp Display device
US5167024A (en) * 1989-09-08 1992-11-24 Apple Computer, Inc. Power management for a laptop computer with slow and sleep modes
JPH03105561A (en) * 1989-09-20 1991-05-02 Hitachi Ltd Word processor
US5021983B1 (en) * 1989-11-13 1996-05-28 Chips & Technologies Inc Suspend/resume apparatus and method for reducing power consumption in battery powered computers
GB2240243B (en) * 1990-01-19 1994-01-19 Rank Cintel Ltd Protection of cathode ray tubes
JPH03214871A (en) * 1990-01-19 1991-09-20 Kokusai Electric Co Ltd Crt display device
JPH03238516A (en) † 1990-02-15 1991-10-24 Koufu Nippon Denki Kk Pos terminal equipment
FR2659155B1 (en) * 1990-03-01 1992-05-29 Renault DEVICE FOR CONTROLLING THE ELECTRICAL SUPPLY OF A PLURALITY OF ELECTRONIC MODULES.
US5089754A (en) * 1990-04-30 1992-02-18 Thomson Consumer Electronics, Inc. Protection circuit for a cathode ray tube
US5396635A (en) * 1990-06-01 1995-03-07 Vadem Corporation Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system
FI87707C (en) * 1990-06-20 1993-02-10 Planar Int Oy PROCEDURE FOR ORGANIZATION OF THE EFFECTIVE DEFINITION OF HOS EN ELECTROLUMINESCENSATION DISPLAY AV VAEXELSTROEMSTYP
JPH0462614A (en) * 1990-06-30 1992-02-27 Nec Home Electron Ltd Portable data processor
JPH0495146A (en) * 1990-08-08 1992-03-27 Hitachi Ltd Information processor
JPH0496811A (en) * 1990-08-13 1992-03-30 Mitsubishi Electric Corp Information processor
JPH04107624A (en) * 1990-08-28 1992-04-09 Seiko Epson Corp Compact electronic equipment
JPH04107623A (en) * 1990-08-28 1992-04-09 Seiko Epson Corp Display device
DE4027470A1 (en) * 1990-08-30 1992-03-05 Boehringer Ingelheim Kg NEW HETRAZEPINOIDE AMIDE
CA2050773A1 (en) † 1990-09-25 1992-03-26 John A. Andresen Automated pap test method and device
JPH04140826A (en) * 1990-10-01 1992-05-14 Nec Corp Crt controller
US5237692A (en) * 1990-11-09 1993-08-17 Ast Research Inc. Internal interrupt controller for a peripheral controller
JPH04188972A (en) * 1990-11-21 1992-07-07 Fujitsu General Ltd Television receiver with built-in timer function
JPH04195091A (en) * 1990-11-28 1992-07-15 Toshiba Corp Display controller
JPH04205020A (en) * 1990-11-29 1992-07-27 Toshiba Corp Electric power saving controller for information processor
KR0155558B1 (en) * 1990-11-30 1998-11-16 구자홍 Power saving method and its apparatus
US5430881A (en) * 1990-12-28 1995-07-04 Dia Semicon Systems Incorporated Supervisory control method and power saving control unit for computer system
JPH04245518A (en) * 1991-01-31 1992-09-02 Nec Home Electron Ltd Information processor
JPH04290388A (en) * 1991-03-19 1992-10-14 Hitachi Ltd Liquid crystal device
JPH04333119A (en) * 1991-05-09 1992-11-20 Matsushita Electric Ind Co Ltd Information processor
JPH04344692A (en) * 1991-05-22 1992-12-01 Nec Eng Ltd Display device
JPH0594163A (en) * 1991-10-02 1993-04-16 Toshiba Corp System for controlling display
US5369771A (en) * 1991-12-23 1994-11-29 Dell U.S.A., L.P. Computer with transparent power-saving manipulation of CPU clock
DE9201166U1 (en) * 1992-01-31 1992-04-09 Siemens Nixdorf Informationssysteme Ag, 4790 Paderborn, De
EP0624272B1 (en) † 1992-01-31 1995-10-25 Siemens Nixdorf Informationssysteme Aktiengesellschaft Electrical functional unit and cathode ray tube display switchable into energy saving states
FI94571C (en) * 1992-03-02 1995-09-25 Icl Personal Systems Oy Video Display Device
US5423045A (en) * 1992-04-15 1995-06-06 International Business Machines Corporation System for distributed power management in portable computers
EP0880278B1 (en) * 1992-09-29 2002-12-11 Eizo Nanao Corporation CRT display unit and power supply control method therefor
KR950005216B1 (en) * 1993-03-31 1995-05-22 삼성전자주식회사 Power saving apparatus for pc

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3941989A (en) * 1974-12-13 1976-03-02 Mos Technology, Inc. Reducing power consumption in calculators
US4553166A (en) * 1983-12-07 1985-11-12 Zenith Electronics Corporation Video system with automatic power up
US4751502A (en) * 1985-03-27 1988-06-14 Ascii Corporation Display controller for displaying a cursor on either of a CRT display device or a liquid crystal display device
JPH0224696A (en) * 1988-07-13 1990-01-26 Toshiba Corp Display control system
US5059961A (en) * 1989-08-21 1991-10-22 Cheng Te J Screen blanker for a monitor of a computer system
US5079666A (en) * 1989-08-31 1992-01-07 International Business Machines Corporation Power supply shutdown through loss of sync

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7417600B2 (en) 1993-06-24 2008-08-26 Nintendo Co., Ltd. Electronic entertainment and communication system
US5923306A (en) * 1993-06-24 1999-07-13 Nintendo Co. Ltd. Hotel-based video game and communication system
US6047127A (en) * 1993-06-24 2000-04-04 Nintendo Co. Ltd. Electronic Entertainment and communications system
US6147696A (en) * 1993-06-24 2000-11-14 Nintendo Co. Ltd. Electronic entertainment and communication system
US6559812B1 (en) 1993-06-24 2003-05-06 Nintendo Co., Ltd. Airline-based video game and communications system
US6762733B2 (en) 1993-06-24 2004-07-13 Nintendo Co. Ltd. Electronic entertainment and communication system
GB2295702B (en) * 1994-11-30 1999-09-22 Lg Electronics Inc Control device for power conservation
WO1996041252A1 (en) * 1995-06-07 1996-12-19 Seiko Epson Corporation Computer system with video display controller having power saving modes
USRE38108E1 (en) 1995-06-07 2003-05-06 Seiko Epson Corporation Computer system with video display controller having power saving modes
JPH1097356A (en) * 1996-08-14 1998-04-14 Samsung Electron Co Ltd Power saving display device
EP0978780A1 (en) * 1998-08-06 2000-02-09 Elonex I.P. Holdings Limited Low-power-consumption monitor standby system
US6088806A (en) * 1998-10-20 2000-07-11 Seiko Epson Corporation Apparatus and method with improved power-down mode
US6327161B1 (en) 1999-01-13 2001-12-04 Acer Peripherals, Inc. Power-saving circuit
DE10000968B4 (en) * 1999-01-13 2006-11-09 Benq Corp., Kweishan Power supply circuit for an electronic device
CN106339063A (en) * 2016-08-26 2017-01-18 苏州佳世达电通有限公司 Display control circuit and control method
CN106339063B (en) * 2016-08-26 2019-04-23 苏州佳世达电通有限公司 A kind of display control circuit and control method

Also Published As

Publication number Publication date
EP1199697A3 (en) 2002-07-10
JP3848465B2 (en) 2006-11-22
DE69324702T3 (en) 2006-12-28
DE69333876D1 (en) 2006-02-02
DE69324702D1 (en) 1999-06-02
EP1199697A2 (en) 2002-04-24
EP0923065A1 (en) 1999-06-16
EP0678843B1 (en) 1999-04-28
DE69333442T2 (en) 2005-01-13
EP1199697B1 (en) 2005-09-21
DE672285T1 (en) 1996-03-14
DE69332748D1 (en) 2003-04-10
JPH11184577A (en) 1999-07-09
EP0672285A4 (en) 1996-02-07
ATE179531T1 (en) 1999-05-15
DE69332748T2 (en) 2004-03-18
ATE305161T1 (en) 2005-10-15
ATE233934T1 (en) 2003-03-15
DE69325106T2 (en) 1999-10-28
EP0678843A3 (en) 1996-01-24
ATE261167T1 (en) 2004-03-15
DE678843T1 (en) 1996-09-19
EP0865018A1 (en) 1998-09-16
ATE180592T1 (en) 1999-06-15
JP2847099B2 (en) 1999-01-13
EP0678843B2 (en) 2006-05-24
EP0923065B1 (en) 2004-03-03
JPH08508831A (en) 1996-09-17
US5880719A (en) 1999-03-09
EP0672285A1 (en) 1995-09-20
EP0678843A2 (en) 1995-10-25
EP0865018B1 (en) 2003-03-05
DE69324702T2 (en) 1999-10-14
EP0672285B1 (en) 1999-05-26
DE69333442D1 (en) 2004-04-08
US5648799A (en) 1997-07-15
DE1199697T1 (en) 2002-11-14
US5389952A (en) 1995-02-14
DE69325106D1 (en) 1999-07-01

Similar Documents

Publication Publication Date Title
US5389952A (en) Low-power-consumption monitor standby system
US5821924A (en) Computer peripherals low-power-consumption standby system
KR950010897B1 (en) Power controller and method of generating power management signals for p.c
US5448262A (en) Display screen blanking using interactive video and user-interface monitoring
US20190155364A1 (en) Display device, computer system and method of managing the operating states of a computer system
US5603040A (en) Power management control unit for a computer peripheral
JPH06250765A (en) Method and equipment for automatically reducing power consumption of monitor
US6404423B1 (en) Method for display power management and monitor equipped with a power management function
EP0978780B1 (en) Low-power-consumption monitor standby system
JP2000020185A (en) Display device
KR100303480B1 (en) Circuit and method for reserving power of display having usb board
JP2000056870A (en) Low-power-consumption monitor standby system
JPH05273950A (en) Picture display device
KR20020084568A (en) Method for controlling power of Monitor
KR20010038875A (en) A DPMS controller and the method thereof
KR20020085196A (en) Apparatus and method for controlling power of Monitor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1994903345

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1994903345

Country of ref document: EP

WWG Wipo information: grant in national office

Ref document number: 1994903345

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1994903345

Country of ref document: EP