WO1994028657A1 - Digital receiver for variable data rate communications - Google Patents

Digital receiver for variable data rate communications Download PDF

Info

Publication number
WO1994028657A1
WO1994028657A1 PCT/US1994/005671 US9405671W WO9428657A1 WO 1994028657 A1 WO1994028657 A1 WO 1994028657A1 US 9405671 W US9405671 W US 9405671W WO 9428657 A1 WO9428657 A1 WO 9428657A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
digital
output
receiver
filter
Prior art date
Application number
PCT/US1994/005671
Other languages
French (fr)
Inventor
Donald W. Becker
Fred Harris
James C. Tiernan
Original Assignee
Tv/Com Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tv/Com Technologies, Inc. filed Critical Tv/Com Technologies, Inc.
Priority to AU69169/94A priority Critical patent/AU692448B2/en
Priority to JP7500818A priority patent/JPH09501279A/en
Priority to BR9406664A priority patent/BR9406664A/en
Publication of WO1994028657A1 publication Critical patent/WO1994028657A1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal

Definitions

  • This invention relates generally to the reception and demodulation of communications signals, and more particularly, to the reception of such signals transmitted with arbitrarily selectable data rates.
  • data is formatted onto a carrier signal and transmitted by a transmitter. After the signal travels through some intervening medium, it is received and decoded by the receiver. Ideally, the waveform of the data would remain unchanged during the communications process. In practice, however, the waveform is distorted and corrupted by its passage both through the electronic circuitry of the transmitter and the receiver, and through the medium.
  • An important feature of the receiver is the processing of the received signal to determine the actual content of the data even though the transmitting signal has become distorted and corrupted during the transmission and reception process.
  • a data signal is created at one location on the earth, encoded onto a radio signal, and transmitted to a satellite in synchronous orbit above the earth.
  • the satellite retransmits the received signal to another location on the earth, where it is received and demodulated.
  • the data-carrying signal passes through several electronic systems, as much as 44,000 miles of free space, and twice through the atmosphere, and in all of these portions of the transmission it is subject to external interference and distortions.
  • the signal has been transmitted and processed entirely by analog techniques. More recently, digital signal processing techniques are being adopted because they permit more precise determination of the data content of the signal.
  • the receiver In digital signal processing, the receiver has a conventional tuner that receives and down converts the signal. The receiver thereafter samples the received analog signal to form a digital pulse train or signal. The digitized signal is further processed to extract the data content.
  • This known approach works well for the condition that the transmitted signal has a fixed data rate known to the receiver, which permits the receiver to be configured for the characteristics of the known transmitted signal.
  • a single satellite channel may be used to carry many different types of data signals, some of which are transmitted at a high data rate and some of which are transmitted at a low data rate.
  • the satellite channel carries a compressed video signal, it may be desirable to vary the data rate depending upon the type of programming being carried.
  • a video feed of a conference could be transmitted at a lower data rate than a video feed of a sports event, for example, due to the differences in the speed of the action. The lower the data rate of the signal, the more different types of data that could be carried by a single satellite channel.
  • the present invention provides a digital receiver that accommodates variable data rates in digital signal processing while performing primary sampling at a fixed clock rate.
  • the digital receiver automatically achieves initial acquisition of the baseband signal and remains locked to the data rate frequency of the signal through changes in the data rate of the baseband signal.
  • the invention accomplishes its purpose by means of a digital receiver for a transmitted analog signal having an arbitrarily variable data rate, being characterized by a source (24, 28, 30, 42) of a baseband analog signal (36), a first sampler (46) having an input of the baseband analog signal and a digital first sampler output (48), the first sampler (46) operating at a preselected fixed asynchronous sampling rate, a controllable digital filter (50) having a first input of the digital first sampler output and a second input of a time-shifting command signal, and an output (52) of a controllable digital resampled signal, means (56) for deterrmning a timing error signal of a data bit stream of the output of the controllable digital resampled signal, and a timing loop (60) having an input of the timing error signal of the data bit stream and an output of the time-shifting command signal to the controllable digital filter.
  • the invention also extends to the mode of operation of the digital receiver.
  • the invention embraces a method for receiving transmitted analog signals of arbitrarily variable data rate, the method characterized by providing an input analog signal (26), extracting a baseband signal (36) from the analog signal, low-pass filtering the baseband signal to produce low-pass filtered signal, sampling the low-pass filtered signal at a preselected fixed asynchronous sampling rate to produce a first sampler output (46), and resampling the first sampler output to derive a filter output having a selectable sampling rate and time position relationship to the baseband signal.
  • a feature of the digital receiver is its ability to acquire the received signal automatically when the receiver is first turned on.
  • the receiver is operated as a frequency spectrum analyzer.
  • the controllable digital resampling filter is operated at a narrow bandwidth to determine the signal strength or power at that bandwidth.
  • the center frequency of the resampling filter is incrementally shifted across the transponder bandwidth, to develop a power spectrum of the transponder signal.
  • the power spectrum is analyzed to determine a strong contributor, and the digital receiver is stored and locked onto that contributor.
  • the receiver reads a transport layer or header of information transmitted with the data stream of the baseband signal in that band.
  • the transport layer provides a menu to identify the center frequencies and bandwidths of other signals carried within the available frequency range and the information carried by those signals.
  • the complete header is carried by all signals, so that if one signal is acquired, all signals may be found. If the receiver seeks a signal other than that to which it first locked, it can be readily returned to the desired signal using the information in the header.
  • Subsequent scheduled changes in the center frequency or bandwidth are signalled by information carried in the baseband signal header.
  • the digital receiver recognizes this information, and accordingly reconfigures the receiver to follow the scheduled transmitter changes. A seamless transition is thereby achieved.
  • the present invention provides an important advance in the art of digital receivers.
  • the baseband signal is sampled at a fixed asynchronous rate, and this sampled data is resampled by a controllable digital filter at an optimal sampling rate for the data transmission rate.
  • the resampling filter is time position locked to the phase of the data transmission of the baseband signal epoch as it changes.
  • Fig. 1 is a block diagram of a receiver
  • Fig. 2 is a graph of a representation of a baseband signal, with indicated sampling
  • Fig. 3 is a schematic diagram of a polyphase filter
  • Fig. 4 is a block flow diagram for the acquisition of a signal upon startup of the system and the continuous monitoring of the signal for transmission changes during operation;
  • Fig. 5 is a graph of a power spectrum of the transmission channel;
  • Fig. 6 is a schematic representation of a header found in the data stream of each signal transmitted within a channel.
  • Fig. 7 is a block flow diagram of a self-compensation of the receiver for thermal drift of the local oscillator.
  • Fig. 1 is a block diagram of a digital receiver 20.
  • a transmitted analog signal 22 is received by a conventional tuner 24 appropriate for the band of the signal 22.
  • a received analog output signal 26 of the tuner 24 is amplified by a variable-gain amplifier 28 to an amplitude suitable for subsequent signal processing.
  • the I/Q components of the received analog signal 26 are separately processed in parallel, as shown in Fig. 1.
  • the processing is the same in each parallel path, and the following description applies to each of the paths.
  • the amplified received analog signal 26 is provided to a detector/mixer 30 as a first input.
  • a second input is an internally generated local oscillator (mixer) waveform 32 provided by a voltage-controlled oscillator 34.
  • the output of the detector/mixer 30 is a baseband signal 36 that contains the transmitted information, in this case a stream of digital waveforms.
  • the baseband signal strength of one of the I/Q components of the processing path is sampled at this point by an automatic gain control loop 38.
  • the AGC loop 38 provides a feedback amplitude control signal 40 to the variable-gain amplifier 28.
  • the gain of the amplifier 28 is adjusted to provide the required baseband signal strength for further processing.
  • the baseband signal 36 still in analog form, is filtered by a low-pass filter
  • the bandwidth and out-of-band attenuation of this filter 42 are selected to avoid spectral aliasing and spectral distortion of the out-of-band and in- band components, respectively, of the maximum bandwidth signal presented to the sampler.
  • subsequent digital sampling is at a fixed rate of 60 MHz, and the low-pass filter 42 is therefore selected to have a maximum bandpass of 15-30 MHz, preferably 20 MHz.
  • Data transmissions are therefore necessarily at a rate of 30 MHz or less per I/Q channel with this preferred embodiment.
  • a higher sampling rate would permit a higher maximum data transmission rate.
  • the filtered signal 44 is digitally sampled by a first sampler 46, preferably provided in the form of an analog-to-digital converter.
  • the first sampler 46 is operated at a fixed, asynchronous sampling rate dete ⁇ riined from a clock 47.
  • the sampling is asynchronous in the sense that the sampling rate is fixed and constant. There is no relation between the sampling rate and the symbol rate or frequency of the baseband signal, except that the sampling rate is sufficiently high that the conditions of the Nyquist sampling criterion are necessarily met for the highest frequency signal available to the receiver. Satisfaction of the sampling criterion is ensured by the selection of the bandpass frequency of the low-pass filter 42 in relation to the operating frequency of the first sampler 46. There may be more than two samples per symbol, when the symbol rate is less than the maximum permitted symbol rate.
  • the combination of the low-pass filter 42 and the first sampler 46 defines a maximum frequency for a particular mode of operation of the receiver 20.
  • Different selectable sets of fixed-rate digital samplers 46 and low-pass filters 42 can be used together to achieve various modes of operation, but vvithin any particular mode the operation of the sampler 46 remains at a fixed asynchronous rate.
  • a single reconfigurable fixed rate digital sampler and reconfigurable low-pass filter can be used to achieve various modes of operation.
  • the first sampler produces a digital first sampler output 48.
  • Fig. 2 depicts the analog baseband signal 44 in the time domain with the digital first sampler output 48 also indicated. There are necessarily at least two samples 48 per symbol. However, these samples 48 do not bear any fixed, known relation to the baseband signal 44.
  • the asynchronous samples 48 are not taken in a particular time position relation with the symbols transmitted or in any other relation to the symbols that is known a priori.
  • the first sampler output 48 is resampled by a controllable digital filter 50.
  • the filter 50 is preferably a multirate polyphase filter capable of either rational resampling capable of interpolation and decimation according to some ratio of integers A/B, or a variable rate polyphase filter capable of a continuously variable resampling at any continuous interpolation and/or decimation.
  • the filter 50 performs two key functions. It produces an output of a controllable digital resampled signal 52 that has twice the frequency of the symbol data rate of the baseband signal 36, to satisfy the Nyquist sampling criterion. Second, it ensures that the digital resampled signal 52 is time position locked to the baseband signal 36 so that the samples are taken at the symbol locations of the signal 36.
  • polyphase filters The basic structure and operation of polyphase filters is known, see, for example, Ronald E. Crochiere et al., "Multirate Digital Signal Processing", Prentice-Hall Company, pages 59 et seq., 1983, whose disclosure is incorporated by reference.
  • decimation and interpolation By a combination of decimation and interpolation, such filters can produce a digital sampling of an input signal at any selected rate.
  • the input is the digital first sampler signal 48 having a frequency at least as high as twice the symbol rate of the baseband signal.
  • the filter 50 therefore functions to produce the same or a lower effective sampling rate, time position locked to the timing of the digital first sampler signal 48.
  • the filter 50 operates by increasing the sampling rate to a higher value than that of the first sampler 46 to interpolate between the digital samples 48, producing a plurality of interpolated samples 54.
  • the larger number of interpolated samples 54 is decimated by selecting the proper number and positions of samples to correspond to the symbol rate of the baseband signal.
  • Fig. 3 schematically illustrates the operation of the polyphase filter 50.
  • the relation of sampled and resampled signals is indicated graphically.
  • the digital first sampler output stream 48 is supplied to each input of a plurality of A interpolators 80 of a polyphase filter bank 82.
  • Each interpolator interpolates between the points of the output stream 48 at the same constant frequency f s , the same rate as the first sampler 46, to produce its own interpolator output 84.
  • Two of the interpolator outputs 84 and 84' are shown, for the first interpolator (INTO) and the second interpolator (INT1).
  • the interpolator outputs 84 and 84' are at the same frequency f s , but time displaced from each other.
  • a commutator 86 operates on the interpolator outputs 84 to downsample or decimate the outputs 84 by a downsampling parameter B. If the downsampling parameter B is made equal to the upsampling parameter A, the filter bank 82 operates as a time-shifting or phasing filter. Time increment quantization is defined by the number of polyphase filter stages, and can be made arbitrarily fine by increasing A. In this mode, the filter bank can align output samples from the asynchronously sampled input stream 48 to arbitrary epochs in the input data.
  • the pointer of output commutator can precess in the appropriate direction to track the epochs.
  • an output sample rate with any rational ratio multiple of the input sample rate (f s A B) can be obtained. If the desired frequency is near a rational ratio, then it can be approximated with minor phase jitter by the same processing approach just described.
  • a processing B e.g., B'
  • the digital resampled signal 52 is amplified as necessary by a digital amplifier 53 controlled by a digital automatic gain control 55.
  • the amplified signal is resampled at the minimum permitted Nyquist rate by a resampler 57, whose output is processed by a matched filter 56 referenced to the transmitter waveforms and bandwidth.
  • An output 58 of the matched filter 56, a spectrally shaped bit stream synchronized to the original data stream that generated the baseband signal, is provided to further processing hardware, which is conventional.
  • the phase of the sampling of the controllable digital filter 50 is established in conjunction with the filter bank 82 discussed above, using a timing loop 60.
  • the error between the reference signal of the matched filter 56 and the digital resampled signal is a measure of the time position shift required in the controllable digital filter 50 to recover the timing and align the digital samples with the symbols encoded into the baseband.
  • the matched filter 56 indicates that the digital resampled signal points, indicated by circled pointer 62, is time position shifted from its respective symbol location by an error 64
  • the timing loop 60 shifts the time position of the resampling of the controllable digital filter 50 by interpolating to the desired positions, thereby reducing the error 64 to zero.
  • the phase error of the output signal I/Q pair 58 is detected by a phase error detector 61.
  • This phase error is provided, via a digital/analog converter 67, to the voltage controlled oscillator 34, which generates the frequency and phase coherent mixer waveform 32.
  • the controllable digital filter 50 and the matched filter 56 together form a controllable signal processor 62.
  • the filters 50 and 56 may be combined into a single polyphase filter.
  • controllable signal processor 62 is controlled in part by the timing loop 60 and in part by a microprocessor 65.
  • the controllable signal processor 62 also provides information to the microprocessor 65.
  • the ability to control and interact with the controllable signal processor 62, which contains the controllable digital filter 50, provides great flexibility and power to the receiver 20.
  • Fig. 4 illustrates both of these processes, in the context of system startup and continued monitoring of the symbol bit stream.
  • the center frequency and bandwidth must be assumed to be unknown, but within the general specifications of the hardware.
  • the center frequency and bandwidth of the signal are preselected, so that the receiver can be configured directly to those values upon startup.
  • the present approach permits the greatest extent of flexibility for those using the communications system with the receiver 20 of the invention.
  • the microprocessor 65 causes the controllable signal processor 62 to act as a narrow bandwidth, swept frequency spectrum analyzer.
  • the controllable digital filter 50 is operated as a narrow bandwidth filter, typically at about 2 MHz bandwidth.
  • the center frequency received by the controllable digital filter 50 is shifted by adjusting the voltage of the voltage controlled oscillator 34 to generate the mixer waveform 32 in a series of frequency steps which span the bandwidth available to the system.
  • the entire available bandwidth is swept, numeral 102.
  • the frequency step size is preferably equal to one-half the filter's bandwidth and the dwell time at each frequency position is sufficient to obtain a low variance estimate of the total signal power received at that frequency.
  • the total power in the received baseband signal is measured, numeral 104.
  • the output of the controllable digital filter 50 is resampled to the appropriate Nyquist rate and converted to a total power estimate by summing the squares of the signal samples.
  • the value of the power received at each frequency is stored in the microprocessor.
  • the spectral sweep 102 and power determination 104 may be repeated as many times as necessary to build a statistical base, with the results of all of the sweeps digitally averaged by a digital integrator.
  • the microprocessor 65 holds a power spectrum of the broadband of the system. This power spectrum contains one or more peaks 66 indicating the transmission of the corresponding signals available to the receiver.
  • Fig. 5 illustrates such a power spectrum.
  • the receiver 20 is tuned to the center frequency of any one of the signal peaks 66, numeral 106, preferably one of strong power indicating a clear signal available for decoding.
  • a symbol bit stream is established by the normal processing discussed previously. As illustrated in Fig. 6, each bit stream contains a transport layer 69 (also termed a "header") of information in addition to the data stream 70.
  • the data stream varies from signal to signal, but the transport layer 68 of each of the signals contains at least a menu 72 of all of the signals, corresponding to each of the spectral peaks in Fig. 5.
  • Each menu 72 of each signal contains a listing of each of the available i signals Sj and their respective center frequencies f; and bandwidths bj.
  • the menu of all signals S is read from the transport layer 68, numeral 108. If the microprocessor 65 determines from the menu that the signal of interest is in fact signal S 3 , the frequency f 3 and bandwidth b 3 are read from the menu 72. The tuner and receiver are immediately reconfigured to the frequency f 3 and bandwidth b 3 to complete the startup, numeral 110.
  • the signal acquisition is completed in about 100 milliseconds from startup.
  • the receiver 20 is operated to respond automatically to changes in the transmission parameters of the signal in the following manner.
  • the transport layer 68 is continuously monitored by the microprocessor 65, numeral 112.
  • the service supplier that provides the signal being monitored decides to change a transmission parameter such as the center frequency, the bandwidth, the symbol frequency, or other parameter
  • information indicating the planned change is encoded into a change block 74 of the transport layer 68.
  • the change block 74 typically would include the old parameters, the new parameters, and a countdown timer to the initiation of the new parameters.
  • the microprocessor 65 counts down to the initiation of the new parameters, numeral 114.
  • the microprocessor 65 instantaneously reconfigures the receiver to the new parameters, numeral 116. With this advance warning of the transmitting parameter change, the changeover is made in a seamless manner. Continuous monitoring of the transport layer 68 also provides information on other signals and their transmission changes, for use when the receiver is switched to a different signal. Switches and changeovers could be made instead by repeating the initiation procedures 102-110, but this would necessarily involve some loss of signal until the new signal parameters were determined.
  • the intelligence provided to the receiver 20 by the microprocessor 65 also is used to advantage in performing test and calibration procedures of the receiver.
  • the receiver 20 can instantaneously self- compensate for temperature changes that alter the frequency of an oscillator.
  • the microprocessor 65 monitors the frequency of the local oscillator of the tuner 24, numeral 120. The frequency is determined by counting the oscillator cycles for a fixed period of time, and converting the number of counts per interval into an oscillator actual cycles per second, numeral 122. The actual oscillator cycles per second is compared to a nominal value, numeral 124.

Abstract

A digital receiver (20) includes a tuner (24) and a demodulator (30) that obtains a baseband signal (36) carried in a received analog signal (22). A first sampler (46) operates at a preselected fixed asynchronous sampling rate on the baseband component to produce a first sampler output (48). A controllable digital filter (50) resamples the first sampler output to produce a filter output with a selectable resampling rate. The resampled output is time-position locked to baseband signal epochs. The resampling is processed to ascertain the bit stream of the baseband signal. The controllable filter sampling rate is automatically varied to correspond to the data rate of the baseband signal, so that the sampling rate of the first sampler need not change. Initial signal acquisition is achieved by operating the receiver as a frequency spectrum analyzer. A single signal-carrying band (66) is identified and demodulated, and a menu (72) carried on a transport layer (68) is read. This menu provides the center frequencies and bandwiths for all of the signals within an available frequency range, so that the receiver can be reconfigured for any desired signal. Changes in transmission characteristics of the signal can later be accommodated seamlessly by reading a change notice (74) transmitted in the transport layer and reconfiguring the receiver for the new transmission characteristics.

Description

DESCRIPTION DIGITAL RECEIVER FOR VARIABLE DATA RATE COMMUNICATIONS
TECHNICAL FIELD
This invention relates generally to the reception and demodulation of communications signals, and more particularly, to the reception of such signals transmitted with arbitrarily selectable data rates.
BACKGROUND ART
In a communications system, data is formatted onto a carrier signal and transmitted by a transmitter. After the signal travels through some intervening medium, it is received and decoded by the receiver. Ideally, the waveform of the data would remain unchanged during the communications process. In practice, however, the waveform is distorted and corrupted by its passage both through the electronic circuitry of the transmitter and the receiver, and through the medium. An important feature of the receiver is the processing of the received signal to determine the actual content of the data even though the transmitting signal has become distorted and corrupted during the transmission and reception process.
For example, in a typical satellite communications system a data signal is created at one location on the earth, encoded onto a radio signal, and transmitted to a satellite in synchronous orbit above the earth. The satellite retransmits the received signal to another location on the earth, where it is received and demodulated. The data-carrying signal passes through several electronic systems, as much as 44,000 miles of free space, and twice through the atmosphere, and in all of these portions of the transmission it is subject to external interference and distortions. Historically, the signal has been transmitted and processed entirely by analog techniques. More recently, digital signal processing techniques are being adopted because they permit more precise determination of the data content of the signal. In digital signal processing, the receiver has a conventional tuner that receives and down converts the signal. The receiver thereafter samples the received analog signal to form a digital pulse train or signal. The digitized signal is further processed to extract the data content.
This known approach works well for the condition that the transmitted signal has a fixed data rate known to the receiver, which permits the receiver to be configured for the characteristics of the known transmitted signal. In other instances, however, it is desirable to vary the data rate of the transmitter in an arbitrary manner. For example, a single satellite channel may be used to carry many different types of data signals, some of which are transmitted at a high data rate and some of which are transmitted at a low data rate. In another example, if the satellite channel carries a compressed video signal, it may be desirable to vary the data rate depending upon the type of programming being carried. A video feed of a conference could be transmitted at a lower data rate than a video feed of a sports event, for example, due to the differences in the speed of the action. The lower the data rate of the signal, the more different types of data that could be carried by a single satellite channel.
Several problems arise in complex communications systems having multiple channels, where the data rate is arbitrarily variable in each channel. As the data rate of the signal in a channel changes, the sampling rate of the sampler in the receiver must change in order to satisfy the Nyquist sampling criterion. The sampler is normally synchronized to a clock, which changes to permit the sampler to be varied to an arbitrary sampling rate. However, for other reasons it is strongly preferred not to change the clock rate in an arbitrary fashion so as to accommodate changes in the data rate. A second problem is that it is difficult to achieve initial acquisition of the data of the received information, when the channel is first activated. There is a need for a digital receiver system that is operable at variable rates, particularly in a multichannel communications system. The present invention fulfills this need, and further provides related advantages.
DISCLOSURE OF INVENTION The present invention provides a digital receiver that accommodates variable data rates in digital signal processing while performing primary sampling at a fixed clock rate. The digital receiver automatically achieves initial acquisition of the baseband signal and remains locked to the data rate frequency of the signal through changes in the data rate of the baseband signal. The invention accomplishes its purpose by means of a digital receiver for a transmitted analog signal having an arbitrarily variable data rate, being characterized by a source (24, 28, 30, 42) of a baseband analog signal (36), a first sampler (46) having an input of the baseband analog signal and a digital first sampler output (48), the first sampler (46) operating at a preselected fixed asynchronous sampling rate, a controllable digital filter (50) having a first input of the digital first sampler output and a second input of a time-shifting command signal, and an output (52) of a controllable digital resampled signal, means (56) for deterrmning a timing error signal of a data bit stream of the output of the controllable digital resampled signal, and a timing loop (60) having an input of the timing error signal of the data bit stream and an output of the time-shifting command signal to the controllable digital filter.
The invention also extends to the mode of operation of the digital receiver. In accordance with this aspect, the invention embraces a method for receiving transmitted analog signals of arbitrarily variable data rate, the method characterized by providing an input analog signal (26), extracting a baseband signal (36) from the analog signal, low-pass filtering the baseband signal to produce low-pass filtered signal, sampling the low-pass filtered signal at a preselected fixed asynchronous sampling rate to produce a first sampler output (46), and resampling the first sampler output to derive a filter output having a selectable sampling rate and time position relationship to the baseband signal.
A feature of the digital receiver is its ability to acquire the received signal automatically when the receiver is first turned on. To achieve the initial signal acquisition, the receiver is operated as a frequency spectrum analyzer. The controllable digital resampling filter is operated at a narrow bandwidth to determine the signal strength or power at that bandwidth. The center frequency of the resampling filter is incrementally shifted across the transponder bandwidth, to develop a power spectrum of the transponder signal. The power spectrum is analyzed to determine a strong contributor, and the digital receiver is stored and locked onto that contributor.
Once a single signal-carrying band has been identified and demodulated, the receiver reads a transport layer or header of information transmitted with the data stream of the baseband signal in that band. The transport layer provides a menu to identify the center frequencies and bandwidths of other signals carried within the available frequency range and the information carried by those signals. The complete header is carried by all signals, so that if one signal is acquired, all signals may be found. If the receiver seeks a signal other than that to which it first locked, it can be readily returned to the desired signal using the information in the header.
Subsequent scheduled changes in the center frequency or bandwidth are signalled by information carried in the baseband signal header. The digital receiver recognizes this information, and accordingly reconfigures the receiver to follow the scheduled transmitter changes. A seamless transition is thereby achieved.
The present invention provides an important advance in the art of digital receivers. The baseband signal is sampled at a fixed asynchronous rate, and this sampled data is resampled by a controllable digital filter at an optimal sampling rate for the data transmission rate. By a symbol timing loop operating from a timing error signal, the resampling filter is time position locked to the phase of the data transmission of the baseband signal epoch as it changes. Other features and advantages of the present invention will be apparent from the following more detailed description of the preferred embodiment, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention.
BRIEF DESCRIPTION OF DRAWING The objects, advantages and features of this invention will be more readily appreciated from the following detailed description, when read in conjunction with the accompanying drawing, in which:
Fig. 1 is a block diagram of a receiver;
Fig. 2 is a graph of a representation of a baseband signal, with indicated sampling;
Fig. 3 is a schematic diagram of a polyphase filter;
Fig. 4 is a block flow diagram for the acquisition of a signal upon startup of the system and the continuous monitoring of the signal for transmission changes during operation; Fig. 5 is a graph of a power spectrum of the transmission channel;
Fig. 6 is a schematic representation of a header found in the data stream of each signal transmitted within a channel; and
Fig. 7 is a block flow diagram of a self-compensation of the receiver for thermal drift of the local oscillator. BEST MODES FOR CARRYING OUT THE INVENTION
Fig. 1 is a block diagram of a digital receiver 20. A transmitted analog signal 22 is received by a conventional tuner 24 appropriate for the band of the signal 22. A received analog output signal 26 of the tuner 24 is amplified by a variable-gain amplifier 28 to an amplitude suitable for subsequent signal processing.
The I/Q components of the received analog signal 26 are separately processed in parallel, as shown in Fig. 1. The processing is the same in each parallel path, and the following description applies to each of the paths. The amplified received analog signal 26 is provided to a detector/mixer 30 as a first input. A second input is an internally generated local oscillator (mixer) waveform 32 provided by a voltage-controlled oscillator 34. The output of the detector/mixer 30 is a baseband signal 36 that contains the transmitted information, in this case a stream of digital waveforms. The baseband signal strength of one of the I/Q components of the processing path is sampled at this point by an automatic gain control loop 38. The AGC loop 38 provides a feedback amplitude control signal 40 to the variable-gain amplifier 28. The gain of the amplifier 28 is adjusted to provide the required baseband signal strength for further processing. The baseband signal 36, still in analog form, is filtered by a low-pass filter
42 that acts as an anti-aliasing filter for the subsequent digital sampling and processing. The bandwidth and out-of-band attenuation of this filter 42 are selected to avoid spectral aliasing and spectral distortion of the out-of-band and in- band components, respectively, of the maximum bandwidth signal presented to the sampler. In the preferred embodiment, subsequent digital sampling is at a fixed rate of 60 MHz, and the low-pass filter 42 is therefore selected to have a maximum bandpass of 15-30 MHz, preferably 20 MHz. Data transmissions are therefore necessarily at a rate of 30 MHz or less per I/Q channel with this preferred embodiment. A higher sampling rate would permit a higher maximum data transmission rate. These values are presented by way of illustration for a preferred embodiment, but other data rate modes can be selected as desired.
The filtered signal 44 is digitally sampled by a first sampler 46, preferably provided in the form of an analog-to-digital converter. The first sampler 46 is operated at a fixed, asynchronous sampling rate deteπriined from a clock 47. The sampling is asynchronous in the sense that the sampling rate is fixed and constant. There is no relation between the sampling rate and the symbol rate or frequency of the baseband signal, except that the sampling rate is sufficiently high that the conditions of the Nyquist sampling criterion are necessarily met for the highest frequency signal available to the receiver. Satisfaction of the sampling criterion is ensured by the selection of the bandpass frequency of the low-pass filter 42 in relation to the operating frequency of the first sampler 46. There may be more than two samples per symbol, when the symbol rate is less than the maximum permitted symbol rate.
This approach to the selection of the first sampler 46 is distinct from that of the art. In prior approaches, the digital sampler was operated at a variable rate to exactly satisfy the Nyquist sampling criterion for the symbol rate of the baseband signal. This approach requires multiple clocks for multiple channels, and multiple matched filters. There would be no universal clock, a significant disadvantage for a multichannel communication system.
The combination of the low-pass filter 42 and the first sampler 46 defines a maximum frequency for a particular mode of operation of the receiver 20. Different selectable sets of fixed-rate digital samplers 46 and low-pass filters 42 can be used together to achieve various modes of operation, but vvithin any particular mode the operation of the sampler 46 remains at a fixed asynchronous rate. Alternatively, a single reconfigurable fixed rate digital sampler and reconfigurable low-pass filter can be used to achieve various modes of operation. Referring again to Fig. 1, the first sampler produces a digital first sampler output 48. Fig. 2 depicts the analog baseband signal 44 in the time domain with the digital first sampler output 48 also indicated. There are necessarily at least two samples 48 per symbol. However, these samples 48 do not bear any fixed, known relation to the baseband signal 44. Specifically, the asynchronous samples 48 are not taken in a particular time position relation with the symbols transmitted or in any other relation to the symbols that is known a priori.
The first sampler output 48 is resampled by a controllable digital filter 50. The filter 50 is preferably a multirate polyphase filter capable of either rational resampling capable of interpolation and decimation according to some ratio of integers A/B, or a variable rate polyphase filter capable of a continuously variable resampling at any continuous interpolation and/or decimation. The filter 50 performs two key functions. It produces an output of a controllable digital resampled signal 52 that has twice the frequency of the symbol data rate of the baseband signal 36, to satisfy the Nyquist sampling criterion. Second, it ensures that the digital resampled signal 52 is time position locked to the baseband signal 36 so that the samples are taken at the symbol locations of the signal 36.
The basic structure and operation of polyphase filters is known, see, for example, Ronald E. Crochiere et al., "Multirate Digital Signal Processing", Prentice-Hall Company, pages 59 et seq., 1983, whose disclosure is incorporated by reference. By a combination of decimation and interpolation, such filters can produce a digital sampling of an input signal at any selected rate. In this case, the input is the digital first sampler signal 48 having a frequency at least as high as twice the symbol rate of the baseband signal. The filter 50 therefore functions to produce the same or a lower effective sampling rate, time position locked to the timing of the digital first sampler signal 48.
As indicated in Fig. 2, the filter 50 operates by increasing the sampling rate to a higher value than that of the first sampler 46 to interpolate between the digital samples 48, producing a plurality of interpolated samples 54. The larger number of interpolated samples 54 is decimated by selecting the proper number and positions of samples to correspond to the symbol rate of the baseband signal.
Fig. 3 schematically illustrates the operation of the polyphase filter 50. The relation of sampled and resampled signals is indicated graphically. The digital first sampler output stream 48 is supplied to each input of a plurality of A interpolators 80 of a polyphase filter bank 82. Each interpolator interpolates between the points of the output stream 48 at the same constant frequency fs, the same rate as the first sampler 46, to produce its own interpolator output 84. Two of the interpolator outputs 84 and 84' are shown, for the first interpolator (INTO) and the second interpolator (INT1). The interpolator outputs 84 and 84' are at the same frequency fs, but time displaced from each other. By the appropriate choice of the time displacements according to the number of interpolators 80 in the filter bank 82, the filter bank 82 produces A upsampled interpolation points between each of the digital first sampler points 48.
A commutator 86 operates on the interpolator outputs 84 to downsample or decimate the outputs 84 by a downsampling parameter B. If the downsampling parameter B is made equal to the upsampling parameter A, the filter bank 82 operates as a time-shifting or phasing filter. Time increment quantization is defined by the number of polyphase filter stages, and can be made arbitrarily fine by increasing A. In this mode, the filter bank can align output samples from the asynchronously sampled input stream 48 to arbitrary epochs in the input data. If the frequency of the sampling clock fs used to form uniformly spaced samples and the frequency of periodic epochs fe in the underlying data differ by a small percentage the pointer of output commutator can precess in the appropriate direction to track the epochs. Thus, rather than increment the commutator 86 in equal steps of length A, the output pointer is instead incremented in steps of A for M-l samples and then in steps of A+/-1 at the Mth sample, according to the relation f/f. = [(M-l)A + (A+/-l)]/M.
When the output incrementing factor B is chosen to be different from the input incrementing factor A, an output sample rate with any rational ratio multiple of the input sample rate (fsA B) can be obtained. If the desired frequency is near a rational ratio, then it can be approximated with minor phase jitter by the same processing approach just described. For a sufficiently large A, the use of a processing B (e.g., B') permits the formation of time matched samples at any output rate. The digital resampled signal 52 is amplified as necessary by a digital amplifier 53 controlled by a digital automatic gain control 55. The amplified signal is resampled at the minimum permitted Nyquist rate by a resampler 57, whose output is processed by a matched filter 56 referenced to the transmitter waveforms and bandwidth. An output 58 of the matched filter 56, a spectrally shaped bit stream synchronized to the original data stream that generated the baseband signal, is provided to further processing hardware, which is conventional.
The phase of the sampling of the controllable digital filter 50 is established in conjunction with the filter bank 82 discussed above, using a timing loop 60.
The error between the reference signal of the matched filter 56 and the digital resampled signal is a measure of the time position shift required in the controllable digital filter 50 to recover the timing and align the digital samples with the symbols encoded into the baseband. Referring to Fig. 2, if the matched filter 56 indicates that the digital resampled signal points, indicated by circled pointer 62, is time position shifted from its respective symbol location by an error 64, the timing loop 60 shifts the time position of the resampling of the controllable digital filter 50 by interpolating to the desired positions, thereby reducing the error 64 to zero. The phase error of the output signal I/Q pair 58 is detected by a phase error detector 61. This phase error is provided, via a digital/analog converter 67, to the voltage controlled oscillator 34, which generates the frequency and phase coherent mixer waveform 32. The controllable digital filter 50 and the matched filter 56 together form a controllable signal processor 62. The filters 50 and 56 may be combined into a single polyphase filter.
In the preferred approach, the controllable signal processor 62 is controlled in part by the timing loop 60 and in part by a microprocessor 65. The controllable signal processor 62 also provides information to the microprocessor 65. The ability to control and interact with the controllable signal processor 62, which contains the controllable digital filter 50, provides great flexibility and power to the receiver 20.
An important function of the microprocessor 65 is to support the initial signal acquisition by the receiver and to aid in making a seamless shift responsive to announced changes in the transmitted signal. Fig. 4 illustrates both of these processes, in the context of system startup and continued monitoring of the symbol bit stream.
At system startup, numeral 100, the center frequency and bandwidth must be assumed to be unknown, but within the general specifications of the hardware. By contrast, in most types of signal communications the center frequency and bandwidth of the signal are preselected, so that the receiver can be configured directly to those values upon startup. The present approach permits the greatest extent of flexibility for those using the communications system with the receiver 20 of the invention.
To locate the unknown center frequency and bandwidth, the microprocessor 65 causes the controllable signal processor 62 to act as a narrow bandwidth, swept frequency spectrum analyzer. The controllable digital filter 50 is operated as a narrow bandwidth filter, typically at about 2 MHz bandwidth. The center frequency received by the controllable digital filter 50 is shifted by adjusting the voltage of the voltage controlled oscillator 34 to generate the mixer waveform 32 in a series of frequency steps which span the bandwidth available to the system. The entire available bandwidth is swept, numeral 102. The frequency step size is preferably equal to one-half the filter's bandwidth and the dwell time at each frequency position is sufficient to obtain a low variance estimate of the total signal power received at that frequency.
At each frequency, the total power in the received baseband signal is measured, numeral 104. To determine the total power transmitted in each frequency band sample, the output of the controllable digital filter 50 is resampled to the appropriate Nyquist rate and converted to a total power estimate by summing the squares of the signal samples. The value of the power received at each frequency is stored in the microprocessor. The spectral sweep 102 and power determination 104 may be repeated as many times as necessary to build a statistical base, with the results of all of the sweeps digitally averaged by a digital integrator. At the completion of the sweeps and power determination, the microprocessor 65 holds a power spectrum of the broadband of the system. This power spectrum contains one or more peaks 66 indicating the transmission of the corresponding signals available to the receiver. Fig. 5 illustrates such a power spectrum.
The receiver 20 is tuned to the center frequency of any one of the signal peaks 66, numeral 106, preferably one of strong power indicating a clear signal available for decoding. A symbol bit stream is established by the normal processing discussed previously. As illustrated in Fig. 6, each bit stream contains a transport layer 69 (also termed a "header") of information in addition to the data stream 70. The data stream varies from signal to signal, but the transport layer 68 of each of the signals contains at least a menu 72 of all of the signals, corresponding to each of the spectral peaks in Fig. 5. Each menu 72 of each signal contains a listing of each of the available i signals Sj and their respective center frequencies f; and bandwidths bj. Thus, for example, if the receiver happened to select signal S2 in step 106, the menu of all signals S; is read from the transport layer 68, numeral 108. If the microprocessor 65 determines from the menu that the signal of interest is in fact signal S3, the frequency f3 and bandwidth b3 are read from the menu 72. The tuner and receiver are immediately reconfigured to the frequency f3 and bandwidth b3 to complete the startup, numeral 110.
In a typical case, it is estimated that the signal acquisition is completed in about 100 milliseconds from startup.
After startup, the receiver 20 is operated to respond automatically to changes in the transmission parameters of the signal in the following manner. During receipt of the symbol bit stream of a signal, the transport layer 68 is continuously monitored by the microprocessor 65, numeral 112. In the event that the service supplier that provides the signal being monitored decides to change a transmission parameter such as the center frequency, the bandwidth, the symbol frequency, or other parameter, information indicating the planned change is encoded into a change block 74 of the transport layer 68. The change block 74 typically would include the old parameters, the new parameters, and a countdown timer to the initiation of the new parameters. The microprocessor 65 counts down to the initiation of the new parameters, numeral 114. At the time of the change to the new signal parameters, the microprocessor 65 instantaneously reconfigures the receiver to the new parameters, numeral 116. With this advance warning of the transmitting parameter change, the changeover is made in a seamless manner. Continuous monitoring of the transport layer 68 also provides information on other signals and their transmission changes, for use when the receiver is switched to a different signal. Switches and changeovers could be made instead by repeating the initiation procedures 102-110, but this would necessarily involve some loss of signal until the new signal parameters were determined.
The intelligence provided to the receiver 20 by the microprocessor 65 also is used to advantage in performing test and calibration procedures of the receiver. As an example of the calibration function, the receiver 20 can instantaneously self- compensate for temperature changes that alter the frequency of an oscillator. As shown in Fig. 7, the microprocessor 65 monitors the frequency of the local oscillator of the tuner 24, numeral 120. The frequency is determined by counting the oscillator cycles for a fixed period of time, and converting the number of counts per interval into an oscillator actual cycles per second, numeral 122. The actual oscillator cycles per second is compared to a nominal value, numeral 124. The difference, a calibration for thermal drift or other variation of the tuner oscillator, is provided to the time position-locked loop of the tuning control, numeral 126. Although a particular embodiment of the invention has been described in detail for purposes of illustration, various modifications and enhancements may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims.

Claims

1. A digital receiver for a transmitted analog signal having an arbitrarily variable data rate, being characterized by: a source (24, 28, 30, 42) of a baseband analog signal (36); a first sampler (46) having an input of the baseband analog signal and a digital first sampler output (48), the first sampler operating at a preselected fixed asynchronous sampling rate; a controllable digital filter (50) having a first input of the digital first sampler output and a second input of a time-shifting command signal, and an output (52) of a controllable digital resampled signal; means (56) for determining a timing error signal of a data bit stream of the output of the controllable digital resampled signal; and a timing loop (60) having an input of the timing error signal of the data bit stream and an output of the time-shifting command signal to the controllable digital filter.
2. The digital receiver of claim 1, wherein the source (24, 28, 30, 42) of the baseband signal comprises: a tuner (24) having the transmitted analog signal as an input and a received analog signal as an output, a demodulator (30, 32, 34) having a first input of the received analog signal and a second input of a mixer waveform, and an output of the baseband signal modulated on the received analog signal, and a low pass analog filter (42) having an input of the baseband signal and an output of a filtered baseband signal comprising the baseband analog signal.
3. The digital receiver of claim 1, further including: a voltage controlled oscillator (34) having an input of a voltage control signal and an output of the mixer waveform.
4. The digital receiver of claim 1, wherein the means (56) for deterniining a timing error signal includes: a matched filter (56) having an input of the controllable digital resampled signal, and a first output (58) of a spectrally shaped data bit stream and a second output of a timing error signal of the data bit stream.
5. The digital receiver of claim 1, further including: means (34, 62, 65) for identifying the bandwidth and center frequency of a transmitted analog signal at the initiation of operation.
6. The digital receiver of claim 5, wherein the means (34, 62, 65) for identifying includes: means (65) for controlling the controllable digital filter to operate at a narrow bandwidth; means (34, 62) for sweeping the narrow bandwidth of the controllable digital filter over a range of narrow bandwidths; means (65) for deterniining the power spectrum of the outputs of the controllable digital filter over the range of narrow bandwidths; and means (65) for selecting a center frequency and bandwidth from the power spectrum.
7. The digital receiver of claim 1, further including: a system clock (47) that provides a clock rate to the first sampler.
8. The digital receiver of claim 1, wherein the controllable digital filter is a multirate polyphase filter.
9. The digital receiver of claim 1, wherein the controllable digital filter is a variable rate polyphase filter.
10. The digital receiver of claim 1, further including: means (65) for reading a header data signal of the data bit stream.
11. A digital receiver for a transmitted analog signal having an arbitrarily variable data rate, being characterized by: a source (24, 28, 30, 42) of a baseband signal; first sampler means (46) for sampling the baseband signal at a preselected fixed asynchronous sampling rate to produce a first digital sampler means output; and controllable digital filter means (50) for receiving the first digital sampler means output and producing a spectrally shaped filter output with a selectable sampling rate and time position relationship to the baseband signal.
12. The digital receiver of claim 11, further including: means (56, 60) for controlling the digital filter means to obtain an optimal sampling rate and to lock the time position relationship to the baseband signal.
13. The digital receiver of claim 11 , wherein the source of the baseband signal comprises: tuner means (24) for receiving the transmitted analog signal and producing a received analog signal; mixer/translator means (30) for translating the received analog signal to the baseband signal; and low pass analog filter means (42) for filtering the baseband signal.
14. The digital receiver of claim 11, further including: means (34, 62, 65) for identifying the bandwidth and center frequency of a transmitted analog signal at the initiation of operation.
15. The digital receiver of claim 14, wherein the means for identifying includes: means (65) for controlling the controllable digital filter to operate at a narrow bandwidth; means (34, 62) for sweeping the narrow bandwidth of the controllable digital filter over a range of narrow bandwidths; means (65) for determining the power spectrum of the outputs of the controllable digital filter over the range of narrow bandwidths; and means (65) for selecting a center frequency and bandwidth from the power spectrum.
16. A method for receiving transmitted analog signals of arbitrarily variable data rate, being characterized by: providing an input analog signal (26); extracting a baseband signal (36) from the analog signal; low-pass filtering the baseband signal to produce a low-pass filtered signal (44); sampling the low-pass filtered signal at a preselected fixed asynchronous sampling rate to produce a first sampler output (48); and resampling the first sampler output to derive a filter output (52) having a selectable sampling rate and time position relationship to the baseband signal.
17. The method of claim 16, wherein the step of providing an input analog signal includes: receiving the transmitted analog signal with an analog tuner (24) that produces a received analog signal.
18. The method of claim 16, including the additional step, after the step of resampling, of: varying the selectable sampling rate of the step of resampling responsive to a change in a data rate of the input analog signal.
19. A method for receiving transmitted signals in which at least two signals are carried on a single carrier, being characterized by: providing a transmitted analog signal (22) having at least two transmitted signals thereon, each of the transmitted signals having a transport layer (69) and a symbol bit stream (70); identifying a center frequency and bandwidth for one of the transmitted signals (66); and reading a menu (72) of center frequencies and bandwidths of each of the transmitted signals from the transport layer of the identified transmitted signal.
20. The method of claim 19, including the additional step, after the step of providing and before the step of identifying, of: producing a digital signal from the transmitted analog signal, the digital signal having the transport layer and the symbol bit stream in digital form.
21. The method of claim 19, including the additional step, after the step of reading, of: tuning a receiver (20) to one of the transmitted signals different from the transmitted signal selected in the step of identifying.
22. A method for receiving transmitted signals, being characterized by: providing (106) a transmitted signal according to a first set of transmission parameters, the transmitted signal having a transport layer (68) and a symbol bit stream (70) , the transport layer having an indication (74) thereon of a subsequent change to a second set of transmission parameters and the time at which the change is to occur; reading the transport layer to determine the time of the subsequent change and the second set of transmission parameters; and tuning a receiver (20) according to the second set of transmission parameters responsive to the time at which the change is to occur as read from the transport layer.
PCT/US1994/005671 1993-05-28 1994-05-20 Digital receiver for variable data rate communications WO1994028657A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU69169/94A AU692448B2 (en) 1993-05-28 1994-05-20 Digital receiver for variable data rate communications
JP7500818A JPH09501279A (en) 1993-05-28 1994-05-20 Digital receiver for variable data rate communication
BR9406664A BR9406664A (en) 1993-05-28 1994-05-20 Digital receiver for variable data speed communications

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/068,560 US5504785A (en) 1993-05-28 1993-05-28 Digital receiver for variable symbol rate communications
US08/068,560 1993-05-28

Publications (1)

Publication Number Publication Date
WO1994028657A1 true WO1994028657A1 (en) 1994-12-08

Family

ID=22083327

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1994/005671 WO1994028657A1 (en) 1993-05-28 1994-05-20 Digital receiver for variable data rate communications

Country Status (17)

Country Link
US (2) US5504785A (en)
EP (1) EP0627830B1 (en)
JP (1) JPH09501279A (en)
AT (1) ATE137372T1 (en)
AU (1) AU692448B2 (en)
BR (1) BR9406664A (en)
CA (1) CA2161626A1 (en)
DE (1) DE69400162T2 (en)
DK (1) DK0627830T3 (en)
ES (1) ES2088697T3 (en)
GR (1) GR3020548T3 (en)
HK (1) HK150796A (en)
IL (1) IL109736A (en)
MY (1) MY110750A (en)
PH (1) PH31698A (en)
SI (1) SI0627830T1 (en)
WO (1) WO1994028657A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5812608A (en) * 1995-05-05 1998-09-22 Nokia Technology Gmbh Method and circuit arrangement for processing received signal
DE102004008227A1 (en) * 2004-02-19 2005-09-15 Infineon Technologies Ag Adjustment method for maximum power in a fractional delay in a digitally modulated, analog receiving signal (RS) in a communications receiving device uses RS to generate an over-scanned bit stream

Families Citing this family (129)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268696A (en) * 1993-03-10 1994-09-22 Toyo Commun Equip Co Ltd Afc circuit
US6512555B1 (en) * 1994-05-04 2003-01-28 Samsung Electronics Co., Ltd. Radio receiver for vestigal-sideband amplitude-modulation digital television signals
CA2169266C (en) * 1994-06-10 2006-01-10 Shogo Ito Receiver with symbol rate sync
EP0696848B1 (en) * 1994-08-08 2000-04-05 Micronas Intermetall GmbH Method of digital signal interpolation
FI112132B (en) * 1995-02-21 2003-10-31 Tait Electronics Ltd Zero intermediate frequency receiver
FR2731310B1 (en) * 1995-03-02 1997-04-11 Alcatel Telspace DEVICE AND METHOD FOR MULTIDEBIT RECEPTION WITH SINGLE FILTERING OF INTERPOLATION AND ADAPTATION
JP3403849B2 (en) * 1995-03-17 2003-05-06 富士通株式会社 Clock phase detection circuit and clock recovery circuit provided in receiving section of multiplex radio apparatus
US5640416A (en) * 1995-06-07 1997-06-17 Comsat Corporation Digital downconverter/despreader for direct sequence spread spectrum communications system
US6212245B1 (en) * 1995-07-13 2001-04-03 Canon Kabushiki Kaisha Communication apparatus
KR0170301B1 (en) * 1995-10-30 1999-04-15 김광호 Integrated phase filter and timing error compensation device thereof and method therefor
JP3225837B2 (en) * 1996-04-19 2001-11-05 松下電器産業株式会社 High frequency signal receiver
JP4505565B2 (en) * 1996-05-08 2010-07-21 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴイ Transmission of a digital information signal having a specific first sampling frequency
FR2752348B1 (en) * 1996-08-07 1998-09-18 Telecommunications Sa DEMODULATOR WITH DIGITAL CARRIER AND RHYTHM RECOVERY CIRCUIT
US5864559A (en) * 1996-08-23 1999-01-26 Ascend Communications, Inc. ISDN modem capable of self-configuring to use one of a variety of pre-programmed ISDN protocols
US5878088A (en) * 1997-04-10 1999-03-02 Thomson Consumer Electronics, Inc. Digital variable symbol timing recovery system for QAM
KR100195756B1 (en) * 1996-09-30 1999-06-15 전주범 Symbol timing restructing circuit of variable rate demodulation
US5914959A (en) * 1996-10-31 1999-06-22 Glenayre Electronics, Inc. Digital communications system having an automatically selectable transmission rate
US5963594A (en) * 1996-12-31 1999-10-05 Lucent Technologies Inc. Vector tracking filter
US5838741A (en) * 1997-02-10 1998-11-17 Motorola, Inc. Communication device and method for reducing effects of noise introduction by synchronizing data transfer to a received signal
US6169767B1 (en) * 1997-03-10 2001-01-02 Sarnoff Corporation Universal network interface module
US6178316B1 (en) * 1997-04-29 2001-01-23 Meta-C Corporation Radio frequency modulation employing a periodic transformation system
US6160858A (en) * 1997-08-04 2000-12-12 Starlink, Inc. MSK signal processing in a GPS correlator channel
US6539064B1 (en) * 1997-09-02 2003-03-25 Intermec Ip Corp. Multiple data rate filtered modulation system for digital data
US20020170735A1 (en) * 1997-09-05 2002-11-21 Bicc General Uk Cables Limited. Electric cable joints and methods of making them
US6014554A (en) * 1997-09-30 2000-01-11 Lucent Technologies, Inc. Method and apparatus for tuning analog filters
US6313765B1 (en) * 1997-10-10 2001-11-06 L-3 Communications Corporation Method for sample rate conversion of digital data
US6654432B1 (en) * 1998-06-08 2003-11-25 Wireless Facilities, Inc. Joint maximum likelihood frame and timing estimation for a digital receiver
US5973740A (en) * 1997-10-27 1999-10-26 International Business Machines Corporation Multi-format reduced memory video decoder with adjustable polyphase expansion filter
GB9723052D0 (en) * 1997-10-31 1998-01-07 Thomson Consumer Electronics High definition television vsb receiver
US6356598B1 (en) * 1998-08-26 2002-03-12 Thomson Licensing S.A. Demodulator for an HDTV receiver
KR100250072B1 (en) * 1997-11-20 2000-03-15 선우명훈 Timing recovery circuit of digital communication receiver and its timing recovery method
US6128357A (en) * 1997-12-24 2000-10-03 Mitsubishi Electric Information Technology Center America, Inc (Ita) Data receiver having variable rate symbol timing recovery with non-synchronized sampling
US6167098A (en) * 1998-01-16 2000-12-26 Lsi Logic Corporation Method and apparatus for digital interference rejection
US6714608B1 (en) * 1998-01-27 2004-03-30 Broadcom Corporation Multi-mode variable rate digital satellite receiver
IL123739A (en) * 1998-03-19 2001-11-25 Infineon Technologies Ag Method and apparatus for clock timing recovery in xdsl, particularly vdsl modems
US6304621B1 (en) 1998-05-13 2001-10-16 Broadcom Corporation Multi-mode variable rate digital cable receiver
US6157820A (en) * 1998-06-12 2000-12-05 Ericsson Inc. Pilot strength measurement and multipath delay searcher for CDMA receiver
US6298103B1 (en) * 1998-06-16 2001-10-02 Sorrento Networks Corporation Flexible clock and data recovery module for a DWDM optical communication system with multiple clock rates
US6282248B1 (en) * 1998-07-14 2001-08-28 Agere Systems Guardian Corp. Variable baud rate demodulator
US6647074B2 (en) * 1998-08-25 2003-11-11 Zenith Electronics Corporation Removal of clock related artifacts from an offset QAM generated VSB signal
US6337636B1 (en) * 1998-09-16 2002-01-08 Cirrus Logic, Inc. System and techniques for seismic data acquisition
US6134268A (en) * 1998-10-19 2000-10-17 Motorola, Inc. Apparatus for performing a non-integer sampling rate change in a multichannel polyphase filter
DE69939781D1 (en) * 1998-10-30 2008-12-04 Broadcom Corp CABLE MODEM SYSTEM
US7103065B1 (en) * 1998-10-30 2006-09-05 Broadcom Corporation Data packet fragmentation in a cable modem system
US6961314B1 (en) * 1998-10-30 2005-11-01 Broadcom Corporation Burst receiver for cable modem system
US20020090037A1 (en) * 1998-12-23 2002-07-11 Xiaoyun Hu System and method for variable bandwidth transmission
US6757340B1 (en) * 1999-02-22 2004-06-29 Telefonaktiebolaget L M Ericsson (Publ) Radio receiver and method for preloading an average DC-offset into a channel filter
SE516182C2 (en) * 1999-02-26 2001-11-26 Ericsson Telefon Ab L M Receiving different signal format standards in multi-standard radio systems
US6707863B1 (en) 1999-05-04 2004-03-16 Northrop Grumman Corporation Baseband signal carrier recovery of a suppressed carrier modulation signal
US6218896B1 (en) * 1999-08-27 2001-04-17 Tachyon, Inc. Vectored demodulation and frequency estimation apparatus and method
US6452982B1 (en) * 1999-09-10 2002-09-17 Raytheon Company Method and system for-down-converting a signal
FI114887B (en) * 1999-10-13 2005-01-14 U Nav Microelectronics Corp Signal detection system of a spread spectrum receiver
US7130579B1 (en) * 1999-10-21 2006-10-31 Broadcom Corporation Adaptive radio transceiver with a wide tuning range VCO
US6650688B1 (en) * 1999-12-20 2003-11-18 Intel Corporation Chip rate selectable square root raised cosine filter for mobile telecommunications
US6252453B1 (en) * 2000-01-20 2001-06-26 Advanced Micro Devices, Inc. Device and method for signal resampling between phase related clocks
US6683905B1 (en) 2000-04-17 2004-01-27 Rf Micro Devices, Inc. Dual-mode receiver
DE10024267A1 (en) * 2000-05-17 2001-11-29 Bosch Gmbh Robert Radio receiver for receiving digital radio signals and method for receiving digital radio signals
US6879627B1 (en) * 2000-06-01 2005-04-12 Shiron Satellite Communications (1996) Ltd. Variable rate continuous mode satellite modem
GB2364478A (en) * 2000-06-30 2002-01-23 Nokia Oy Ab Cellular broadcast system responsive to distribution of demand
US7298691B1 (en) 2000-08-04 2007-11-20 Intellon Corporation Method and protocol to adapt each unique connection in a multi-node network to a maximum data rate
US6724439B1 (en) * 2000-08-04 2004-04-20 Zenith Electronics Corporation Low cost VSB encoder and RF modulator for supplying a substantially 6 MHZ VSB signal to digital television receiver
US6907044B1 (en) 2000-08-04 2005-06-14 Intellon Corporation Method and protocol to support contention-free intervals and QoS in a CSMA network
US7469297B1 (en) 2000-08-04 2008-12-23 Intellon Corporation Mechanism for using a quasi-addressed response to bind to a message requesting the response
US7352770B1 (en) * 2000-08-04 2008-04-01 Intellon Corporation Media access control protocol with priority and contention-free intervals
US6909723B1 (en) 2000-08-04 2005-06-21 Intellon Corporation Segment bursting with priority pre-emption and reduced latency
US6987770B1 (en) 2000-08-04 2006-01-17 Intellon Corporation Frame forwarding in an adaptive network
US6983047B1 (en) * 2000-08-29 2006-01-03 Lucent Technologies Inc. Echo canceling system for a bit pump and method of operating the same
US6973146B1 (en) * 2000-08-29 2005-12-06 Lucent Technologies Inc. Resampler for a bit pump and method of resampling a signal associated therewith
US6785080B1 (en) * 2000-10-10 2004-08-31 Maxtor Corporation Method and apparatus for providing a variable rate oversampling digital filter for resonance compensation in disk drive servo control systems
KR100400752B1 (en) * 2001-02-07 2003-10-08 엘지전자 주식회사 Apparatus for VSB demodulating in digital TV receiver
US7076225B2 (en) * 2001-02-16 2006-07-11 Qualcomm Incorporated Variable gain selection in direct conversion receiver
US7095801B1 (en) * 2001-03-30 2006-08-22 Skyworks Solutions, Inc. Phase adjustable polyphase filters
US6985550B2 (en) * 2001-04-30 2006-01-10 Agere Systems Inc. Jitter control processor and a transceiver employing the same
US7164741B2 (en) * 2001-05-09 2007-01-16 Signum Concept, Inc. Non-recursive resampling digital fir filter structure for demodulating 3G cellular signals
US7158591B2 (en) * 2001-05-09 2007-01-02 Signum Concept, Inc. Recursive resampling digital filter structure for demodulating 3G wireless signals
FR2825550B1 (en) * 2001-05-30 2003-09-05 Mitsubishi Electric Inf Tech DEVICE AND METHOD FOR DIGITAL DEMODULATION OF A SIGNAL RECEIVED BY SELECTION OF A FILTER AND DIGITAL COMMUNICATION RECEIVER COMPRISING SAME
US6931089B2 (en) * 2001-08-21 2005-08-16 Intersil Corporation Phase-locked loop with analog phase rotator
US7415088B2 (en) * 2001-08-31 2008-08-19 Qualcomm Incorporated Multi-standard baseband receiver
DE10157864B4 (en) * 2001-11-26 2006-08-10 Infineon Technologies Ag Quadrature Amplitude Modulation (QAM) receiver
US7026985B2 (en) * 2002-01-15 2006-04-11 Accord Softwire And Systems Pvt. Ltd. Global positioning system receiver
US6999132B1 (en) 2002-02-19 2006-02-14 Lsi Logic Corporation RF/IF digital demodulation of video and audio
US6954114B2 (en) * 2002-04-26 2005-10-11 Broadcom Corporation NCO with rational frequency and normalized phase
US6917247B2 (en) * 2002-04-26 2005-07-12 Broadcom Corporation NCO based timebase recovery system and method for A/V decoder
US7035339B2 (en) * 2002-05-03 2006-04-25 Silicon Integrated Systems Corp. Carrier recovery apparatus for digital QAM receivers
US7120847B2 (en) * 2002-06-26 2006-10-10 Intellon Corporation Powerline network flood control restriction
US8149703B2 (en) * 2002-06-26 2012-04-03 Qualcomm Atheros, Inc. Powerline network bridging congestion control
US7826466B2 (en) * 2002-06-26 2010-11-02 Atheros Communications, Inc. Communication buffer scheme optimized for VoIP, QoS and data networking over a power line
AU2003284317A1 (en) 2002-10-21 2004-05-13 Intellon Corporation Contention-free access intervals on a csma network
US7170956B1 (en) * 2003-01-15 2007-01-30 Wideband Semiconductors, Inc Frequency agile tuner and variable rate decimator for digital demodulator
KR100519360B1 (en) * 2003-09-17 2005-10-07 엘지전자 주식회사 Digital Cable Receiver
US7281187B2 (en) 2003-11-20 2007-10-09 Intellon Corporation Using error checking bits to communicated an address or other bits
US8090857B2 (en) * 2003-11-24 2012-01-03 Qualcomm Atheros, Inc. Medium access control layer that encapsulates data from a plurality of received data units into a plurality of independently transmittable blocks
US7272178B2 (en) * 2003-12-08 2007-09-18 Freescale Semiconductor, Inc. Method and apparatus for controlling the bandwidth frequency of an analog filter
US7403584B2 (en) * 2003-12-31 2008-07-22 Intel Corporation Programmable phase interpolator adjustment for ideal data eye sampling
US7660327B2 (en) * 2004-02-03 2010-02-09 Atheros Communications, Inc. Temporary priority promotion for network communications in which access to a shared medium depends on a priority level
US7193228B2 (en) * 2004-03-10 2007-03-20 Cymer, Inc. EUV light source optical elements
US7715425B2 (en) * 2004-02-26 2010-05-11 Atheros Communications, Inc. Channel adaptation synchronized to periodically varying channel
US7697641B2 (en) * 2004-06-28 2010-04-13 L-3 Communications Parallel DSP demodulation for wideband software-defined radios
US7272375B2 (en) * 2004-06-30 2007-09-18 Silicon Laboratories Inc. Integrated low-IF terrestrial audio broadcast receiver and associated method
US7486747B1 (en) * 2004-07-09 2009-02-03 L-3 Communications Corporation Digital timing recovery operable at very low or less than zero dB Eb/No
GB0418133D0 (en) 2004-08-13 2004-09-15 Ttp Communications Ltd Sample acquisition timing adjustment
WO2006018231A1 (en) * 2004-08-16 2006-02-23 Giesecke & Devrient Gmbh Controlled wireless charging of an accumulator in a chipcard
US7636370B2 (en) * 2005-03-03 2009-12-22 Intellon Corporation Reserving time periods for communication on power line networks
US20060274874A1 (en) * 2005-06-01 2006-12-07 Arvind Kumar Clock and data timing compensation for receiver
US7822059B2 (en) 2005-07-27 2010-10-26 Atheros Communications, Inc. Managing contention-free time allocations in a network
US8175190B2 (en) * 2005-07-27 2012-05-08 Qualcomm Atheros, Inc. Managing spectra of modulated signals in a communication network
US7623989B2 (en) * 2005-09-29 2009-11-24 Agilent Technologies, Inc. System and method for pulsed signal device characterization utilizing an adaptive matched filterbank
US7227478B1 (en) * 2005-12-14 2007-06-05 Sigmatel, Inc. Sample rate converter with selectable sampling rate and timing reference
US7411531B2 (en) * 2006-06-30 2008-08-12 Agere Systems Inc. Methods and apparatus for asynchronous sampling of a received signal at a downsampled rate
US7720185B2 (en) * 2006-11-06 2010-05-18 Qualcomm Incorporated Narrow-band interference canceller
JP4260187B2 (en) * 2007-01-25 2009-04-30 富士通株式会社 Frequency synchronization method and apparatus
US8036332B2 (en) * 2007-03-30 2011-10-11 4472314 Canada Inc. Communication signal symbol timing error detection and recovery
ATE545241T1 (en) 2007-05-10 2012-02-15 Qualcomm Atheros Inc MANAGING DISTRIBUTED ACCESS TO A SHARED MEDIUM
KR101159887B1 (en) * 2008-12-22 2012-06-26 창원대학교 산학협력단 Band-pass sampling receiver and method for receiving of the same
EP2239860B1 (en) * 2009-04-07 2012-08-15 The Swatch Group Research and Development Ltd. High-sensitivity, low-rate fsk modulation signal receiver
US8743977B2 (en) * 2009-06-23 2014-06-03 Intel Corporation Efficient tuning and demodulation techniques
US7969337B2 (en) * 2009-07-27 2011-06-28 Lsi Corporation Systems and methods for two tier sampling correction in a data processing circuit
US8295421B1 (en) 2009-11-10 2012-10-23 Altera Corporation Data communications circuitry with high jitter tolerance
US9032449B2 (en) 2009-11-13 2015-05-12 Thomson Licensing Algorithm for improving transponder scanning in a satellite set-top box
KR101491571B1 (en) 2010-04-12 2015-02-09 퀄컴 인코포레이티드 Channel estimation for low-overhead communication in a network
US8582675B1 (en) * 2010-06-01 2013-11-12 Fredric J. Harris Pre-channelized spectrum analyzer
US8553748B2 (en) * 2011-09-16 2013-10-08 Renesas Mobile Corporation ADC clock selection based on determined maximum conversion rate
US8891605B2 (en) 2013-03-13 2014-11-18 Qualcomm Incorporated Variable line cycle adaptation for powerline communications
US9240815B1 (en) * 2014-03-25 2016-01-19 Rockwell Collins, Inc. Reconfigurable filter
WO2018013756A1 (en) 2016-07-15 2018-01-18 Safe-Com Wireless A method, apparatus and system to amplify and transport analog signals
US10277231B1 (en) 2018-05-17 2019-04-30 Emhiser Research Limited DC coupled phase locked loop FM discriminator
US10516426B1 (en) * 2018-09-26 2019-12-24 Rockwell Collins, Inc. Systems and methods for wideband image-rejecting receivers
US11290903B2 (en) * 2019-07-17 2022-03-29 SiTune Corporation Spectrum monitoring
US10797788B1 (en) * 2019-12-02 2020-10-06 Amazon Technologies, Inc. Reducing power consumption in a receiver of a communications device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0092400A2 (en) * 1982-04-20 1983-10-26 Trw Inc. Digital synchronization technique
EP0174125A2 (en) * 1984-08-21 1986-03-12 The University Of Toronto Innovations Foundation Digital data receiver
EP0498022A2 (en) * 1991-01-28 1992-08-12 Industrial Technology Research Institute Timing recovery method and system for a receiver with A/D conversion

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3978407A (en) * 1975-07-23 1976-08-31 Codex Corporation Fast start-up adaptive equalizer communication system using two data transmission rates
US4004226A (en) * 1975-07-23 1977-01-18 Codex Corporation QAM receiver having automatic adaptive equalizer
FR2445079A1 (en) * 1978-12-20 1980-07-18 Ibm France METHOD AND DEVICE FOR DETECTING A PSEUDO-RANDOM SEQUENCE OF PHASE CHANGES OF 0O AND 180O OF THE CARRIER IN A DATA RECEIVER
FR2445078A1 (en) * 1978-12-20 1980-07-18 Ibm France METHOD AND DEVICE FOR DETECTING A PSEUDO-RANDOM SEQUENCE OF TWO SYMBOLS IN A DATA RECEIVER USING QUADRATURE DOUBLE SIDE-CARRIER MODULATION
FR2478914B1 (en) * 1980-03-19 1986-01-31 Ibm France METHOD AND DEVICE FOR INITIAL ADJUSTMENT OF THE CLOCK OF A SYNCHRONOUS DATA RECEIVER
ATE37972T1 (en) * 1983-07-14 1988-10-15 Ant Nachrichtentech METHOD OF MATCHING TWO SYSTEMS WITH DIFFERENT SAMPLING RATE.
US4599732A (en) * 1984-04-17 1986-07-08 Harris Corporation Technique for acquiring timing and frequency synchronization for modem utilizing known (non-data) symbols as part of their normal transmitted data format
US4733403A (en) * 1986-05-12 1988-03-22 Motorola, Inc. Digital zero IF selectivity section
US4882733A (en) * 1987-03-13 1989-11-21 Ford Aerospace Corporation Method and apparatus for combining encoding and modulation
US4815103A (en) * 1987-10-29 1989-03-21 American Telephone And Telegraph Company Equalizer-based timing recovery
US4878029A (en) * 1988-12-05 1989-10-31 General Electric Company Complex digital sampling converter for demodulator
US5214656A (en) * 1990-12-13 1993-05-25 At&T Bell Laboratories Multiplexed coded modulation with unequal error protection
JP2884792B2 (en) * 1991-02-19 1999-04-19 日本電気株式会社 Timing extraction device
US5309482A (en) * 1992-03-30 1994-05-03 Novatel Communications Ltd. Receiver having an adjustable matched filter
US5276706A (en) * 1992-05-20 1994-01-04 Hughes Aircraft Company System and method for minimizing frequency offsets between digital communication stations
US5274372A (en) * 1992-10-23 1993-12-28 Tektronix, Inc. Sampling rate conversion using polyphase filters with interpolation
GB9301704D0 (en) * 1993-01-28 1993-03-17 Signal Processors Ltd New digital modem design techniques
US5432813A (en) * 1993-12-28 1995-07-11 Unisys Corporation Parallel processing based digital matched filter and error detector for a digital demodulator
US5425057A (en) * 1994-04-25 1995-06-13 Paff; Thomas M. Phase demodulation method and apparatus using asynchronous sampling pulses

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0092400A2 (en) * 1982-04-20 1983-10-26 Trw Inc. Digital synchronization technique
EP0174125A2 (en) * 1984-08-21 1986-03-12 The University Of Toronto Innovations Foundation Digital data receiver
EP0498022A2 (en) * 1991-01-28 1992-08-12 Industrial Technology Research Institute Timing recovery method and system for a receiver with A/D conversion

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
GARDNER: "Interpolation in digital modems - part I: fundamentals", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 41, no. 3, March 1993 (1993-03-01), NEW YORK US, pages 501 - 507, XP000372693, DOI: doi:10.1109/26.221081 *
HARRIS: "Design Considerations and design tricks for digital receivers", 9TH KOBE INTERNATIONAL SYMPOSIUM ON ELECTRONICS AND INFORMATION SCIENCES, 18 June 1991 (1991-06-18), KOBE, JP, pages 1 - 9 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5812608A (en) * 1995-05-05 1998-09-22 Nokia Technology Gmbh Method and circuit arrangement for processing received signal
DE102004008227A1 (en) * 2004-02-19 2005-09-15 Infineon Technologies Ag Adjustment method for maximum power in a fractional delay in a digitally modulated, analog receiving signal (RS) in a communications receiving device uses RS to generate an over-scanned bit stream
DE102004008227B4 (en) * 2004-02-19 2006-04-13 Infineon Technologies Ag Polyphase selection in decimation devices of mobile radio receivers to correct a fractional delay

Also Published As

Publication number Publication date
IL109736A (en) 1997-07-13
EP0627830B1 (en) 1996-04-24
ES2088697T3 (en) 1996-08-16
DK0627830T3 (en) 1996-08-26
MY110750A (en) 1999-02-27
JPH09501279A (en) 1997-02-04
AU692448B2 (en) 1998-06-11
AU6916994A (en) 1994-12-20
BR9406664A (en) 1996-02-06
EP0627830A1 (en) 1994-12-07
GR3020548T3 (en) 1996-10-31
ATE137372T1 (en) 1996-05-15
HK150796A (en) 1996-08-16
US5504785A (en) 1996-04-02
SI0627830T1 (en) 1997-10-31
DE69400162T2 (en) 1996-12-12
DE69400162D1 (en) 1996-05-30
CA2161626A1 (en) 1994-12-08
US5612975A (en) 1997-03-18
IL109736A0 (en) 1994-09-26
PH31698A (en) 1999-01-18

Similar Documents

Publication Publication Date Title
AU692448B2 (en) Digital receiver for variable data rate communications
KR100713109B1 (en) Instrumentation receiver for digitally modulated radio frequency signals
US6498819B1 (en) Integrated multi-mode bandpass sigma-delta receiver subsystem with interference mitigation and method of using same
US7496158B2 (en) Swept bandpass filter frequency modulated continuous wave (FMCW) receiver and related method
CA2169551C (en) Apparatus and method for maximizing frequency offset tracking performance in a digital receiver
KR0178750B1 (en) Full digital symbol timing recovery apparatus
US5541965A (en) Carrier frequency synchronization device using two different B/W filters
JPH06188776A (en) Transmission system and receiver for transmission system
FI98412C (en) Code-free GPS positioning method and equipment for code-free positioning
US5857003A (en) Digital radio having improved modulation and detection processes
EP1753134B1 (en) Enhanced data rate receiver with an ADC clock rate being a fractional multiple of the receiving symbol rate
US5970086A (en) Radio remote interface for modulating/demodulating data in a digital communication system
AU747696C (en) Direct frequency selection and down-conversion for digital receivers
US5748036A (en) Non-coherent digital FSK demodulator
IL143490A (en) Variable rate continuous mode satellite modem
CN110880964A (en) Bit synchronization tracking system based on data conversion tracking loop
EP0259867A2 (en) Demodulator for psk-modulated signals
KR101078441B1 (en) Method for resampling at transmission and reception of a digital signal with digital band translation
US6298103B1 (en) Flexible clock and data recovery module for a DWDM optical communication system with multiple clock rates
US7260168B2 (en) Network measurement method and apparatus
WO1996013897A1 (en) Communication device with reduced sensitivity to in-channel interference
KR100433639B1 (en) Apparatus and method for timing recovery in residual sideband modulation
KR20040046316A (en) Digital tv receiver
KR960000542B1 (en) Frame timing signal detecting method and system using synchronization signal
KR20040038248A (en) Timing recovery apparatus in digital TV receiver

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AT AU BB BG BR BY CA CH CZ DE DK ES FI GB HU JP KP KR KZ LK LU MG MN MW NL NO NZ PL PT RO RU SD SE SK UA VN

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BF BJ CF CG CI CM GA GN ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2161626

Country of ref document: CA

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642