WO1995032505A1 - Memory device - Google Patents

Memory device Download PDF

Info

Publication number
WO1995032505A1
WO1995032505A1 PCT/US1995/006139 US9506139W WO9532505A1 WO 1995032505 A1 WO1995032505 A1 WO 1995032505A1 US 9506139 W US9506139 W US 9506139W WO 9532505 A1 WO9532505 A1 WO 9532505A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
portals
memory device
memory
outputs
Prior art date
Application number
PCT/US1995/006139
Other languages
French (fr)
Inventor
Robert B. Mclaughlin
Lawrence C. Plumhoff
M. James Bullen
Original Assignee
Image Telecommunications Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Image Telecommunications Corporation filed Critical Image Telecommunications Corporation
Priority to EP95920463A priority Critical patent/EP0763243B1/en
Priority to DE69505661T priority patent/DE69505661T2/en
Priority to AU26070/95A priority patent/AU711519B2/en
Publication of WO1995032505A1 publication Critical patent/WO1995032505A1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/188—Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/231—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/10—Adaptations for transmission by electrical cable
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/16—Analogue secrecy systems; Analogue subscription systems
    • H04N7/173—Analogue secrecy systems; Analogue subscription systems with two-way working, e.g. subscriber sending a programme selection signal
    • H04N7/17309—Transmission or handling of upstream communications
    • H04N7/17336—Handling of requests in head-ends

Definitions

  • the present invention relates generally to memory devices and methods
  • the invention concerns storage
  • information e.g., information in digital or analog form.
  • the types of information capable of being stored can include video and audio
  • information e.g., movies, video games, television and other entertainment
  • audio information such as speech or musical
  • compositions for compositions, visual information, such as paintings and photographs, and audio ⁇
  • the still pictures are moved past a light source in sequence and at a
  • music stored on magnetic tape can be
  • data may be stored in a memory and accessed in serial fashion to obtain the same
  • They include shift registers, charge coupled devices (CCDs), delay
  • ROM read-only memory
  • RAM random-access memory
  • Fig. 1 A shows
  • the shift register 10 is
  • clock pulses input at clock input 12 cause the data at the inputs D to transfer to
  • the shift register illustrated in Fig. IB is another example of a register
  • the shift register comprises an input 20 for data, an input selector 21, a
  • data storage selector 22 composed of logic gates, a shift register 23, a device
  • the data to be stored is fed to the input 20, thereby inputting the data to be stored.
  • the write control 28 is changed to low, the data storage
  • selector 22 recirculates the stored data through the shift register 23, thereby
  • the output operation does not damage the recirculating data, the output operation can
  • the storage capacity for this type of shift register is 512 or 1024 binary
  • bits o digits (bits).
  • Prior art delay lines such as the one shown in Fig. 1C, are composed of
  • Figs. ID and IE show a CCD, where Fig. ID is a schematic circuit
  • Fig. IE is a structural diagram. As shown in Fig. ID, the CCD
  • MOSFET metal oxide semiconductor field effect transistor
  • Amplifiers 41, 42 also composed of MOSFETs, are also connected in series.
  • Amplifiers 41, 42 also composed of MOSFETs, are also composed of MOSFETs, are also composed of MOSFETs, are also composed of MOSFETs, are
  • the CCD input and the CCD output are provided on the CCD input and the CCD output, respectively.
  • MOSFET in accordance with clock pulses supplied at clock inputs 43 and 44.
  • the individual MOSFETs are formed by
  • FIG. IF A typical RAM is illustrated in Fig. IF. As shown in the drawing, an
  • array of memory cells 50 is connected to respective series of row selectors 51,
  • a particular cell to be written to is selected by providing the cell's
  • Fig. 1G illustrates a typical ROM. The structure is very similar to that
  • the memory devices according to the present invention borrow from the
  • the location of the data can be computed, e.g., by knowing the present
  • plural output ports permit independent, simultaneous access to the stored data.
  • these plural output ports can be configured to allow data cloning.
  • the present invention provides for extremely efficient and powerful methods of
  • the present invention provides a
  • the memory devices of the present invention can be designed in several aspects
  • the memory device circulates data either through or past fixed portals.
  • the data is stored in fixed address locations and the portals
  • Figs. 1A-1G show various data storage techniques known in the prior art
  • Fig. 2 illustrates a memory device according to the present invention
  • Fig. 3 shows a first alternative structure, in which fixed data are accessed by moving portals
  • Figs. 4A-4D show one embodiment of the arrangement of Fig. 3;
  • Figs. 5A-5D show one embodiment of the arrangement of Fig. 2;
  • Fig. 6 shows a second alternative structure, in which moving data are
  • Figs. 7A-7D show one embodiment of the arrangement of Fig. 6;
  • Figs. 8A-8E show embodiments of the present invention constructed using
  • Fig. 9 shows an embodiment of the present invention constructed using
  • Fig. 10 shows an embodiment of the present invention constructed using
  • Fig. 11 shows an embodiment of the present invention constructed using
  • Fig. 12 shows an embodiment of the present invention constructed of a
  • Fig. 13 shows an embodiment of the present invention in which a memory
  • Fig. 14 illustrates a data output scenario, where stored data is supplied to
  • Fig. 2 shows a memory device that is capable of storing data information
  • the device is constructed of a plurality of data
  • storage devices 2 together forming a storage unit 1 , and a plurality of portals
  • the portals 3 are dispersed around the storage unit 1 in a manner that can be
  • the memory device is configured to
  • the storage devices 2 are arranged in the storage unit 1 in
  • This structure can take the form
  • FIG. 2 shows six storage devices 2 connected into the ring structure.
  • the portals 3 are connected to the storage unit 1 at various locations.
  • the portals 3 are connected into the ring and alternate with storage
  • portals 3 are a ⁇ anged in a systematic and predictable manner, and that they are
  • portals 3 is defined by modular
  • Modular arithmetic as defined by Merriam- Webster Inc., is the
  • o'clock is 15 o'clock, but is also 3 o'clock, because clocks follow a modular
  • portals 3 are defined as follows:
  • M the total number of data portals 3 provided in the storage
  • the seventh data portal 3 is equivalent to the first data portal
  • Arranging the portals according to modular arithmetic renders access to
  • the portals 3 shown in Fig. 2 are each constructed as data replicators
  • each portal performs both a replicating and an outputting
  • the memory device can be constructed with non-replicating portals
  • portals 3 that can be used as portals 3 include latches, logic gates, regenerators and
  • the memory device includes a
  • n-phase clocks include n-phase clocks, timing generators, address generators, data multiplexers,
  • Fig. 2 shows a controller 6 connected to the storage unit 1.
  • controller 6 is connected via signal control lines to respective
  • the controller 6 is configured to control data traffic at the portals 3,
  • Data traffic includes either the input of data into the storage
  • the controller 6 establishes and regulates connections between
  • the signal lines 7 can also be used for inputting data into the
  • the memory device is utilized for inputting data, for storing
  • data to be stored is presented to some portal 3 in an input operation.
  • the ring e.g. portal number 1.
  • the data may be input in a time-division multiplexed or
  • predetermined relative times for example, simultaneously.
  • the controller 6 can, but need not, be used during the input operation.
  • the controller 6 selects one of the signal lines 7 and
  • one of the portals 3 controls the input of data from the selected line 7 to the
  • the ring stores it in a cyclical arrangement.
  • cyclical arrangement is one in which, even though, en route, the data may be
  • the point in the memory structure may be stationary, while the data is kept in motion.
  • the data can
  • Fig. 2 shows a cyclical arrangement of stored data in which the data
  • portals 3 are connected into the ring, as shown in Fig. 2, they pass the data from
  • portals can be appended onto the ring, such
  • the fidelity of the stored data is maintained while the data circulates in
  • the movie title data circulates continuously through the ring, head
  • the data repeatedly passes by in the fashion in which it was loaded.
  • the rate of circulation is determined by the frequency of the clock used by the memory device, as described above.
  • the clock can also be used to alter the rate of circulation
  • intermittent data progression include video games and electronic catalogs.
  • Movies, television programs, music and the like are preferably stored using
  • one of the portals 3 is selected by the controller 6 as commanded by the
  • control signal 8 Also, one of the signal lines 7 is selected as an output line.
  • the output operation then preferably proceeds by reproducing the stored data at
  • the output rate simply matches the
  • the controller 6 may sever the connection between
  • non-selected portals simply pass the data within the ring, without reproducing it, on to the next storage device 2, as described above.
  • a portal is selected which lies an appropriate
  • s be accessed based, e.g., on the portal that was used to load the data, the time
  • the intervals between portals are constant, i.e.,
  • the ability to compute a desired portal relative to data is a feature of the
  • a single computation provides access to an entire stream of stored
  • LANs local area networks
  • Token Ring
  • Ethernet wide area networks
  • WANs wide area networks
  • MANs metropolitan area networks
  • a first data portal 3 (e.g., data portal number 6) is selected for
  • the controller 6 controls the output such that the data is replicated and routed out from the storage unit 1, via
  • output line 7 thus carries the data, e.g., movie title, television program, etc., out
  • controller 6 then replicates and routes the data as a second data stream from the
  • portal number 1 Given the large number of portals and
  • time delay defining intervals between consecutive portals might be chosen to be,
  • intervals between portals would be determined primarily by balancing grade of
  • the data streams being output may be staggered, i.e., partially
  • the signal lines 7 may be controlled in such a way that one
  • memory device can be output as a large number of independent output data
  • the present invention provides an extremely powerful method of
  • the present invention provides an extremely efficient method of data
  • data preferably representing video and/or audio information
  • 3 and 4A-4D inclusive illustrate the moving output ports (address) design
  • Figures 2 and 5A-5D illustrate the moving data alternative.
  • Fig. 3 shows an alternative where the data forming a title 100 is held
  • Each block is a sequential
  • each block of data is associated with one portal 101.
  • Fig. 3 also shows a control device 102, which is used to select data blocks
  • control device 102 activates the portal 101
  • the data in block 1 travels via signal line 103 to
  • control device 102 which transfers data block 1 to an output line 104.
  • control device 102 When data block 1 has been successfully output, the control device 102 will
  • control device will activate one
  • the data stored in the data memory is held fixed, while the
  • Figs. 4A-4D show an implementation of the fixed
  • Figure 4A depicts a group of "N" memories
  • Each memory has a capacity of eight cells (a cell being any arbitrary
  • port 1 is again free to be reset to the initial memory cell location and to
  • control device operates according to a
  • This programmed sequence can be determined by an external control
  • the external control signal 105 may still be used, e.g., for selecting
  • the data memory used in this alternative can be any of a number of
  • memory storage devices including dynamic RAM, static RAM, and pseudo static
  • RAM random access memory
  • data block as shown in the figure, can represent a complete RAM, a sector in
  • the portals 101 can be constructed from logic gates, gate a ⁇ ays, programmable logic a ⁇ ays, etc.
  • the control device 102 can be
  • microprocessors and sequencers.
  • Fig. 2 showed one memory
  • Figure 5A shows the configuration of title data 115 relative to output port 1 (see
  • Figure 5C shows the data position once eight read operations have
  • Figure 5D shows the relative position of the data to the output port
  • Fig. 6 shows an alternative where the data forming titles 120 and 130 are
  • each storage sub-unit were constructed of a recirculating shift register, as
  • portal 121 or 131 associated with each block of data stored in the respective data
  • control device 122 During an output operation of the title 120, the control device 122
  • control device 122 will cause the next portal 121 in the programmed
  • control device will activate one
  • the data blocks also changes with time.
  • FIGS. 7A-7D show one possible implementation
  • output port 1 (see
  • data stack D1-D8 circulates within memory 1, data
  • stack D9-D16 circulates within memory 2, and so forth.
  • the data memory in this third alternative can be constructed, e.g., of
  • control device can be implemented through microprocessors, data sequencers, logic gates, gate a ⁇ ays, etc.
  • preferable memory device hardware options are various types of semiconductor
  • Fig. 8A shows a long series of clocked shift registers 151
  • the ring 150 is constructed such that an entire
  • title is capable of being stored on the ring. Typically, to store a two-hour
  • the ring should be able to
  • the ring 150 is clocked by a clock source 152
  • the ring 150 which governs the rate of circulation of the data around the ring.
  • FIG. 8B illustrates
  • FIG. 8C illustrates
  • shift registers 151 are interconnected in series and in
  • the data forming the title passes through the shift registers 151 serially
  • the access to the title stored in the ring 150 is obtained via the data ports
  • the ports 153 are preferably composed of logic
  • each port 153 has an input for receiving a bit stream input 154.
  • Data for a new title is inserted into the ring 150 via inputs 154.
  • Data for a new title is inserted into the ring 150 via inputs 154.
  • each port 153 also has an output connected to the following register 151, each port 153 also has an
  • the spacing of the ports 154 defines the time intervals between permissible data access, and thus
  • regenerators 156 can be
  • regenerator 156 is formed as a data checker
  • Each data checker 156' preferably
  • logic circuitry 163-165 contains logic circuitry 163-165 as well as a decoder 166 and an encoder 167.
  • the decoder 166 receives the data stream at an input, outputs any
  • circuitry 163-165 The output 168 leads to operational surveillance units.
  • the data stream is input into the encoder 1167 and is output as an
  • data may be compressed. Particularly with respect to video
  • Such schemes include MPEG, fractal and variable data rate coding.
  • MPEG uses a discrete cosine transform and is a lossy compression scheme.
  • compression techniques include W.B Pennebaker et al., JPEG (Reinhold, New
  • each ring is structured to allow data to be placed into the ring
  • each ring is able to detect and repair e ⁇ ors
  • the shift registers 151 can be any suitable shift registers 151 .
  • shift registers includes Emitter Coupled Logic (ECL), Transistor Transistor
  • TTL Transmission Line
  • MOS Metal Oxide Semiconductor
  • a memory device may be any memory device according to the first prefe ⁇ ed embodiment.
  • the MOS-type shift register For purpose of storing and accessing movies and the like, the MOS-type shift register
  • a further, prefe ⁇ ed alte ⁇ iative for embodying the memory device is to
  • CCDs 171 Charge-Coupled Devices
  • a ring memory device 170 to form a ring memory device 170. If the ring 170 is constructed using
  • each CCD 171 must be pumped by a clock source 172. Further, some form of regenerating means 176 must be coupled between each
  • Possibilities for the regenerating means 176 include logic gates, as
  • the ring memory device 170 functions similarly to the ring memory
  • Access gates 182 connect the
  • the access gates 182 provide
  • delay lines 181 themselves are preferably provided with egress ports 186 in
  • Fig. 11 shows yet anotiier embodiment of the invention, which utilizes one
  • RAM random access memories
  • a RAM 190 has a series of address lines AQ - A N , a data line
  • the RAM 190 is connected to a data sequencer
  • control device 192 activates the RAM 190 by triggering the line R/W and the
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • PSRAM Pseudo Static Random Access Memory
  • SRAM static random access memory
  • DRAMs require periodic refresh of the data. The periodic
  • PSRAM technology represents a combination of the benefits
  • PSRAM devices have the memory capacity
  • Fig. 12 shows an embodiment of the invention which is constructed
  • a memory storage medium 200 capable of confining cyclically
  • the data representing one or more tides, or a portion thereof is embodied in the form of a propagating wave, where the wave defines
  • the storage medium forms a ring
  • the propagating wave can, in theory,
  • waves including light, microwaves and radio waves, but, preferably light or
  • microwaves are employed. As known, such waves can be used to store
  • a wave 201 representing data is trapped in a ring
  • the storage medium may be provided with repeaters or other
  • amplifying means (not shown) which compensate for any propagation losses.
  • the list of cu ⁇ entiy available media for providing such a ring cavity 202 include
  • the ring cavity 202 is associated with a plurality of data portals 203
  • portals 203 is one defined by modular arithmetic. The embodiment illustrated
  • Individual portals can be configured either for inputting
  • portals can be constructed of amplifiers, regenerators, beam
  • a controller (not shown) is used to select one or more of the
  • portals 203 When selected for data output, a given portal 203 passes the data
  • the controller may,
  • Fig. 13 shows a memory device with further details regarding portal selection. This embodiment is again an example of a memory device 300
  • Data can be placed into the device 300 or
  • controller 310 provides the selection and switching operability required to output
  • logic circuitry including AND gates 321-328 and OR
  • Each AND gate 321-328 has a first input originating at the
  • each AND gate 321-328 has one output
  • each OR gate 331-332 has a line that forms an input into one of the OR gates 331-332. As shown, each OR
  • gate 331-332 receives inputs from a number of AND gates 321-328.
  • controller output points 351-352, as shown.
  • a signal from a given selector e.g., 341
  • the selection signal 341 is chosen to synchronize with the circulating data
  • the portal is
  • the data stream flows out from the portal 301 and through the appropriate
  • AND gate 325 that is connected to the same portal 301 as the one activated in
  • the first output operation is triggered by a further selection signal 345 to forward
  • a second AND gate e.g.,
  • the portal 303 is determined by the momentary location of the starting point of
  • the data stream stored in the memory 300 can be output to multiple destinations
  • Overlaps as just described, can either be
  • FIG. 14 illustrates one output scenario. As shown,
  • the request from subscriber D is
  • controller 310 selects a different portal in the ring to respond to the request from
  • tides e.g., movies, educational-, entertainment-, consumer-, and

Abstract

A method and an apparatus for storing data provide data memory in a systematic, cyclical arrangement, provide plural data portals in an arrangement defined by modular arithmetic, and provide sequential, relative movement between the data memory and the data portals. When one or more of the plural portals is selected, data can be input or output in a manner which is predictable, straight-forward, free of scheduling constraints, and very efficient, without contention between the separate portals. Also disclosed are a method and apparatus which provide data memory in a systematic, cyclical arrangement, provide a systematic arrangement of plural data outputs, and provide sequential, relative movement between the data memory and the data outputs. The memory devices of the present invention can be designed so that the memory device circulates data either through or past fixed portals. Alternatively, the data can be stored in fixed locations and the portals moved from location to location. Preferred embodiments of the invention utilize semiconductor memory technology in order to implement the memory devices. Another set of embodiments utilizes memory storage media capable of confining propagating waves in order to implement the memory devices.

Description

MEMORY DEVICE
Related Application Information
This application is a continuation-in-part of co-pending Application Serial
No. 08/136,185, filed October 15, 1993, the disclosure of which is incorporated
herein by reference. This co-pending application relates to an Information
s Service Control Point for controlling data transmissions from a central station
that may be equipped with Memory Devices such as the ones described in the
instant application. The Information Service Control Point disclosed in the co-
pending application is one advantageous alternative for utilizing Memory Devices
according to the present invention as a storage means. However, the Memory
o Devices according to the present invention can be utilized equally well with other
information services and for other data storage needs.
BACKGROUND OF THE INVENTION
s Field of the Invention
The present invention relates generally to memory devices and methods
of storing and accessing data. More particularly, the invention concerns storage
of data streams in a manner that establishes a systematic relationship between the
data itself and points used for accessing the data, to provide independent and extremely efficient access to, and dissemination of, the stored data streams.
Description of Relevant Background
Consumer demand for enhanced on-site entertainment and information
services is on the rise. Examples of such entertainment and information services
include so-called "on-demand" video, interactive videogames, database research,
"home-shopping" and the like. Numerous service providers are currently eager
to tap this demand, and are therefore expressing interest in schemes for
providing such services to consumers.
In order to be economically practical and viable, a system offering the
wide range of information-related services just described should preferably be
able to (i) store very large quantities of data at an affordable cost per bit; and
(ii) provide for efficient retrieval of the data with a minimal contention between
users for any portion of the data.
Memory devices according to the present invention are advantageously
utilized for storing information (e.g., information in digital or analog form).
The types of information capable of being stored can include video and audio
information (e.g., movies, video games, television and other entertainment
programs), educational information and programs, scientific and other research-
related database information, consumer catalog and home-shopping information, and the like, and are hereinafter referenced generically as "information" or
"titles".
Many such types of information, in order to be useful, require that the
data, which together form the information, are provided in a given sequence or
order. Examples include audio information, such as speech or musical
compositions, visual information, such as paintings and photographs, and audio¬
visual information, such as movies, television shows and video games. In the
case of a movie, for example, a sequential group of still pictures is connected
together on a long strip of photographic film. In order to "play back" the
movie, the still pictures are moved past a light source in sequence and at a
certain speed, and the resulting images are focused onto a screen while the audio
portion of the movie is output over speakers. These resulting images will appear
to the viewer to be moving. Similarly, music stored on magnetic tape can be
"played back" by moving the magnetic tape serially past a playback head of a
tape player.
In analogous fashion, according to more recent techniques, digitally stored
data may be stored in a memory and accessed in serial fashion to obtain the same
result achieved by the more traditional storage formats mentioned above. As
such, an assemblage of stored digital data, if "played back" in serial fashion, can
reproduce any of the above types of information. A few of the many types of mechanisms used to store digital data are introduced here just by way of
example. They include shift registers, charge coupled devices (CCDs), delay
lines, read-only memory (ROM) and random-access memory (RAM).
The shift register as a technology has existed for decades. Fig. 1 A shows
a typical shift register arrangement. As illustrated, the shift register 10 is
composed of a series of D-flip-flops 11. The number of flip-flops provided is
variable and depends upon the number of bits N to be stored. In operation,
clock pulses input at clock input 12 cause the data at the inputs D to transfer to
the outputs Q. This clocking causes data supplied bit by bit at the data input 13
to shift right by one flip-flop. After an appropriate number of clock cycles, the
data is output bit by bit at the data output 14.
The shift register illustrated in Fig. IB is another example of a register,
namely a recirculating shift register manufactured by Signetics in 1972. As
shown, the shift register comprises an input 20 for data, an input selector 21, a
data storage selector 22 composed of logic gates, a shift register 23, a device
selector 24, an output selector 25, clock inputs 26, 27, a write control 28, a read
control 29, and a data output 30. In operation, the shift register is activated by
inputting high signals at the device selector 24. Then, a write enable signal is
input to the write control 28, while clock input 26 receives clock pulses. At the
same time, the data to be stored is fed to the input 20, thereby inputting the data to be stored. When the write control 28 is changed to low, the data storage
selector 22 recirculates the stored data through the shift register 23, thereby
storing the data. When it is desired to output the stored data, a read signal to
the read control 29 and clock pulses to the clock input 27 trigger the output
s selector 25 to output the data stored in the shift register at output 30. Since the
output operation does not damage the recirculating data, the output operation can
be performed repeatedly for the same stored data. To alter the data stored in the
register, it must be over-written with new data by a write operation, as described
above. The storage capacity for this type of shift register is 512 or 1024 binary
o digits (bits).
Prior art delay lines, such as the one shown in Fig. 1C, are composed of
a silicon substrate 31, a signal input 32, several signal taps 33 spaced equally
along the substrate 31, and a signal output 34. An electrical signal entering the
s delay line at the input 32 propagates through the substrate 31 at a fixed,
predetermined velocity. While propagating, the signal passes by each of the
several taps 33, which can be used to access the data. Thus, it becomes possible
to delay the propagating signal a predetermined amount of time by passing it
through the delay line and then selecting an appropriate tap that coπesponds to
o the amount of desired delay. Once the propagating signal reaches the end of the
substrate, it is output from the delay line at 34. Figs. ID and IE show a CCD, where Fig. ID is a schematic circuit
diagram and Fig. IE is a structural diagram. As shown in Fig. ID, the CCD
is composed of metal oxide semiconductor field effect transistors (MOSFETs)
40 connected in series. Amplifiers 41, 42, also composed of MOSFETs, are
provided on the CCD input and the CCD output, respectively. The CCD
operates similarly to the shift register (see Fig. IA) in that a signal enters the
CCD at the input 41 and progresses through the CCD from MOSFET to
MOSFET in accordance with clock pulses supplied at clock inputs 43 and 44.
After proceeding through the series of MOSFETs 40, the signal exits the CCD
at output 42. As shown in Fig. IE, the individual MOSFETs are formed by
placing metal contact layers 45 at appropriate locations on a semiconductor
substrate 46.
A typical RAM is illustrated in Fig. IF. As shown in the drawing, an
array of memory cells 50 is connected to respective series of row selectors 51,
column selectors 52, write amplifiers 53, and sense amplifiers 54. In a data load
operation, a particular cell to be written to is selected by providing the cell's
appropriate column and row address, using the selectors 51 and 52. The data
to be written to that cell is then input to the array 50 via the write amplifiers 53.
Given the prior selection operation, however, the data is stored only in the
selected cell. Similarly, in a data read operation, a particular cell to be read is
again selected by providing appropriate column and row addresses via the selectors 51 and 52. The data is then copied out from the array 50 via the sense
amplifiers 54.
Fig. 1G illustrates a typical ROM. The structure is very similar to that
≠
5 of the RAM just described. An array of pre-set memory cells 60 is connected
to respective series of row selectors 61, column selectors 62 and sense amplifiers
63. Operation of the ROM proceeds as described with respect to the data read
operation of the RAM illustrated in Fig. IF.
ιo The more traditional (i.e., analog) storage and playback formats suffer
from drawbacks both in limitations on dissemination and in scheduling
constraints. Thus, traditionally, in order to see a movie, for example, a viewer
would have to attend a scheduled showing at a predetermined location. With the
advent of broadcasting, the viewer was freed from the need to travel to the
is showing, but nonetheless was bound by the schedule imposed by the broadcaster.
In more recent times, videotape technology has effectively freed the consumer
even from the former restrictions on scheduling. However, this additional
measure of freedom has given rise to other inconveniences. For example, the
consumer must either travel to purchase or rent a particular tape, or program a
20 recorder in order to "time-shift" viewing of a particular scheduled broadcast.
Similarly, data stored digitally in a computer memory also suffers from limitations on access and dissemination. For instance, in an Input/Output
operation performed by a computer, the computer must repeatedly perform
complex, multi-step operations to access, move and output the desired data in
small increments. Also, output using known addressing techniques is a dedicated
operation, in that it is limited to one single destination at any given time. As a
result, only one end user at a time has access to the output data. Additionally,
digital storage of audio-visual information has not been widely practiced, at least
in part because the above limitations render it economically unfeasible.
SUMMARY OF THE INVENTION
The memory devices according to the present invention borrow from the
above philosophy of outputting data in a serial and sequential manner to convey
useful information, e.g., a motion picture. The data output from such a memory
device can be used to produce a moving picture or the like from, essentially,
sequential frames or their equivalent. Unlike the more traditional media,
however, the data is stored in a cyclical, systematic arrangement. In other
words, once the data is input into the memory device, the data and some
appropriate point of data access will repeatedly coincide. Furthermore,
according to the present invention, once the data is input into the memory
device, the location of the data can be computed, e.g., by knowing the present
or past location of at least some part of the data. Also, unlike the more traditional media, access to the data is not limited
to a single scheduled output. Rather, according to the invention, there can be
many output ports associated with one and the same set of stored data. These
plural output ports permit independent, simultaneous access to the stored data.
Also, these plural output ports can be configured to allow data cloning. Thus,
the present invention provides for extremely efficient and powerful methods of
data access and dissemination.
It is an object of the invention to provide a particularly useful manner of
storing data.
It is a further object of the invention to provide a data storage
arrangement and a data retrieval arrangement that permit very efficient access
to stored data, with minimal access contention.
It is yet another object of the present invention to provide a data storage
arrangement and a data retrieval arrangement that allow the stored data to be
disseminated widely and efficiently.
These and other objects are solved by the present invention in its various
embodiments. According to one formulation, the present invention provides a
method and an apparatus for storing data which: provide data memory in a systematic, cyclical arrangement;
provide plural data portals in an arrangement defined by modular
arithmetic; and
provide sequential, relative movement between the data memory and the
data portals.
As a result, when one or more of the plural portals is selected, data can be input
or output in a manner which is predictable, straight-forward, free of scheduling
constraints, and very efficient, without contention between the separate portals.
According to another formulation of the invention, a method and
apparatus are disclosed which:
provide data memory in a systematic, cyclical arrangement;
provide a systematic arrangement of plural data outputs; and
provide sequential, relative movement between the data memory and the
data outputs.
Again, when one or more of the plural outputs is selected, data stored in the data
memory can be tapped in a manner which is predictable, straight-forward, and
very efficient, without scheduling constraints and without contention between
outputs.
The memory devices of the present invention can be designed in several
different ways, as long as linkage between data and portals is assured. But it is not material how such linkage is achieved. For instance, according to one
design, the memory device circulates data either through or past fixed portals.
According to another, the data is stored in fixed address locations and the portals
are moved from address to address. These and other alternative designs will be
discussed in greater detail below in the Detailed Description.
Preferred embodiments of the invention utilize semiconductor memory
technology in order to implement the memory devices. Various such
semiconductor solutions are described below in the section entitled "Specific
Embodiments of the Invention". Another set of embodiments, also described
below, utilizes memory storage media capable of confining propagating waves
in order to implement the memory devices.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the invention are described, by way of
example, with reference to the accompanying drawings, in which:
Figs. 1A-1G show various data storage techniques known in the prior art;
Fig. 2 illustrates a memory device according to the present invention,
which, in this embodiment, is fashioned as a ring memory device;
Fig. 3 shows a first alternative structure, in which fixed data are accessed by moving portals;
Figs. 4A-4D show one embodiment of the arrangement of Fig. 3;
. Figs. 5A-5D show one embodiment of the arrangement of Fig. 2;
Fig. 6 shows a second alternative structure, in which moving data are
s accessed by moving portals;
Figs. 7A-7D show one embodiment of the arrangement of Fig. 6;
Figs. 8A-8E show embodiments of the present invention constructed using
shift register technology;
Fig. 9 shows an embodiment of the present invention constructed using
o CCD technology;
Fig. 10 shows an embodiment of the present invention constructed using
delay line technology;
Fig. 11 shows an embodiment of the present invention constructed using
RAM technology;
s Fig. 12 shows an embodiment of the present invention constructed of a
storage medium capable of confining waves that represent data;
Fig. 13 shows an embodiment of the present invention in which a memory
device is coupled to an output controller;
Fig. 14 illustrates a data output scenario, where stored data is supplied to
0 various subscribers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
I. PRINCIPLES OF THE INVENTION
A. Structure
Fig. 2 shows a memory device that is capable of storing data information,
i.e., titles of various sorts. The device is constructed of a plurality of data
storage devices 2, together forming a storage unit 1 , and a plurality of portals
3. The portals 3 are dispersed around the storage unit 1 in a manner that can be
described by means of modular arithmetic. As indicated by the directional
arrows superimposed on signal paths 4, the memory device is configured to
establish relative movement between data stored in the storage unit and the
portals 3.
Preferably, the storage devices 2 are arranged in the storage unit 1 in
series fashion to form a circulating structure. This structure can take the form
of an endless loop or ring, as shown in Fig. 2. The specific form chosen,
however, is not particularly important, as long as the structure is systematic and
provides a predictable arrangement of storage devices 2. Preferably, the
arrangement of storage devices 2 is defined in accordance with modular
arithmetic. Modular arithmetic will be explained below, in conjunction with the
detailed discussion of the portals 3. Fig. 2 shows six storage devices 2 connected into the ring structure. (As
will become more apparent below, the number of storage devices 2 in an actual,
commercial embodiment would be far greater than this. Only six are shown in
order to render description of the invention simpler and clearer.) As will be
discussed in descriptions of various implementations, below, the storage devices
2 can be selected from a wide variety of existing technologies. Currently, the
most preferable hardware options are various types of semiconductor memory,
e.g., shift registers, delay lines, CCDs, RAMs, ROMs and non-volatile
memories of various types. Advances in technology will surely expand the list
of available options.
The portals 3 are connected to the storage unit 1 at various locations. In
Fig. 2, the portals 3 are connected into the ring and alternate with storage
devices 2. However, as with the storage devices, the particular form of
connection is not important to the invention. Rather, it is important that the
portals 3 are aπanged in a systematic and predictable manner, and that they are
configured to allow data to enter or exit (or both enter and exit) the storage unit.
As noted above, the arrangement of portals 3 is defined by modular
arithmetic. Modular arithmetic, as defined by Merriam- Webster Inc., is the
"arithmetic that deals with whole numbers where the numbers are replaced by
their remainders after division by a fixed number. " By way of example, since the hours in a day are also defined by a modular arithmetic, 6 hours after 9
o'clock is 15 o'clock, but is also 3 o'clock, because clocks follow a modular
arithmetic with modulus 12. Stated in the form of an equation, the arrangement
of portals 3 is defined as follows:
Figure imgf000017_0001
where Pj = any chosen data portal in the arrangement, and
M = the total number of data portals 3 provided in the storage
unit 1. Fig. 2 shows a storage unit provided with M = 6 data portals 3.
(Again, a commercial embodiment would most likely contain many more than
lo six portals.) Thus, the seventh data portal 3 is equivalent to the first data portal
3.
The relationship between consecutive data portals can also be described
mathematically, as follows:
Figure imgf000017_0002
where Pj = any chosen data portal in the arrangement,
Pi+ j = the next data portal relative to Pj, and
f(t) = a function of time. It should be noted that, given the non-
continuous nature of hardware implementations, f(t) should not be construed as
0 being limited to a smoothly continuous function, but includes rational number
(e.g., integer) approximations of continuous functions. Preferably,
f(t) = C, where C = a constant. When f(t) is constant, the portals 3 are arranged
around the storage unit 1 at fixed, regular intervals, as illustrated in Fig. 2. The
benefits of having constant intervals between portals include the ability to
construct the ring and, in particular, the portals, of pre-fabricated, modular units
(other benefits are described later in the application). The intervals need not be
constant, however, to provide an operable and practical memory device 1. For
example, dispersing the portals 3 according to the function:
f(t) = log (t)
causes the intervals between portals to become progressively longer until the loop
returns to the initial portal. The function:
f(t) = sin (t)
causes portals to bunch at various locations around the ring. Any other function
of time can be utilized, to match specifications desired by the service provider,
and thereby more closely match the information needs of end users.
Arranging the portals according to modular arithmetic renders access to
data stored in the memory device calculable and reproducible. The benefits of
the systematic nature of the arrangement will become apparent below.
The portals 3 shown in Fig. 2 are each constructed as data replicators,
such that, if selected, each portal performs both a replicating and an outputting
function. This is indicated by the arrows shown on each of the signal paths 4 and 5 emanating from each portal 3. The arrows on signal paths 4 indicate data
that continues circulating in the ring. The arrows on output signal paths 5
indicate data which is output from the ring. This is the preferable arrangement.
Alternatively, the memory device can be constructed with non-replicating portals
3 and separate data replicators (not shown), which merely replicate the data
stored in the device 1 but do not output it from the ring. Examples of hardware
that can be used as portals 3 include latches, logic gates, regenerators and
amplifiers.
Although not specifically shown in Fig. 2, the memory device includes a
means which forces portals 3 and data stored in the storage unit 1 to move
relative to one another. Conceptually, it does not matter whether the data moves
and the portals remain static, or whether the portals move while the data remain
static (or, for that matter, whether both the portals and the data move relative to
some third point of reference). The arrangement shown in Fig. 2 is one in
which the data move and the portals 3 are fixed.
Generally, in digital arrangements, the means which establish the relative
movement would be embodied by some form of clocking mechanism. Types of
clocks easily adapted to a memory device according to the present invention
include n-phase clocks, timing generators, address generators, data multiplexers,
and microprocessors. Finally, Fig. 2 shows a controller 6 connected to the storage unit 1.
Specifically, the controller 6 is connected via signal control lines to respective
portals 3. The controller 6 is configured to control data traffic at the portals 3,
e.g., by selecting among data portals 3 in accordance with an externally supplied
s control signal 8. Data traffic includes either the input of data into the storage
unit 1 via the portals, or the output of data from the storage unit 1 via the
portals. As such, the controller 6 establishes and regulates connections between
the data portals 3 and signal lines 7. The signal lines 7 in Fig. 2 are indicated
by the arrows as being output lines that transport replicated data out from the
o unit 1. However, the signal lines 7 can also be used for inputting data into the
unit 1.
B. Operation
In operation, the memory device is utilized for inputting data, for storing
s data and for outputting data. These three aspects will now be described in turn.
In an input operation, data to be stored is presented to some portal 3 in
the ring, e.g. portal number 1. Once the portal number 1 is activated, the data
is fed into the storage unit via the portal number 1 preferably as a sequential data
o stream. Any data previously existing in the ring is thereby over-written. The
input operation is completed when all of the data desired to be stored has entered
the storage unit 1 via the portal. Thus, for example, if one wishes to store data corresponding to a movie title in the memory device, according to one
straightforward model, the data is input in serial fashion, starting with the
beginning of the movie and ending with the data corresponding to the closing
credits. If desired, the data may be input in a time-division multiplexed or
space-division multiplexed manner. This can be achieved, for example, by
selecting more than one portal, e.g., the portals numbered 1 and 4, at
predetermined relative times, for example, simultaneously.
The controller 6 can, but need not, be used during the input operation.
If the controller 6 is used, the controller 6 selects one of the signal lines 7 and
one of the portals 3, and controls the input of data from the selected line 7 to the
storage unit 1 via the selected portal 3. If the controller 6 is not used, an input
line is simply connected directly to one or more portals 3 during the input
operation.
Once the data is input, the ring stores it in a cyclical arrangement. A
cyclical arrangement is one in which, even though, en route, the data may be
processed (e.g., error-corrected, error-proofed, modulated, encoded, decoded,
encrypted, decrypted, etc.), branched, diverted, or otherwise acted upon,
eventually, the data (or an appropriate facsimile or coπelate thereof) and an
appropriate point (such as a portal) in the memory structure will again coincide.
Several variations are possible. For example, the point in the memory structure may be stationary, while the data is kept in motion. Conversely, the data can
be held fixed while the point in the memory structure is moved. Also, both the
data and the points can be moved, relative to some third position of reference.
Embodiments employing each of the above variations will be described in greater
detail later in the specification.
Fig. 2 shows a cyclical arrangement of stored data in which the data
moves relative to fixed portals 3. More specifically, the data circulates in a ring
structure, passing from one storage device 2 to the next, and so forth. If the
portals 3 are connected into the ring, as shown in Fig. 2, they pass the data from
one storage device 2 to the next during storage but otherwise remain passive.
Alternatively, the portals 3, equally well, can be appended onto the ring, such
that, during storage, the data stream passes directly from one storage device 2
to the next without passing through the portals 3.
The fidelity of the stored data is maintained while the data circulates in
the ring. As such, the data circulates in the same order in which it was input
into the ring. Thus, if the ring has been loaded with data corresponding to a
movie title, the movie title data circulates continuously through the ring, head
following tail. As viewed from a specific point on the ring (e.g., some given
portal 3), the data repeatedly passes by in the fashion in which it was loaded.
The rate of circulation is determined by the frequency of the clock used by the memory device, as described above. The clock can also be used to alter the
rate of circulation, if desired. For instance, it may be desirable to provide an
arrangement wherein the relative movement between the stored data and the data
portals is intermittent rather than continual. Applications conducive to
intermittent data progression include video games and electronic catalogs.
Movies, television programs, music and the like are preferably stored using
continual (i.e., uninterrupted) data movement.
When it is desired to output data that is stored in the memory device,
first, one of the portals 3 is selected by the controller 6 as commanded by the
control signal 8. Also, one of the signal lines 7 is selected as an output line.
The output operation then preferably proceeds by reproducing the stored data at
the selected portal and delivering the reproduced data to the selected output line
7, so that the data may be routed to an appropriate destination. No further
control is needed; once the appropriate portal is selected and the output operation
commences, the stored data stream simply "flows out", i.e., is reproduced and
delivered as it passes the selected portal. The output rate simply matches the
rate of circulation of the data within the ring (assuming the portals operate at real
time). When the complete data stream has been output from beginning to end,
in appropriate circumstances, the controller 6 may sever the connection between
the selected portal 3 and the selected output line 7. Of course, during the
described operation, non-selected portals simply pass the data within the ring, without reproducing it, on to the next storage device 2, as described above.
The decision of which portal to select is governed by the momentary,
current location of the stored data stream relative to the portals 3. For instance,
s if the stored data represents a movie title or television program, and it is desired
to output it from its beginning, a portal is selected which lies an appropriate
distance downstream of the cuπent location of the beginning of the title/program.
The momentary, cuπent location can be calculated, given the predictable
aπangement of the portals around the ring and the known rate of circulation of
o the data (or comparable parameters).
Specifically, given the described structure, it is possible to construct
appropriate functions to calculate the portal to be accessed. Such functions,
which would be apparent to those skilled in the art, can determine the portal to
s be accessed based, e.g., on the portal that was used to load the data, the time
elapsed from loading, and the speed of propagation of the data. If, as described
above and as shown in Fig. 2, the intervals between portals are constant, i.e.,
. f(t) = C, the calculation is especially simple.
0 Of course, variations more complicated than the ones just described,
which utilize more complex aπangements of portals and/or data storage, are
possible. Such functions, even though more complex, nonetheless operate according to the same principle, and are covered by the present invention.
The ability to compute a desired portal relative to data is a feature of the
invention which is not characteristic of outputs of standard electronic devices
(e.g., prior art shift registers, delay lines, CCDs, and so forth). As such, the
calculated portal number assumes a quality more commonly associated with an
Input/Output operation performed by a computer. However, unlike an I/O
operation, a single computation provides access to an entire stream of stored
data, not just one data unit. Further, the provision of plural data portals permits
overlapping output sequences not achievable by standard I/O operations. Finally,
this feature also distinguishes the present invention over known information
distribution systems, such as local area networks (LANs, e.g., Token Ring,
Ethernet), wide area networks (WANs), metropolitan area networks (MANs),
and cable television systems. In these systems, calculation of a portal has no
relationship with input/output operations. Rather, these systems require
cumbersome scheduling, addressing and routing schemes, to permit users to find
and access data in the system.
In a practical operation of the memory device, plural data portals would
normally be active in outputting data at any one time. Thus, in a typical
operation, a first data portal 3 (e.g., data portal number 6) is selected for
outputting the data at a first moment in time. The controller 6 controls the output such that the data is replicated and routed out from the storage unit 1, via
a first selected output line 7, to a desired first end-user destination. The selected
output line 7 thus carries the data, e.g., movie title, television program, etc., out
in its sequential order as a first data stream. Thereafter, if a second end-user
destination requests the same data, the controller 6 again calculates which portal
should be selected for outputting the data at the second moment in time. The
controller 6 then replicates and routes the data as a second data stream from the
second selected data portal (e.g., portal number 2), via a second output line 7,
to the second end-user destination.
If the above-described calculation again happens to yield data portal
number 6, preferably, the calculation would provide for selecting the next
available portal, here portal number 1. Given the large number of portals and
short time delays between portals in an actual embodiment, the end user would
not perceive the resulting delay. For instance, in a working embodiment, the
time delay defining intervals between consecutive portals might be chosen to be,
e.g., anywhere between 5 minutes, the best estimate of cuπent human patience,
and l/30th of a second, the cuπent refresh rate between television frames. The
intervals between portals would be determined primarily by balancing grade of
service with cost of the service.
Since the stored data is replicated at each selected portal, and the portals operate independently, there is no requirement that output of the second data
stream be delayed until the first data stream has been completely output. In
other words, the data streams being output may be staggered, i.e., partially
overlap. As a result, in the aπangement of Fig. 2, even though only one copy
of the title is stored in the unit 1, the title could be output to six different end-
user destinations at once if the portals were each activated one after another.
Furthermore, the signal lines 7 may be controlled in such a way that one
given data stream branches to multiple end users. As such, the number of
staggered "playbacks" of the stored title is further increased by providing
simultaneous playback to different end-user destinations of any or all of the
staggered "playbacks".
As apparent from the explanation above, since the data stored in the
memory device can be output as a large number of independent output data
streams, the present invention provides an extremely powerful method of
accessing data. Further, since the data streams (accessed as described and
further cloned if desired) can be routed to a practically unlimited number of
customers, the present invention provides an extremely efficient method of data
dissemination. C. Alternative Structures
• The design of the memory device described above implies that digital
information will be circulating in a loop and that portal locations are fixed at
given locations on the loop. According to the invention, however, it does not
matter whether the data moves and the portal location is static, or the portal
location moves and the data is static (or whether both move relative to a third
chosen location). All these alternative designs perform the required functionality
of a memory device.
As evident from the alternatives discussed below, the manner of storing
and accessing data (preferably representing video and/or audio information)
according to the present invention is amenable to a variety of designs. Figures
3 and 4A-4D inclusive illustrate the moving output ports (address) design,
Figures 2 and 5A-5D illustrate the moving data alternative. Figures 6 and 7A-
7D inclusive illustrate movement of both the ports and the data.
Cl. First Alternative: Fixed Data, Moving Portals
Fig. 3 shows an alternative where the data forming a title 100 is held
fixed in time in a data memory. As shown, the title 100 is subdivided into
numerous individual blocks 1 to n and stored. Each block is a sequential
segment of data. Preferably, each block of data is associated with one portal 101. Fig. 3 also shows a control device 102, which is used to select data blocks
by activating appropriate portals 101.
During an output operation, the control device 102 activates the portal 101
5 associated with data block 1. The data in block 1 travels via signal line 103 to
the control device 102, which transfers data block 1 to an output line 104.
When data block 1 has been successfully output, the control device 102 will
cause the next portal 101 in the sequence to be read. In this case, it is the portal
associated with block 2. In this manner, the control device will activate one
o portal after another, such that the output portal being activated changes with
time. As such, the data stored in the data memory is held fixed, while the
portals used for. accessing the title data move.
In more concrete terms, Figs. 4A-4D show an implementation of the fixed
s data, moving portals alternative. Figure 4A depicts a group of "N" memories
110. Each memory has a capacity of eight cells (a cell being any arbitrary
amount of data). The configuration of data relative to output port 1 (see
reference number 111), shown in figure 4A, coπesponds to a reading operation
of the data Dl held in the first cell of the first memory 1. Figure IB shows the
o results as the second piece of data D2 held in the second cell of memory 1 is
being read. This process continues until the data D8 in the eighth cell of
memory 1 is read, as shown in Fig. 4C. Before the next piece of data is read, the "pointer" in the column of cells is then reset to the position associated with
the first cell. Additionally the output port 1 is moved to the "next" memory 2.
This is shown in Fig. 4D. This process continues until the full data stream has
been accessed and output. Once the "last" piece of data is output, the output
port 1 is again free to be reset to the initial memory cell location and to
commence reading the data stream Dl-DN from the beginning. If the memory
structure is fully utilized, the "last" piece of data DN should be stored in cell
number 8 of memory N. However, the "last" piece of data may be held in some
previous location in memory, for instance, cell 3 of memory N-l.
Referring back to Fig. 3, the control device operates according to a
programmed sequence defining the sequence in which the portals 101 are
accessed. This programmed sequence can be determined by an external control
signal 105 or can be stored internally in the control device itself. If stored
internally, the external control signal 105 may still be used, e.g., for selecting
between several different stored sequence programs.
The data memory used in this alternative can be any of a number of
memory storage devices including dynamic RAM, static RAM, and pseudo static
RAM. Further, there is no limit on the size of a data block. For example, one
data block, as shown in the figure, can represent a complete RAM, a sector in
RAM or even just a bit. The portals 101 can be constructed from logic gates, gate aπays, programmable logic aπays, etc. The control device 102 can be
made from a number of devices including logic gates, gate aπays,
microprocessors, and sequencers.
C2. Second Alternative: Moving Data, Fixed Portals
In illustrating the principle of the invention, Fig. 2 showed one memory
aπangement in which moving data is accessed by fixed portals. Figs. 5A-5D
show one possible implementation of the moving data, fixed portals alternative.
Figure 5A shows the configuration of title data 115 relative to output port 1 (see
reference numeral 116) when the data Dl held in the first cell of the first
memory 1 is being output. After the first piece of data Dl is read, the data Dl-
DN is transfeπed, as shown in figure 5B, such that the next piece of data D2
can be read. Figure 5C shows the data position once eight read operations have
occuπed. Figure 5D shows the relative position of the data to the output port
1 while DN, the final piece of data in the data stream, is being read.
C3. Third Alternative: Moving Data, Moving Portals
Fig. 6 shows an alternative where the data forming titles 120 and 130 are
moving in time in respective data memories. The title 120, subdivided into
blocks 1 to n, moves in time much in the same manner as described with respect
to Fig. 2. In other words, the data blocks move from one storage sub-unit to the
next. The title 130, also subdivided into blocks 1 to n, moves in time within individual storage sub-units. Such an aπangement would exist, for example, if
each storage sub-unit, were constructed of a recirculating shift register, as
described with respect to Fig. IB. The aπangement of Fig. 6 is shown with one
portal 121 or 131 associated with each block of data stored in the respective data
memories.
During an output operation of the title 120, the control device 122
activates the portal 121 associated with data block 1 of that title. The data in
block 1 travels via signal line 123 to the control device 122, which transfers data
block 1 to an output line 124. When the data block 1 has been completely
output, the control device 122 will cause the next portal 121 in the programmed
output sequence to be read. In this manner, the control device will activate one
portal after another, such that the output portal being activated changes with
time. Since the data blocks forming title 120 are also moving, the location of
the data blocks also changes with time.
In more concrete terms, Figs. 7A-7D show one possible implementation
of the moving data, moving portals alternative. Here, output port 1 (see
reference numeral 141) is always associated with memory 1. Figure 7A shows
the configuration of title data 140 relative to output port 1 when the data Dl held
in the first cell of the first memory 1 is being output. After the first piece of
data Dl is read, the data Dl, D9, D17...DN are transfeπed as shown in Figure 7B. The "pointer" is moved to the next memory cell in the same memory 1, to
read data block D2. Figure 7C shows the data position after eight read
operations, coπesponding to D1-D8, have occuπed, and the "pointer" has
moved completely up the column of cells of memory 1. Figure 7D shows the
device during the next subsequent read operation. Here, the "pointer" is reset
to the bottom of the column of data cells of memory 1. Also, by this time, the
data forming title 120 has been completely shifted over by one memory. Thus,
e.g., the data formerly held in memory 2 is shifted into memory 1, and the data
formerly held in memory 1 is shifted into memory N. The "pointer" now begins
reading up the column of memory 1 once again, but now reads the next set of
data D9-D16. This process continues until the data Dl finally returns to
memory 1.
Returning to Fig. 6, an output operation of title 130 proceeds as described
with respect to Figs. 4A-4D. However, here, data blocks 1 to n are moved
internally within individual storage sub-units. Thus, according to one concrete
example (not illustrated), data stack D1-D8 circulates within memory 1, data
stack D9-D16 circulates within memory 2, and so forth.
The data memory in this third alternative can be constructed, e.g., of
circulating shift registers, charge coupled devices, or RAM controlled by data
sequencers and the like. The control device can be implemented through microprocessors, data sequencers, logic gates, gate aπays, etc.
II. SPECIFIC EMBODIMENTS OF THE INVENTION
As evident from the implementations discussed below, the hardware
design options for storing and accessing data according to the present invention
can be chosen from a variety of existing technologies. Cuπently, the most
preferable memory device hardware options are various types of semiconductor
memory. Advances in technology will surely expand the list of available
options.
A. First Embodiment: Shift Registers
The prefeπed manner of embodying a memory device using shift registers
is shown in Fig. 8A. Fig. 8A shows a long series of clocked shift registers 151
connected to form a ring 150. The ring 150 is constructed such that an entire
title is capable of being stored on the ring. Typically, to store a two-hour
movie, using MPEG2 as a data compression method, the ring should be able to
store approximately 180Gbits. The ring 150 is clocked by a clock source 152
which governs the rate of circulation of the data around the ring. The ring 150
is preferably clocked at such a rate to deliver (i.e., output) the title at a rate
required by the receiver. If the clock rate required cannot be attained by one shift register, many
registers in parallel can be used to obtain the rate required. Fig. 8B illustrates
one possible such embodiment in which two parallel rings are constructed, each
comprising clocked shift registers 151 connected in series. Fig. 8C illustrates
an embodiment in which shift registers 151 are interconnected in series and in
parallel to form the ring 150. The rate required is determined largely by the
requirements imposed by the service provider.
The data forming the title passes through the shift registers 151 serially
as a sequential bit stream. The data is passed from one register 151 to the next
in a manner explained in greater detail below.
The access to the title stored in the ring 150 is obtained via the data ports
153. An example of a port 153, coupled between two registers 151, is shown
in Fig. 8D. As illustrated there, the ports 153 are preferably composed of logic
circuitry 160-162. In addition to an input connected to the register 151
preceding it, each port 153 has an input for receiving a bit stream input 154.
Data for a new title is inserted into the ring 150 via inputs 154. In addition to
an output connected to the following register 151, each port 153 also has an
output 155 for copying the bit stream circulating in the ring 150. The number
(spacing) of ports 153 included in the ring 150 is based on an efficiency
determination, balancing overall cost against access time. The spacing of the ports 154 defines the time intervals between permissible data access, and thus
determines, in part, the waiting time between a subscriber request and
fulfillment. If the title is accessible in sufficiently small increments, the delay
time is imperceptible by humans.
The embodiment of Fig. 8D, described above, has no provision for eπor
coπection between registers. As shown in Fig. 8A, regenerators 156 can be
inserted periodically in the ring 150 such that the data stream stored in the ring
is regenerated as it passes through the regenerator. Fig. 8E shows in greater
detail an embodiment in which the regenerator 156 is formed as a data checker
156' inserted between the registers 151. Each data checker 156' preferably
contains logic circuitry 163-165 as well as a decoder 166 and an encoder 167.
These are preferably a Reed-Solomon decoder and a Reed-Solomon encoder,
respectively. The decoder 166 receives the data stream at an input, outputs any
eπors detected via an output 1, and outputs the decoded data to the logic
circuitry 163-165. The output 168 leads to operational surveillance units.
Similarly, the data stream is input into the encoder 1167 and is output as an
encoded data stream to the next following shift register 151. Regeneration
occurs as the bit stream passes through the Reed-Solomon decoders/encoders.
Thus, eπors can be coπected and/or brought to the attention of surveillance
equipment. In addition to eπor coπection, stored data can be processed in other
useful ways known to those skilled in the art. Thus, for example, data can be
encoded or encrypted. Data would be encoded to provide means to ensure its
reliability and to facilitate access to it. Data would be encrypted to prevent
unauthorized access to and use of the data.
Further, data may be compressed. Particularly with respect to video
information, the repetitive data content of video signals allows for significant
reduction in required data storage capacity by use of compression schemes.
Such schemes include MPEG, fractal and variable data rate coding. MPEG,
cuπently the most common scheme used in the telecommunications industry,
uses a discrete cosine transform and is a lossy compression scheme. MPEG
provides a compression ratio of approximately 38:1. Fractal compression
techniques, which have only recently become viable, typically provide
compression ratios of approximately 1500:1. References describing image
compression techniques include W.B Pennebaker et al., JPEG (Reinhold, New
York, NY, 1993); M.F. Barnsley et al., Fractal Image Compression (A.K.
Peters, Wellesley, MA 1993); Chiang et al. "Hierarchical Coding of Digital
Television", IEEE Communications Magazine. Vol 32, No. 5 (May 1994), pp.
38-45; Pancha et al. "MPEG Coding for Variable Bit Rate Video Transmission" ,
IEEE Communications Magazine. Vol. 32, No. 5 (May 1994), pp. 54-66. The techniques of encoding, encrypting and data compression just
described can be advantageously incorporated into the methods of storing data
described in the present application. Thus, if the data stored in the ring is
encoded, it can be more efficiently accessed and more reliably stored. By
encrypting the data, one provides added security against unauthorized access to
and use of the stored data. Finally, data compression provides significant
savings in hardware costs, since the storage rings can be constructed of far fewer
components.
As such, each ring is structured to allow data to be placed into the ring
and copied from the ring. Further, each ring is able to detect and repair eπors
automatically. If excessive eπors arise, this fact is signalled to the surveillance
equipment, such that the ring can be taken temporarily out of service and
repaired.
The details of construction of the circuitry of the ring 150 are not
particularly important in the present invention. The shift registers 151 can be
constructed simply of standard logic circuits. The logic family for consideration
of shift registers includes Emitter Coupled Logic (ECL), Transistor Transistor
Logic (TTL), and Metal Oxide Semiconductor (MOS). The logic family and the
approximate memory size of the shift register are shown in the table below. Shift Register Technology Memory Sizes
Logic Family Size In Bits
ECL 512
TTL 1,024
MOS 1,048,576
A memory device according to the first prefeπed embodiment may be
implemented through the utilization of off-the-shelf shift registers. For the
purpose of storing and accessing movies and the like, the MOS-type shift register
is prefeπed, due to its larger memory size.
The above embodiment is an example of a memory device in which the
data portals are fixed and the stored data stream is moved through the shift
registers 151 and through the data portals 153.
B. Second Embodiment: Charge Coupled Devices
A further, prefeπed alteπiative for embodying the memory device is to
employ CCDs 171 (Charge-Coupled Devices) as the registers 151, as shown in
Fig. 9, to form a ring memory device 170. If the ring 170 is constructed using
CCDs 171, then each CCD 171 must be pumped by a clock source 172. Further, some form of regenerating means 176 must be coupled between each
CCD 171. Possibilities for the regenerating means 176 include logic gates, as
above. The individual CCDs simply function as registers in this embodiment,
and the ring memory device 170, overall, functions similarly to the ring memory
device 150 described with reference to Fig. 8.
C. Third Embodiment: Delay Lines
A further implementation of a ring memory device, using delay lines 181
as the storage devices, is shown in Fig. 10. Access gates 182 connect the
individual delay lines 181 together. Preferably, the access gates 182 provide
data ingress lines 183, data egress lines 184 and access control lines 185. The
delay lines 181 themselves are preferably provided with egress ports 186 in
addition to those provided at the access gates. In operation, signals transmitted
over the access control lines 185 activate the ingress lines 183 or the egress lines
184, thereby allowing data to be input to or output from the ring memory device
180, respectively. If it is desired to output the title via one or more of the
additional egress ports 186, appropriate gates at ends of the egress ports 186 are
controlled accordingly. Otherwise, operation is analogous to that described with
respect to Fig. 8. D. Fourth Embodiment: Random Access Memories
■ Fig. 11 shows yet anotiier embodiment of the invention, which utilizes one
or more random access memories (RAM) to store the data coπesponding to a
tide. As shown, a RAM 190 has a series of address lines AQ - AN, a data line
D0, and a read/write line R/W. The RAM 190 is connected to a data sequencer
191 on the one hand and a control device 192 on the other hand. In operation,
the data sequencer 191 cycles through the address lines Ao - AN in accordance
with a clock signal input to the data sequencer 191. At the same time, the
control device 192 activates the RAM 190 by triggering the line R/W and the
data line D0. As a result, the data coπesponding to the tide stored in the RAM
190 is output in sequential order on the Data Out line. Various alternatives for
designing an embodiment utilizing RAM have been described with reference to
Figs. 3-7D, which need not be repeated here.
There are various types of RAM cuπendy on the market which could be
used to implement a memory structure as just described. These include Static
Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM),
and Pseudo Static Random Access Memory (PSRAM). Digital information
stored in SRAM is held in "static" locations. Several transistors are required to
form a memory cell that represents a binary digit. In order to store 1 million
bits of data, a device would need several million transistors. This packing density is achievable today. With respect to DRAM technology, the memory
capacity of DRAM devices has dramatically risen over the years. In fact, the
memory capacity has attained a level such that construction of a memory device
according to the present invention can be achieved readily, using off-the-shelf
components. DRAMs require periodic refresh of the data. The periodic
refreshing must be performed on a constant basis. As DRAM technology is
widely used in the computer industry today, the cost is relatively low in
comparison to other technologies. The class of PSRAM memory is a relatively
new technology. PSRAM technology represents a combination of the benefits
of SRAM and DRAM technology. PSRAM devices have the memory capacity
of DRAM devices, yet have an internal refresh capability, making them easy to
use. Advances in technology will surely provide additional memory options
suited to the present invention.
E. Fifth Embodiment: Storage Medium Confining Waves
Fig. 12 shows an embodiment of the invention which is constructed
without the use of individual storage devices. Instead, the memory storage
device utilizes a memory storage medium 200 capable of confining cyclically
propagating data.
More specifically, the data representing one or more tides, or a portion thereof, is embodied in the form of a propagating wave, where the wave defines
the stream of data. In the embodiment shown, the storage medium forms a ring
structure, and the wave travels in a circle. The propagating wave can, in theory,
be chosen from any known wave phenomenon, e.g., sound, electro-magnetic
waves including light, microwaves and radio waves, but, preferably light or
microwaves are employed. As known, such waves can be used to store
information content. Further, such waves, when trapped in a cavity, have the
property that they will sustain forward motion. These properties of waves can
thus be used to provide data memory for the present invention.
As shown in the figure, a wave 201 representing data is trapped in a ring
cavity 202. The speed of propagation is predetermined by the inherent
characteristics of the wave and the medium chosen. The type of storage medium
chosen is preferably one which minimizes propagation losses. Alternatively, or
in addition, the storage medium may be provided with repeaters or other
amplifying means (not shown) which compensate for any propagation losses.
The list of cuπentiy available media for providing such a ring cavity 202 include
electrical cable, coaxial cable, reverberation lines, delay lines, fiber-optical cable
and microwave cavities.
The ring cavity 202 is associated with a plurality of data portals 203
systematically aπanged around the periphery of the ring 200. As discussed in the description of the principle of the invention, the systematic aπangement of
portals 203 is one defined by modular arithmetic. The embodiment illustrated
has five data portals, with intervals between consecutive portals being equal
(although, a commercial embodiment would generally contain a far greater
number of portals). Individual portals can be configured either for inputting
data, or outputting data, or both. In practice, depending upon the choice of
storage medium, portals can be constructed of amplifiers, regenerators, beam
splitters, microwave cavity taps, and coaxial cable taps.
In operation, a controller (not shown) is used to select one or more of the
portals 203. When selected for data output, a given portal 203 passes the data
circulating in the storage medium, in the sequence and at the rate the data
appears at the portal. The data output travels along an appropriate exit signal
line 204, to be processed and routed to its eventual destination. If the portals are
constructed from one of the options listed above, their output is a copy of the
data circulating, so that the data wave remains circulating in the ring cavity after
output. When data output at a selected portal is complete, the controller may,
in appropriate instances, close the portal, so that no further data exits therefrom.
F. Sixth Embodiment: Storage Device Coupled to Output Controller
Fig. 13 shows a memory device with further details regarding portal selection. This embodiment is again an example of a memory device 300
provided with a plurality of fixed access portals 301-305 and with a capability
of storing a moving data stream. Data can be placed into the device 300 or
copied out, as required. The present discussion will focus on data output. The
internal portals 301-305 are connected to a controller 310, with each portal 301-
305 being associated witii one input 311-314 to the controller 310. The
controller 310 provides the selection and switching operability required to output
the stored data stream to external signal lines, via output points 351-352.
More specifically, logic circuitry, including AND gates 321-328 and OR
gates 331-332, connects the controller inputs 311-314 to the controller output
points 351-352. Each AND gate 321-328 has a first input originating at the
input 311-314 and a second input constituting a selection line from one of a
group of selectors 341-348. Further, each AND gate 321-328 has one output
line that forms an input into one of the OR gates 331-332. As shown, each OR
gate 331-332 receives inputs from a number of AND gates 321-328. The
number of AND gates 321-328 and the number of OR gates 331-332 is
determined by the number of desired controller inputs 311-314 and desired
controller output points 351-352, as shown.
In a given output operation, a signal from a given selector, e.g., 341,
triggers a coπesponding AND gate 321. The activated AND gate 321 then permits the data stream from its associated output portal 301 to pass through.
The selection signal 341 is chosen to synchronize with the circulating data
stream. Thus, if the tide is to be output from its beginning, the portal is selected
to be able to "capture" the data stream from its beginning. (If tide playback is
5 to commence from some other point, e.g., after a pause operation, the portal is
again selected accordingly to "capture" the data stream from the other point.)
Then, the data stream flows out from the portal 301 and through the appropriate
AND gate 321. The data stream then appears at the coπesponding input to one
of the OR gates 331, where it is passed through to the controller output point
lo 351.
Either simultaneously or at any time thereafter, a second selection signal
can prompt a second output operation. Thus, for example, in a simultaneous
output operation (or one coπesponding to the modulus of the ring), a second
is AND gate 325 that is connected to the same portal 301 as the one activated in
the first output operation is triggered by a further selection signal 345 to forward
the data stream. On the other hand, in an output operation occurring later in
time but before the first output operation is completed, a second AND gate, e.g.,
327, connected to a different portal, e.g., 303, is activated by a selection signal,
-to e.g., 347. As in the first output operation, the choice of the AND gate 327 and
the portal 303 is determined by the momentary location of the starting point of
the data stream in the ring 300. Given a sufficient number of portals 301-305 and output points 351-352,
the data stream stored in the memory 300 can be output to multiple destinations
in a multi-overlapped manner. Overlaps, as just described, can either be
complete or be partial. Fig. 14 illustrates one output scenario. As shown,
requests from subscribers A, B and C give rise to simultaneous, completely
overlapping, response outputs. Only one output portal, e.g., 301, need be
activated to respond to these three requests. The request from subscriber D is
somewhat delayed in time, however, so that the appropriate response output is
staggered relative to the response for subscribers A, B and C. Thus, the
controller 310 selects a different portal in the ring to respond to the request from
subscriber D. Requests from additional subscribers X, Y and Z are handled in
like manner.
In summary, the various data storage systems disclosed allow a wide assortment of tides (e.g., movies, educational-, entertainment-, consumer-, and
business-related information, and any information that can be converted into a
stream of data) to be stored and retrieved by a wide audience with great
flexibility and minimal contention between users for the tides offered.
The above description of the prefeπed embodiments has been given by
way of example. From the disclosure given, those skilled in the art will not only
understand the present invention and its attendant advantages, but will also find apparent various changes and modifications that can be made to the methods and
structures disclosed. It is sought, therefore, to cover all such changes and
modifications as fall within the spirit and scope of the invention, as defined by
the appended claims, and equivalents thereof.

Claims

CLAIMSWe claim:
1. A method comprising the steps of:
providing data memory in a systematic, cyclical aπangement;
providing plural data portals in an aπangement defined by modular
arithmetic; and
providing sequential, relative movement between the data memory and the
data portals.
2. The method according to claim 1, wherein
said step of providing data memory comprises providing stored data.
3. The method according to claim 1, wherein
said step of providing data memory comprises providing data locations.
4. The method according to claim 1 , wherein
said step of providing data memory comprises providing systematically
connected plural storage devices.
5. The method according to claim 7, wherein said step of providing plural storage devices comprises aπanging the
plural storage devices in an aπangement defined by modular arithmetic.
6. The method according to claim 5, wherein the aπangement of plural storage
devices is defined by:
Si s Si+M ,
where Sj = a storage device in the aπangement, and
M = the total number of the plural storage devices provided.
7. The method according to claim 6, wherein a relationship between consecutive
storage devices is defined by:
Figure imgf000050_0001
where Sj = a storage device in the aπangement,
Si+ , = a next storage device relative to S;, and
f(t) = a function of time.
8. The method according to claim 7, wherein:
f(t) = C, where C = a constant.
9. The method according to claim 1, wherein the aπangement of plural data
portals is defined by:
Figure imgf000051_0001
where Pj = a data portal in the aπangement, and
M = the total number of the plural data portals provided.
10. The method according to claim 9, a relationship between consecutive data
portals is defined by:
Figure imgf000051_0002
where Pj = a data portal in the aπangement,
Pj+ j = a next data portal relative to Pj, and
f(t) = a function of time.
11. The method according to claim 10, wherein:
f(t) = C, where C = a constant.
12. The method according to claim 1, wherein:
the data portals are fixed; and
the data memory is moved past the data portals.
13. The method according to claim 12, wherein:
the data memory is moved past each of the data portals.
14. The method according to claim 12, wherein:
the data memory is moved from one of the data portals to another one of
the data portals.
15. The method according to claim 1, wherein:
the data memory is in fixed locations; and
the data portals move from one fixed location to other fixed locations.
16. The method according to claim 15, wherein:
the data portals move from the one fixed location to one other fixed
location.
17. The method according to claim 1, wherein:
the data memory is moved in a first predetermined fashion; and
the data portals are moved in a second predetermined fashion.
18. The method according to claim 2, wherein:
the stored data passes through at least some of the data portals.
19. The method according to claim 2, wherein:
the stored data does not pass through at least some of the data portals.
20. The method according to claim 1, wherein the relative movement between
the data memory and the data portals is continual.
21. The method according to claim 1, wherein the relative movement between
the data memory and the data portals is intermittent.
22. A method according to claim 1 , further comprising the step of:
outputting the data from at least one of the plural data outputs.
23. A method according to claim 1, further comprising the step of:
selecting at least one of the data portals.
24. A method according to claim 23, wherein the data memory comprises stored
data.
25. A method according to claim 24, further comprising the step of:
outputting the data at the selected at least one data portal.
26. A method according to claim 25, wherein said step of outputting the data
comprises:
reproducing the data; and
delivering the reproduced data from the selected at least one data portal.
27. A method according to claim 26, wherein the data is reproduced at and
delivered from the selected at least one data portal.
28. A method according to claim 23, further comprising the step of:
after said selecting step, inputting data into the data memory via the at
least one data portal.
29. A method according to claim 23, further comprising the step of:
after said selecting step, outputting data from the data memory via the at
least one data portal.
30. A method according to claim 29, wherein a first one of the data portals is
selected at a first time, to output the data via the first data portal, and a second
one of the data portals is selected at a second time, to output the data via the
second data portal.
31. A method according to claim 1, further comprising the step of:
selecting certain ones of the plural data portals.
32. A method according to claim 31 , wherein the data memory comprises stored
data.
33. A method according to claim 32, further comprising the step of:
outputting the data at the selected data portals.
34. A method according to claim 33, wherein said step of outputting the data
comprises:
reproducing die data; and
delivering the reproduced data from the selected data portals.
35. A method according to claim 34, wherein the data is both reproduced at and
delivered from individual ones of the selected data portals.
36. A method according to claim 32, further comprising the step of:
during said selecting step, outputting the data from the data memory via
the selected data portals.
37. A method according to claim 31, wherein the selected data portals are
selected independentiy of one another.
38. A method according to claim 37, wherein the selected data portals are
selected independentiy with respect to time.
39. A method according to claim 38, wherein a first one of the selected data portals is selected at a first time and a second one of the selected data portals is
selected at a second time.
40. A method of efficiendy disseminating data, comprising the steps of:
providing stored data and a plurality of data portals aπanged in a manner
defined by modular arithmetic;
establishing relative, cyclical movement between the stored data and the
data portals; and
selecting at least one of the data portals and outputting the data at the
selected at least one data portal in accordance with the relative, cyclical
movement.
41. A method of accessing information held in data locations, comprising the
steps of:
providing a systematic aπangement of plural data locations;
providing a plurality of data portals aπanged in a manner defined by
modular arithmetic;
establishing relative, cyclical movement between the data locations and the
data portals; and
selecting one of the data portals and accessing the information held in the
data locations in accordance with the relative, cyclical movement.
42. A memory device comprising:
a data storage unit;
a plurality of data portals aπanged in a manner defined by modular
arithmetic and connected to said data storage unit; and
means for establishing relative movement between data stored in said data
storage unit and said data portals.
43. A memory device according to claim 42, wherein:
said data storage unit comprises a plurality of systematically connected
storage devices.
44. A memory device according to claim 43, wherein:
said storage devices are aπanged in said data storage unit to form a data
storing loop.
45. A memory device according to claim 43, wherein:
said storage devices are aπanged in said data storage unit to form a ring.
46. A memory device according to claim 43, wherein:
said storage devices are connected together in series.
47. A memory device according to claim 43, wherein: at least a portion of said storage devices are connected together in series.
48. A memory device according to claim 44, wherein:
said storage devices are connected together in series.
49. A memory device according to claim 45, wherein:
said storage devices are connected together in series.
50. A memory device according to claim 43, wherein:
said storage devices are selected from the group consisting of shift
registers, static random access memories, dynamic random access memories,
pseudo static random access memories, delay lines, charge coupled devices,
read-only memories, programmable read-only memories, and non-volatile
memories.
51. A memory device according to claim 43, wherein:
at least a portion of said storage devices are provided with said data
portals.
52. A memory device according to claim 43, wherein:
at least a portion of said data portals are respectively inserted between said
storage devices in said data storage unit.
53. A memory device according to claim 43, wherein:
at least a portion of said data portals are respectively connected to ones
of said storage devices, such that said portion of said data portals are appended
onto said data storage unit.
54. A memory device according to claim 42, wherein:
said data portals comprise at least one data replicator.
55. A memory device according to claim 42, wherein:
at least some of said data portals comprise data replicators.
56. A memory device according to claim 42, wherein said data portals are
physical locations.
57. A memory device according to claim 42, wherein at least some of said data
portals are selected from the group consisting of latches, logic gates,
regenerators, and amplifiers.
58. A memory device according to claim 42, wherein said data portals are
logical locations.
59. A memory device according to claim 42, wherein at least a portion of said data portals are connected into said data storage unit.
60. A memory device according to claim 42, wherein at least a portion of said
data portals are appended onto said data storage unit.
61. A memory device according to claim 42, wherein said means for
establishing relative movement comprises a clock.
62. A memory device according to claim 61, wherein said clock comprises data
shifting circuitry.
63. A memory device according to claim 61, wherein said clock comprises
portal shifting circuitry.
64. A memory device according to claim 42, wherein said means for
establishing relative movement are selected from the group consisting of n-phase
clocks, timing generators, address generators, data multiplexers, and a
microprocessor.
65. A memory device according to claim 42, further comprising:
at least one data replicator connected to said data storage unit and to at
least one of said data portals.
66. A memory device according to claim 42, further comprising:
plural data replicators connected to said data storage unit and to respective
ones of said data portals.
67. A memory device according to claim 42, further comprising:
a controller, connected to said plurality of data portals, configured to
control data traffic at said data portals.
68. A memory device according to claim 42, further comprising:
a control device configured to establish a connection between said data
portals and at least one output line.
69. A memory device according to claim 42, further comprising:
a control device configured to establish a connection between said data
portals and at least one input line.
70. A memory device according to claim 42, further comprising:
a control device configured to select among said data portals in accordance
with an externally supplied selection signal.
71. A memory device comprising:
a data storage unit having a systematic aπangement of data locations for storing data;
a plurality of data portals aπanged in a manner defined by modular
arithmetic and connected to said data locations; and
means for establishing relative movement between said data locations and
said data portals.
72. A memory device comprising:
a data storage unit;
a plurality of data portals connected to said data storage unit in a manner
defined by modular arithmetic; and
a data pump that establishes relative movement between data stored in said
data storage unit and said data portals.
73. A memory device comprising:
a data storage unit having a systematic aπangement of data locations for
storing data;
a plurality of data portals connected to said data locations and aπanged
in a manner defined by modular arithmetic; and
a generator configured to establish relative movement between said data
locations and said data portals.
74. A memory device comprising: a memory storage medium for confining cyclically propagating data; and
a plurality of data portals connected to said storage medium and aπanged
in a manner defined by modular arithmetic.
75. A memory device according to claim 74, wherein said memory storage
medium is selected from the group consisting of electrical cable, coaxial cable,
reverberation lines, delay lines, fiber-optical cable, and microwave cavities.
76. A memory device according to claim 74, wherein at least some of said data
portals are configured to tap the propagating data.
77. A memory device according to claim 74, wherein at least some of said data
portals are selected from the group consisting of amplifiers, regenerators, beam
splitters, microwave cavity taps, and coaxial cable taps.
78. A method comprising the steps of:
providing data memory in a systematic, cyclical aπangement;
providing a systematic aπangement of plural data outputs; and
providing sequential, relative movement between the data memory and the
data outputs.
79. The method according to claim 78, wherein said step of providing data memory comprises providing stored data.
80. The method according to claim 78, wherein
said step of providing data memory comprises providing data locations.
81. The method according to claim 78, wherein:
the data outputs are fixed; and
the data memory is moved past the data outputs.
82. The method according to claim 81, wherein:
the data memory is moved past each of the data outputs.
83. The method according to claim 81, wherein:
the data memory is moved from one of the data outputs to another one of
the data outputs.
84. The metiiod according to claim 78, wherein:
the data memory is in fixed locations; and
the data outputs move from one fixed location to other fixed locations.
85. The method according to claim 84, wherein:
the data outputs move from the one fixed location to one other fixed location.
86. The method according to claim 78, wherein:
the data memory is moved in a first predetermined fashion; and
the data outputs are moved in a second predetermined fashion.
87. The method according to claim 79, wherein:
the stored data passes through at least some of the data portals.
88. The method according to claim 79, wherein:
the stored data does not pass through at least some of the data portals.
89. The method according to claim 78, wherein the relative movement between
the data memory and the data outputs is continual.
90. The method according to claim 78, wherein the relative movement between
the data memory and the data outputs is intermittent.
91. A method according to claim 78, wherein the data memory comprises stored
data.
92. A method according to claim 91, further comprising the step of: outputting the data from at least one of the plural data outputs.
93. A method according to claim 91, further comprising the steps of:
reproducing the data; and
delivering the reproduced data from the cyclical aπangement at a selected
one of the data outputs.
94. A metiiod according to claim 91, further comprising the steps of:
selecting a first one of the data outputs at a first time, to output the data
via the first data output, and
selecting a second one of the data outputs at a second time, to output the
data via the second data output.
95. A method of efficiendy disseminating data, comprising the steps of:
providing a systematic aπangement of stored data and a systematic
aπangement of plural data outputs;
establishing relative, cyclical movement between the stored data and the
data outputs; and
selecting at least one of the data outputs and outputting the data at the
selected at least one data output in accordance with die relative, cyclical
movement.
96. A method of accessing information held in data locations, comprising the
steps of:
providing a systematic aπangement of plural data locations;
providing a systematic aπangement of plural data outputs;
establishing relative, cyclical movement between the data locations and the
data outputs; and
selecting one of the data outputs and accessing the information held in the
data locations in accordance with the relative, cyclical movement.
97. A memory device comprising:
a data storage unit;
a systematic aπangement of plural data outputs connected to said data
storage unit; and
means for establishing relative movement between data stored in said data
storage unit and said data outputs.
98. A memory device according to claim 97, wherein:
said data storage unit comprises a plurality of systematically connected
storage devices.
99. A memory device according to claim 98, wherein:
said storage devices are aπanged in said data storage unit to form a data storing loop.
100.. A memory device according to claim 98, wherein:
said storage devices are aπanged in said data storage unit to form a ring.
101. A memory device according to claim 98, wherein:
at least a portion of said storage devices are connected together in series.
102. A memory device according to claim 98, wherein:
said storage devices selected from the group consisting of shift registers,
static random access memories, dynamic random access memories, pseudo static
random access memories, delay lines, charge coupled devices, read-only
memories, programmable read-only memories, and non-volatile memories.
103. A memory device according to claim 98, wherein:
at least a portion of said storage devices are provided with said data
outputs.
104. A memory device according to claim 98, wherein:
at least a portion of said data outputs are respectively inserted between
said storage devices in said data storage unit.
105. A memory device according to claim 98, wherein:
at least a portion of said data outputs are respectively connected to ones
of said storage devices, such that said portion of said data outputs are appended
onto said data storage unit.
106. A memory device according to claim 97, wherein:
at least some of said data outputs comprise data replicators.
107. A memory device according to claim 97, wherein said data outputs are
physical locations.
108. A memory device according to claim 97, wherein at least some of said
data outputs are selected from the group consisting of latches, logic gates,
regenerators, and amplifiers.
109. A memory device according to claim 97, wherein said data outputs are
logical locations.
110. A memory device according to claim 97, wherein at least a portion of said
data outputs are connected into said data storage unit.
111. A memory device according to claim 97, wherein at least a portion of said data outputs are appended onto said data storage unit.
112. A memory device according to claim 97, wherein said means for
establishing relative movement comprises a clock.
113. A memory device according to claim 112, wherein said clock comprises
data shifting circuitry.
114. A memory device according to claim 112, wherein said clock comprises
output shifting circuitry.
115. A memory device according to claim 97, wherein said means for
establishing relative movement are selected from the group consisting of n-phase
clocks, timing generators, address generators, data multiplexers and a
microprocessor.
116. A memory device according to claim 97, further comprising:
at least one data replicator connected to said data storage unit and to at
least one of said data outputs.
117. A memory device according to claim 97, further comprising:
a controller, connected to said plurality of data outputs, configured to control data traffic at said data outputs.
118. A memory device according to claim 97, further comprising:
a control device configured to establish a connection between said data
outputs and at least one output line.
119. A memory device according to claim 97, further comprising:
a control device configured to select among said data outputs in
accordance with an externally supplied selection signal.
120. A memory device comprising:
a data storage unit having a systematic aπangement of data locations for
storing data;
a systematic aπangement of plural data outputs connected to said data
locations; and
means for establishing relative movement between said data locations and
said data outputs.
121. A memory device comprising:
a data storage unit;
a systematic aπangement of plural data outputs connected to said data
storage unit; and a data pump mat establishes relative movement between data stored in said
data storage unit and said data outputs.
122. A memory device comprising:
a data storage unit having a systematic aπangement of data locations for
storing data;
a systematic aπangement of plural data outputs connected to said data
locations; and
a generator configured to establish relative movement between said data
locations and said data outputs.
123. A memory device comprising:
a memory storage medium for confining cyclically propagating data; and
a systematic aπangement of plural data outputs connected to said storage
medium.
124. A memory device according to claim 123, wherein said memory storage
medium is selected from the group consisting of electrical cable, coaxial cable,
reverberation lines, delay lines, fiber-optical cable, and microwave cavities.
125. A memory device according to claim 123, wherein at least some of said
data outputs are configured to copy the propagating data.
126. A memory device according to claim 123, wherein at least some of said
data outputs are selected from the group consisting of amplifiers, regenerators,
beam splitters, microwave cavity taps, and coaxial cable taps.
PCT/US1995/006139 1994-05-25 1995-05-19 Memory device WO1995032505A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP95920463A EP0763243B1 (en) 1994-05-25 1995-05-19 Memory device
DE69505661T DE69505661T2 (en) 1994-05-25 1995-05-19 STORAGE DEVICE
AU26070/95A AU711519B2 (en) 1994-05-25 1995-05-19 Memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/249,265 US6356973B1 (en) 1993-10-15 1994-05-25 Memory device having a cyclically configured data memory and having plural data portals for outputting/inputting data
US08/249,265 1994-05-25

Publications (1)

Publication Number Publication Date
WO1995032505A1 true WO1995032505A1 (en) 1995-11-30

Family

ID=22942722

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/006139 WO1995032505A1 (en) 1994-05-25 1995-05-19 Memory device

Country Status (6)

Country Link
US (2) US6356973B1 (en)
EP (1) EP0763243B1 (en)
AU (1) AU711519B2 (en)
CA (1) CA2191113A1 (en)
DE (1) DE69505661T2 (en)
WO (1) WO1995032505A1 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU6863998A (en) * 1997-03-11 1998-09-29 Computer Information And Sciences, Inc. System and method for image compression and decompression
DE60115154T2 (en) * 2000-06-19 2006-08-10 Broadcom Corp., Irvine Method and device for data frame forwarding in an exchange
US7707351B2 (en) * 2002-10-31 2010-04-27 Ring Technology Enterprises Of Texas, Llc Methods and systems for an identifier-based memory section
US6879526B2 (en) * 2002-10-31 2005-04-12 Ring Technology Enterprises Llc Methods and apparatus for improved memory access
US7415565B2 (en) * 2002-10-31 2008-08-19 Ring Technology Enterprises, Llc Methods and systems for a storage system with a program-controlled switch for routing data
US7197662B2 (en) * 2002-10-31 2007-03-27 Ring Technology Enterprises, Llc Methods and systems for a storage system
EP1606823B1 (en) * 2003-03-14 2009-11-18 Nxp B.V. Two-dimensional data memory
US7401179B2 (en) * 2005-01-21 2008-07-15 Infineon Technologies Ag Integrated circuit including a memory having low initial latency
US7634622B1 (en) 2005-06-14 2009-12-15 Consentry Networks, Inc. Packet processor that generates packet-start offsets to immediately store incoming streamed packets using parallel, staggered round-robin arbitration to interleaved banks of memory
US7577868B2 (en) * 2005-09-30 2009-08-18 Lockheed Martin Corporation No data loss IT disaster recovery over extended distances
US7848142B2 (en) 2007-10-31 2010-12-07 Micron Technology, Inc. Fractional bits in memory cells
US7742335B2 (en) 2007-10-31 2010-06-22 Micron Technology, Inc. Non-volatile multilevel memory cells
JP6115308B2 (en) * 2013-05-22 2017-04-19 富士通株式会社 Information processing system, information processing system control method, and control program
GB2523165B (en) * 2014-02-17 2018-09-26 Technetix Bv Cable television cable tap device
US10313641B2 (en) 2015-12-04 2019-06-04 Google Llc Shift register with reduced wiring complexity
JP6902000B2 (en) * 2018-07-10 2021-07-14 株式会社東芝 Arithmetic logic unit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975605A (en) * 1989-11-13 1990-12-04 Intel Corporation Synchronous delay line with automatic reset

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3713096A (en) 1971-03-31 1973-01-23 Ibm Shift register interconnection of data processing system
US3748647A (en) 1971-06-30 1973-07-24 Ibm Toroidal interconnection system
US3735362A (en) 1971-09-22 1973-05-22 Ibm Shift register interconnection system
US3812476A (en) 1971-11-16 1974-05-21 Texas Instruments Inc Memory device
US4064556A (en) 1975-06-23 1977-12-20 Sperry Rand Corporation Packed loop memory with data manipulation capabilities
US4065756A (en) 1976-03-15 1977-12-27 Burroughs Corporation Associative memory with neighboring recirculated paths offset by one bit
GB1580057A (en) 1976-07-16 1980-11-26 Post Office Information handling apparatus
IT1118355B (en) 1979-02-15 1986-02-24 Cselt Centro Studi Lab Telecom INTERCONNECTION SYSTEM BETWEEN PROCESSORS
US4363125A (en) 1979-12-26 1982-12-07 International Business Machines Corporation Memory readback check method and apparatus
US4506387A (en) 1983-05-25 1985-03-19 Walter Howard F Programming-on-demand cable system and method
US4792848A (en) 1986-12-02 1988-12-20 Scientific-Atlanta, Inc. Cable television impulse pay per view system
US4829372A (en) 1987-08-20 1989-05-09 Telaction Corporation Presentation player
US5119481A (en) 1987-12-22 1992-06-02 Kendall Square Research Corporation Register bus multiprocessor system with shift
US5084839A (en) 1990-02-05 1992-01-28 Harris Corporation Variable length shift register
US5093718A (en) 1990-09-28 1992-03-03 Inteletext Systems, Inc. Interactive home information system
US5526034A (en) 1990-09-28 1996-06-11 Ictv, Inc. Interactive home information system with signal assignment
US5268656A (en) * 1992-11-05 1993-12-07 At&T Bell Laboratories Programmable clock skew adjustment circuit
US5357276A (en) 1992-12-01 1994-10-18 Scientific-Atlanta, Inc. Method of providing video on demand with VCR like functions
EP0609054A3 (en) 1993-01-25 1996-04-03 Matsushita Electric Ind Co Ltd Method and apparatus for recording or reproducing video data on or from storage media.
US5440334A (en) 1993-02-01 1995-08-08 Explore Technology, Inc. Broadcast video burst transmission cyclic distribution apparatus and method
US5414455A (en) 1993-07-07 1995-05-09 Digital Equipment Corporation Segmented video on demand system
US5477263A (en) 1994-05-26 1995-12-19 Bell Atlantic Network Services, Inc. Method and apparatus for video on demand with fast forward, reverse and channel pause

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975605A (en) * 1989-11-13 1990-12-04 Intel Corporation Synchronous delay line with automatic reset

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"BIT INTERLEAVING IN ELECTRONIC SHIFT REGISTER STORE", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 24, no. 7B, December 1981 (1981-12-01), NEW YORK US, pages 3577 - 3578 *
MILLMAN ET AL.: "INTEGRATED ELECTRONICS", 1985, MC GRAW-HILL, SINGAPORE *

Also Published As

Publication number Publication date
AU2607095A (en) 1995-12-18
EP0763243B1 (en) 1998-10-28
CA2191113A1 (en) 1995-11-30
US20020062420A1 (en) 2002-05-23
DE69505661T2 (en) 1999-07-08
US6779073B2 (en) 2004-08-17
EP0763243A1 (en) 1997-03-19
DE69505661D1 (en) 1998-12-03
AU711519B2 (en) 1999-10-14
US6356973B1 (en) 2002-03-12

Similar Documents

Publication Publication Date Title
EP0763243B1 (en) Memory device
EP0697703B1 (en) Video storage apparatus and method
EP0707423B1 (en) Video signal reproducing device
EP0804028B1 (en) Near video on-demand system and televising method of the same
KR100293856B1 (en) Program server for interactive television systems
EP0686908B1 (en) Server for video on demand system
EP0723731B1 (en) Information service control point
US5621799A (en) Scrambled transmission system
MX9801217A (en) Method and device for multi-angle connecting and encoding bit stream.
WO1999035562A2 (en) Incremental archiving and restoring of data in a multimedia server
JPH07272404A (en) Video data storage system
JPH11509993A (en) Information on demand system
JPH11509951A (en) Storage media device
JPH0983867A (en) Edit system and video signal transmission system
US6144796A (en) Video data system
EP0975164B1 (en) Imaging system and method
JPH11509994A (en) Navigation system
JP3401978B2 (en) Audio / video signal providing device
JP2002344901A (en) Data reproducing device and data reproducing method
JPS63276989A (en) Video signal multiplex recoder
Fleming DialM'for Movies: New Technologies, New Relations
Papanikolaou Server and management system design for a distributed VoD service
JPH09116870A (en) Reproduction device
JPH08317368A (en) Data transmitter
JPH09224205A (en) Parallel storage device for plural video images

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AM AT AU BB BG BR BY CA CH CN CZ DE DK EE ES FI GB GE HU IS JP KE KG KP KR KZ LK LR LT LU LV MD MG MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TT UA UG UZ VN

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): KE MW SD SZ UG AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2191113

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 1995920463

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1995920463

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWG Wipo information: grant in national office

Ref document number: 1995920463

Country of ref document: EP